Intel 64 and IA-32 Architectures. Software Developer’s Manual (Collection, 2023)

INSTRUCTION SET REFERENCE, M-U

MOVDQA,VMOVDQA32/64—Move Aligned Packed Integer Values

Opcode/

Op/En

64/32

CPUID

Description

Instruction

bit Mode

Feature

Support

Flag

66 0F 6F /r

V/V

SSE2

Move aligned packed integer values from

MOVDQA xmm1, xmm2/m128

xmm2/mem to xmm1.

66 0F 7F /r

V/V

SSE2

Move aligned packed integer values from xmm1

MOVDQA xmm2/m128, xmm1

to xmm2/mem.

VEX.128.66.0F.WIG 6F /r

V/V

AVX

Move aligned packed integer values from

VMOVDQA xmm1, xmm2/m128

xmm2/mem to xmm1.

VEX.128.66.0F.WIG 7F /r

V/V

AVX

Move aligned packed integer values from xmm1

VMOVDQA xmm2/m128, xmm1

to xmm2/mem.

VEX.256.66.0F.WIG 6F /r

V/V

AVX

Move aligned packed integer values from

VMOVDQA ymm1, ymm2/m256

ymm2/mem to ymm1.

VEX.256.66.0F.WIG 7F /r

V/V

AVX

Move aligned packed integer values from ymm1

VMOVDQA ymm2/m256, ymm1

to ymm2/mem.

EVEX.128.66.0F.W0 6F /r

V/V

AVX512VL

Move aligned packed doubleword integer values

VMOVDQA32 xmm1 {k1}{z},

AVX512F

from xmm2/m128 to xmm1 using writemask

xmm2/m128

k1.

EVEX.256.66.0F.W0 6F /r

V/V

AVX512VL

Move aligned packed doubleword integer values

VMOVDQA32 ymm1 {k1}{z},

AVX512F

from ymm2/m256 to ymm1 using writemask

ymm2/m256

k1.

EVEX.512.66.0F.W0 6F /r

V/V

AVX512F

Move aligned packed doubleword integer values

VMOVDQA32 zmm1 {k1}{z},

from zmm2/m512 to zmm1 using writemask k1.

zmm2/m512

EVEX.128.66.0F.W0 7F /r

V/V

AVX512VL

Move aligned packed doubleword integer values

VMOVDQA32 xmm2/m128 {k1}{z},

AVX512F

from xmm1 to xmm2/m128 using writemask

xmm1

k1.

EVEX.256.66.0F.W0 7F /r

V/V

AVX512VL

Move aligned packed doubleword integer values

VMOVDQA32 ymm2/m256 {k1}{z},

AVX512F

from ymm1 to ymm2/m256 using writemask

ymm1

k1.

EVEX.512.66.0F.W0 7F /r

V/V

AVX512F

Move aligned packed doubleword integer values

VMOVDQA32 zmm2/m512 {k1}{z},

from zmm1 to zmm2/m512 using writemask k1.

zmm1

EVEX.128.66.0F.W1 6F /r

V/V

AVX512VL

Move aligned packed quadword integer values

VMOVDQA64 xmm1 {k1}{z},

AVX512F

from xmm2/m128 to xmm1 using writemask

xmm2/m128

k1.

EVEX.256.66.0F.W1 6F /r

V/V

AVX512VL

Move aligned packed quadword integer values

VMOVDQA64 ymm1 {k1}{z},

AVX512F

from ymm2/m256 to ymm1 using writemask

ymm2/m256

k1.

EVEX.512.66.0F.W1 6F /r

V/V

AVX512F

Move aligned packed quadword integer values

VMOVDQA64 zmm1 {k1}{z},

from zmm2/m512 to zmm1 using writemask k1.

zmm2/m512

EVEX.128.66.0F.W1 7F /r

V/V

AVX512VL

Move aligned packed quadword integer values

VMOVDQA64 xmm2/m128 {k1}{z},

AVX512F

from xmm1 to xmm2/m128 using writemask

xmm1

k1.

EVEX.256.66.0F.W1 7F /r

V/V

AVX512VL

Move aligned packed quadword integer values

VMOVDQA64 ymm2/m256 {k1}{z},

AVX512F

from ymm1 to ymm2/m256 using writemask

ymm1

k1.

EVEX.512.66.0F.W1 7F /r

V/V

AVX512F

Move aligned packed quadword integer values

VMOVDQA64 zmm2/m512 {k1}{z},

from zmm1 to zmm2/m512 using writemask k1.

zmm1

MOVDQA,VMOVDQA32/64—Move Aligned Packed Integer Values

Vol. 2B

4-67

INSTRUCTION SET REFERENCE, M-U

Instruction Operand Encoding

Op/En

Tuple Type

Operand 1

Operand 2

Operand 3

Operand 4

N/A

ModRM:reg (w)

ModRM:r/m (r)

N/A

ModRM:r/m (w)

ModRM:reg (r)

N/A

Full Mem

ModRM:reg (w)

ModRM:r/m (r)

N/A

Full Mem

ModRM:r/m (w)

ModRM:reg (r)

N/A

Description

Note: VEX.vvvv and EVEX.vvvv are reserved and must be 1111b otherwise instructions will #UD.

EVEX encoded versions:

Moves 128, 256 or 512 bits of packed doubleword/quadword integer values from the source operand (the second

operand) to the destination operand (the first operand). This instruction can be used to load a vector register from

an int32/int64 memory location, to store the contents of a vector register into an int32/int64 memory location, or

to move data between two ZMM registers. When the source or destination operand is a memory operand, the

operand must be aligned on a 16 (EVEX.128)/32(EVEX.256)/64(EVEX.512)-byte boundary or a general-protection

exception (#GP) will be generated. To move integer data to and from unaligned memory locations, use the

VMOVDQU instruction.

The destination operand is updated at 32-bit (VMOVDQA32) or 64-bit (VMOVDQA64) granularity according to the

writemask.

VEX.256 encoded version:

Moves 256 bits of packed integer values from the source operand (second operand) to the destination operand

(first operand). This instruction can be used to load a YMM register from a 256-bit memory location, to store the

contents of a YMM register into a 256-bit memory location, or to move data between two YMM registers.

When the source or destination operand is a memory operand, the operand must be aligned on a 32-byte boundary

or a general-protection exception (#GP) will be generated. To move integer data to and from unaligned memory

locations, use the VMOVDQU instruction. Bits (MAXVL-1:256) of the destination register are zeroed.

128-bit versions:

Moves 128 bits of packed integer values from the source operand (second operand) to the destination operand

(first operand). This instruction can be used to load an XMM register from a 128-bit memory location, to store the

contents of an XMM register into a 128-bit memory location, or to move data between two XMM registers.

When the source or destination operand is a memory operand, the operand must be aligned on a 16-byte boundary

or a general-protection exception (#GP) will be generated. To move integer data to and from unaligned memory

locations, use the VMOVDQU instruction.

128-bit Legacy SSE version: Bits (MAXVL-1:128) of the corresponding ZMM destination register remain

unchanged.

VEX.128 encoded version: Bits (MAXVL-1:128) of the destination register are zeroed.

4-68

Vol. 2B

MOVDQA,VMOVDQA32/64—Move Aligned Packed Integer Values

INSTRUCTION SET REFERENCE, M-U

Operation

VMOVDQA32 (EVEX encoded versions, register-copy form)

(KL, VL) = (4, 128), (8, 256), (16, 512)

FOR j := 0 TO KL-1

i := j * 32

IF k1[j] OR *no writemask*

THEN DEST[i+31:i] := SRC[i+31:i]

ELSE

IF *merging-masking*

; merging-masking

THEN *DEST[i+31:i] remains unchanged*

ELSE DEST[i+31:i] := 0

; zeroing-masking

FI;

ENDFOR

DEST[MAXVL-1:VL] := 0

VMOVDQA32 (EVEX encoded versions, store-form)

(KL, VL) = (4, 128), (8, 256), (16, 512)

FOR j := 0 TO KL-1

i := j * 32

IF k1[j] OR *no writemask*

THEN DEST[i+31:i] := SRC[i+31:i]

ELSE *DEST[i+31:i] remains unchanged*

; merging-masking

FI;

ENDFOR;

VMOVDQA32 (EVEX encoded versions, load-form)

(KL, VL) = (4, 128), (8, 256), (16, 512)

FOR j := 0 TO KL-1

i := j * 32

IF k1[j] OR *no writemask*

THEN DEST[i+31:i] := SRC[i+31:i]

ELSE

IF *merging-masking*

; merging-masking

THEN *DEST[i+31:i] remains unchanged*

ELSE DEST[i+31:i] := 0

; zeroing-masking

FI;

ENDFOR

DEST[MAXVL-1:VL] := 0

MOVDQA,VMOVDQA32/64—Move Aligned Packed Integer Values

Vol. 2B

4-69

INSTRUCTION SET REFERENCE, M-U

VMOVDQA64 (EVEX encoded versions, register-copy form)

(KL, VL) = (2, 128), (4, 256), (8, 512)

FOR j := 0 TO KL-1

i := j * 64

IF k1[j] OR *no writemask*

THEN DEST[i+63:i] := SRC[i+63:i]

ELSE

IF *merging-masking*

; merging-masking

THEN *DEST[i+63:i] remains unchanged*

ELSE DEST[i+63:i] := 0

; zeroing-masking

FI;

ENDFOR

DEST[MAXVL-1:VL] := 0

VMOVDQA64 (EVEX encoded versions, store-form)

(KL, VL) = (2, 128), (4, 256), (8, 512)

FOR j := 0 TO KL-1

i := j * 64

IF k1[j] OR *no writemask*

THEN DEST[i+63:i] := SRC[i+63:i]

ELSE *DEST[i+63:i] remains unchanged*

; merging-masking

FI;

ENDFOR;

VMOVDQA64 (EVEX encoded versions, load-form)

(KL, VL) = (2, 128), (4, 256), (8, 512)

FOR j := 0 TO KL-1

i := j * 64

IF k1[j] OR *no writemask*

THEN DEST[i+63:i] := SRC[i+63:i]

ELSE

IF *merging-masking*

; merging-masking

THEN *DEST[i+63:i] remains unchanged*

ELSE DEST[i+63:i] := 0

; zeroing-masking

FI;

ENDFOR

DEST[MAXVL-1:VL] := 0

VMOVDQA (VEX.256 encoded version, load - and register copy)

DEST[255:0] := SRC[255:0]

DEST[MAXVL-1:256] := 0

VMOVDQA (VEX.256 encoded version, store-form)

DEST[255:0] := SRC[255:0]

VMOVDQA (VEX.128 encoded version)

DEST[127:0] := SRC[127:0]

DEST[MAXVL-1:128] := 0

VMOVDQA (128-bit load- and register-copy- form Legacy SSE version)

DEST[127:0] := SRC[127:0]

DEST[MAXVL-1:128] (Unmodified)

4-70

Vol. 2B

MOVDQA,VMOVDQA32/64—Move Aligned Packed Integer Values

INSTRUCTION SET REFERENCE, M-U

(V)MOVDQA (128-bit store-form version)

DEST[127:0] := SRC[127:0]

Intel C/C++ Compiler Intrinsic Equivalent

VMOVDQA32 __m512i _mm512_load_epi32( void * sa);

VMOVDQA32 __m512i _mm512_mask_load_epi32(__m512i s, __mmask16 k, void * sa);

VMOVDQA32 __m512i _mm512_maskz_load_epi32( __mmask16 k, void * sa);

VMOVDQA32 void _mm512_store_epi32(void * d, __m512i a);

VMOVDQA32 void _mm512_mask_store_epi32(void * d, __mmask16 k, __m512i a);

VMOVDQA32 __m256i _mm256_mask_load_epi32(__m256i s, __mmask8 k, void * sa);

VMOVDQA32 __m256i _mm256_maskz_load_epi32( __mmask8 k, void * sa);

VMOVDQA32 void _mm256_store_epi32(void * d, __m256i a);

VMOVDQA32 void _mm256_mask_store_epi32(void * d, __mmask8 k, __m256i a);

VMOVDQA32 __m128i _mm_mask_load_epi32(__m128i s, __mmask8 k, void * sa);

VMOVDQA32 __m128i _mm_maskz_load_epi32( __mmask8 k, void * sa);

VMOVDQA32 void _mm_store_epi32(void * d, __m128i a);

VMOVDQA32 void _mm_mask_store_epi32(void * d, __mmask8 k, __m128i a);

VMOVDQA64 __m512i _mm512_load_epi64( void * sa);

VMOVDQA64 __m512i _mm512_mask_load_epi64(__m512i s, __mmask8 k, void * sa);

VMOVDQA64 __m512i _mm512_maskz_load_epi64( __mmask8 k, void * sa);

VMOVDQA64 void _mm512_store_epi64(void * d, __m512i a);

VMOVDQA64 void _mm512_mask_store_epi64(void * d, __mmask8 k, __m512i a);

VMOVDQA64 __m256i _mm256_mask_load_epi64(__m256i s, __mmask8 k, void * sa);

VMOVDQA64 __m256i _mm256_maskz_load_epi64( __mmask8 k, void * sa);

VMOVDQA64 void _mm256_store_epi64(void * d, __m256i a);

VMOVDQA64 void _mm256_mask_store_epi64(void * d, __mmask8 k, __m256i a);

VMOVDQA64 __m128i _mm_mask_load_epi64(__m128i s, __mmask8 k, void * sa);

VMOVDQA64 __m128i _mm_maskz_load_epi64( __mmask8 k, void * sa);

VMOVDQA64 void _mm_store_epi64(void * d, __m128i a);

VMOVDQA64 void _mm_mask_store_epi64(void * d, __mmask8 k, __m128i a);

MOVDQA void __m256i _mm256_load_si256 (__m256i * p);

MOVDQA _mm256_store_si256(_m256i *p, __m256i a);

MOVDQA __m128i _mm_load_si128 (__m128i * p);

MOVDQA void _mm_store_si128(__m128i *p, __m128i a);

SIMD Floating-Point Exceptions

None

Other Exceptions

Non-EVEX-encoded instruction, see Exceptions Type1.SSE2 in Table 2-18, “Type 1 Class Exception Conditions”.

EVEX-encoded instruction, see Table 2-44, “Type E1 Class Exception Conditions”.

Additionally:

#UD

If EVEX.vvvv != 1111B or VEX.vvvv != 1111B.

MOVDQA,VMOVDQA32/64—Move Aligned Packed Integer Values

Vol. 2B

4-71

INSTRUCTION SET REFERENCE, M-U

MOVDQU,VMOVDQU8/16/32/64—Move Unaligned Packed Integer Values

Opcode/

Op/En

64/32

CPUID

Description

Instruction

bit Mode

Feature

Support

Flag

F3 0F 6F /r

V/V

SSE2

Move unaligned packed integer values from

MOVDQU xmm1, xmm2/m128

xmm2/m128 to xmm1.

F3 0F 7F /r

V/V

SSE2

Move unaligned packed integer values from

MOVDQU xmm2/m128, xmm1

xmm1 to xmm2/m128.

VEX.128.F3.0F.WIG 6F /r

V/V

AVX

Move unaligned packed integer values from

VMOVDQU xmm1, xmm2/m128

xmm2/m128 to xmm1.

VEX.128.F3.0F.WIG 7F /r

V/V

AVX

Move unaligned packed integer values from

VMOVDQU xmm2/m128, xmm1

xmm1 to xmm2/m128.

VEX.256.F3.0F.WIG 6F /r

V/V

AVX

Move unaligned packed integer values from

VMOVDQU ymm1, ymm2/m256

ymm2/m256 to ymm1.

VEX.256.F3.0F.WIG 7F /r

V/V

AVX

Move unaligned packed integer values from

VMOVDQU ymm2/m256, ymm1

ymm1 to ymm2/m256.

EVEX.128.F2.0F.W0 6F /r

V/V

AVX512VL

Move unaligned packed byte integer values

VMOVDQU8 xmm1 {k1}{z}, xmm2/m128

AVX512BW

from xmm2/m128 to xmm1 using writemask

k1.

EVEX.256.F2.0F.W0 6F /r

V/V

AVX512VL

Move unaligned packed byte integer values

VMOVDQU8 ymm1 {k1}{z}, ymm2/m256

AVX512BW

from ymm2/m256 to ymm1 using writemask

k1.

EVEX.512.F2.0F.W0 6F /r

V/V

AVX512BW

Move unaligned packed byte integer values

VMOVDQU8 zmm1 {k1}{z}, zmm2/m512

from zmm2/m512 to zmm1 using writemask

k1.

EVEX.128.F2.0F.W0 7F /r

V/V

AVX512VL

Move unaligned packed byte integer values

VMOVDQU8 xmm2/m128 {k1}{z}, xmm1

AVX512BW

from xmm1 to xmm2/m128 using writemask

k1.

EVEX.256.F2.0F.W0 7F /r

V/V

AVX512VL

Move unaligned packed byte integer values

VMOVDQU8 ymm2/m256 {k1}{z}, ymm1

AVX512BW

from ymm1 to ymm2/m256 using writemask

k1.

EVEX.512.F2.0F.W0 7F /r

V/V

AVX512BW

Move unaligned packed byte integer values

VMOVDQU8 zmm2/m512 {k1}{z}, zmm1

from zmm1 to zmm2/m512 using writemask

k1.

EVEX.128.F2.0F.W1 6F /r

V/V

AVX512VL

Move unaligned packed word integer values

VMOVDQU16 xmm1 {k1}{z}, xmm2/m128

AVX512BW

from xmm2/m128 to xmm1 using writemask

k1.

EVEX.256.F2.0F.W1 6F /r

V/V

AVX512VL

Move unaligned packed word integer values

VMOVDQU16 ymm1 {k1}{z}, ymm2/m256

AVX512BW

from ymm2/m256 to ymm1 using writemask

k1.

EVEX.512.F2.0F.W1 6F /r

V/V

AVX512BW

Move unaligned packed word integer values

VMOVDQU16 zmm1 {k1}{z}, zmm2/m512

from zmm2/m512 to zmm1 using writemask

k1.

EVEX.128.F2.0F.W1 7F /r

V/V

AVX512VL

Move unaligned packed word integer values

VMOVDQU16 xmm2/m128 {k1}{z}, xmm1

AVX512BW

from xmm1 to xmm2/m128 using writemask

k1.

EVEX.256.F2.0F.W1 7F /r

V/V

AVX512VL

Move unaligned packed word integer values

VMOVDQU16 ymm2/m256 {k1}{z}, ymm1

AVX512BW

from ymm1 to ymm2/m256 using writemask

k1.

EVEX.512.F2.0F.W1 7F /r

V/V

AVX512BW

Move unaligned packed word integer values

VMOVDQU16 zmm2/m512 {k1}{z}, zmm1

from zmm1 to zmm2/m512 using writemask

k1.

EVEX.128.F3.0F.W0 6F /r

V/V

AVX512VL

Move unaligned packed doubleword integer

VMOVDQU32 xmm1 {k1}{z},

AVX512F

values from xmm2/m128 to xmm1 using

xmm2/mm128

writemask k1.

4-72

Vol. 2B

MOVDQU,VMOVDQU8/16/32/64—Move Unaligned Packed Integer Values

INSTRUCTION SET REFERENCE, M-U

Opcode/

Op/En

64/32

CPUID

Description

Instruction

bit Mode

Feature

Support

Flag

EVEX.256.F3.0F.W0 6F /r

V/V

AVX512VL

Move unaligned packed doubleword integer

VMOVDQU32 ymm1 {k1}{z}, ymm2/m256

AVX512F

values from ymm2/m256 to ymm1 using

writemask k1.

EVEX.512.F3.0F.W0 6F /r

V/V

AVX512F

Move unaligned packed doubleword integer

VMOVDQU32 zmm1 {k1}{z}, zmm2/m512

values from zmm2/m512 to zmm1 using

writemask k1.

EVEX.128.F3.0F.W0 7F /r

V/V

AVX512VL

Move unaligned packed doubleword integer

VMOVDQU32 xmm2/m128 {k1}{z}, xmm1

AVX512F

values from xmm1 to xmm2/m128 using

writemask k1.

EVEX.256.F3.0F.W0 7F /r

V/V

AVX512VL

Move unaligned packed doubleword integer

VMOVDQU32 ymm2/m256 {k1}{z}, ymm1

AVX512F

values from ymm1 to ymm2/m256 using

writemask k1.

EVEX.512.F3.0F.W0 7F /r

V/V

AVX512F

Move unaligned packed doubleword integer

VMOVDQU32 zmm2/m512 {k1}{z}, zmm1

values from zmm1 to zmm2/m512 using

writemask k1.

EVEX.128.F3.0F.W1 6F /r

V/V

AVX512VL

Move unaligned packed quadword integer

VMOVDQU64 xmm1 {k1}{z}, xmm2/m128

AVX512F

values from xmm2/m128 to xmm1 using

writemask k1.

EVEX.256.F3.0F.W1 6F /r

V/V

AVX512VL

Move unaligned packed quadword integer

VMOVDQU64 ymm1 {k1}{z}, ymm2/m256

AVX512F

values from ymm2/m256 to ymm1 using

writemask k1.

EVEX.512.F3.0F.W1 6F /r

V/V

AVX512F

Move unaligned packed quadword integer

VMOVDQU64 zmm1 {k1}{z}, zmm2/m512

values from zmm2/m512 to zmm1 using

writemask k1.

EVEX.128.F3.0F.W1 7F /r

V/V

AVX512VL

Move unaligned packed quadword integer

VMOVDQU64 xmm2/m128 {k1}{z}, xmm1

AVX512F

values from xmm1 to xmm2/m128 using

writemask k1.

EVEX.256.F3.0F.W1 7F /r

V/V

AVX512VL

Move unaligned packed quadword integer

VMOVDQU64 ymm2/m256 {k1}{z}, ymm1

AVX512F

values from ymm1 to ymm2/m256 using

writemask k1.

EVEX.512.F3.0F.W1 7F /r

V/V

AVX512F

Move unaligned packed quadword integer

VMOVDQU64 zmm2/m512 {k1}{z}, zmm1

values from zmm1 to zmm2/m512 using

writemask k1.

Instruction Operand Encoding

Op/En

Tuple Type

Operand 1

Operand 2

Operand 3

Operand 4

N/A

ModRM:reg (w)

ModRM:r/m (r)

N/A

ModRM:r/m (w)

ModRM:reg (r)

N/A

Full Mem

ModRM:reg (w)

ModRM:r/m (r)

N/A

Full Mem

ModRM:r/m (w)

ModRM:reg (r)

N/A

Description

Note: VEX.vvvv and EVEX.vvvv are reserved and must be 1111b otherwise instructions will #UD.

EVEX encoded versions:

Moves 128, 256 or 512 bits of packed byte/word/doubleword/quadword integer values from the source operand

(the second operand) to the destination operand (first operand). This instruction can be used to load a vector

between two vector registers.

MOVDQU,VMOVDQU8/16/32/64—Move Unaligned Packed Integer Values

Vol. 2B

4-73

INSTRUCTION SET REFERENCE, M-U

The destination operand is updated at 8-bit (VMOVDQU8), 16-bit (VMOVDQU16), 32-bit (VMOVDQU32), or 64-bit

(VMOVDQU64) granularity according to the writemask.

VEX.256 encoded version:

Moves 256 bits of packed integer values from the source operand (second operand) to the destination operand

(first operand). This instruction can be used to load a YMM register from a 256-bit memory location, to store the

contents of a YMM register into a 256-bit memory location, or to move data between two YMM registers.

Bits (MAXVL-1:256) of the destination register are zeroed.

128-bit versions:

Moves 128 bits of packed integer values from the source operand (second operand) to the destination operand

(first operand). This instruction can be used to load an XMM register from a 128-bit memory location, to store the

contents of an XMM register into a 128-bit memory location, or to move data between two XMM registers.

128-bit Legacy SSE version: Bits (MAXVL-1:128) of the corresponding destination register remain unchanged.

When the source or destination operand is a memory operand, the operand may be unaligned to any alignment

without causing a general-protection exception (#GP) to be generated

VEX.128 encoded version: Bits (MAXVL-1:128) of the destination register are zeroed.

Operation

VMOVDQU8 (EVEX encoded versions, register-copy form)

(KL, VL) = (16, 128), (32, 256), (64, 512)

FOR j := 0 TO KL-1

i := j * 8

IF k1[j] OR *no writemask*

THEN DEST[i+7:i] := SRC[i+7:i]

ELSE

IF *merging-masking*

; merging-masking

THEN *DEST[i+7:i] remains unchanged*

ELSE DEST[i+7:i] := 0

; zeroing-masking

FI;

ENDFOR

DEST[MAXVL-1:VL] := 0

VMOVDQU8 (EVEX encoded versions, store-form)

(KL, VL) = (16, 128), (32, 256), (64, 512)

FOR j := 0 TO KL-1

i := j * 8

IF k1[j] OR *no writemask*

THEN DEST[i+7:i] :=

SRC[i+7:i]

ELSE *DEST[i+7:i] remains unchanged*

; merging-masking

FI;

ENDFOR;

4-74

Vol. 2B

MOVDQU,VMOVDQU8/16/32/64—Move Unaligned Packed Integer Values

INSTRUCTION SET REFERENCE, M-U

VMOVDQU8 (EVEX encoded versions, load-form)

(KL, VL) = (16, 128), (32, 256), (64, 512)

FOR j := 0 TO KL-1

i := j * 8

IF k1[j] OR *no writemask*

THEN DEST[i+7:i] := SRC[i+7:i]

ELSE

IF *merging-masking*

; merging-masking

THEN *DEST[i+7:i] remains unchanged*

ELSE DEST[i+7:i] := 0

; zeroing-masking

FI;

ENDFOR

DEST[MAXVL-1:VL] := 0

VMOVDQU16 (EVEX encoded versions, register-copy form)

(KL, VL) = (8, 128), (16, 256), (32, 512)

FOR j := 0 TO KL-1

i := j * 16

IF k1[j] OR *no writemask*

THEN DEST[i+15:i] := SRC[i+15:i]

ELSE

IF *merging-masking*

; merging-masking

THEN *DEST[i+15:i] remains unchanged*

ELSE DEST[i+15:i] := 0

; zeroing-masking

FI;

ENDFOR

DEST[MAXVL-1:VL] := 0

VMOVDQU16 (EVEX encoded versions, store-form)

(KL, VL) = (8, 128), (16, 256), (32, 512)

FOR j := 0 TO KL-1

i := j * 16

IF k1[j] OR *no writemask*

THEN DEST[i+15:i] :=

SRC[i+15:i]

ELSE *DEST[i+15:i] remains unchanged*

; merging-masking

FI;

ENDFOR;

MOVDQU,VMOVDQU8/16/32/64—Move Unaligned Packed Integer Values

Vol. 2B

4-75

INSTRUCTION SET REFERENCE, M-U

VMOVDQU16 (EVEX encoded versions, load-form)

(KL, VL) = (8, 128), (16, 256), (32, 512)

FOR j := 0 TO KL-1

i := j * 16

IF k1[j] OR *no writemask*

THEN DEST[i+15:i] := SRC[i+15:i]

ELSE

IF *merging-masking*

; merging-masking

THEN *DEST[i+15:i] remains unchanged*

ELSE DEST[i+15:i] := 0

; zeroing-masking

FI;

ENDFOR

DEST[MAXVL-1:VL] := 0

VMOVDQU32 (EVEX encoded versions, register-copy form)

(KL, VL) = (4, 128), (8, 256), (16, 512)

FOR j := 0 TO KL-1

i := j * 32

IF k1[j] OR *no writemask*

THEN DEST[i+31:i] := SRC[i+31:i]

ELSE

IF *merging-masking*

; merging-masking

THEN *DEST[i+31:i] remains unchanged*

ELSE DEST[i+31:i] := 0

; zeroing-masking

FI;

ENDFOR

DEST[MAXVL-1:VL] := 0

VMOVDQU32 (EVEX encoded versions, store-form)

(KL, VL) = (4, 128), (8, 256), (16, 512)

FOR j := 0 TO KL-1

i := j * 32

IF k1[j] OR *no writemask*

THEN DEST[i+31:i] :=

SRC[i+31:i]

ELSE *DEST[i+31:i] remains unchanged*

; merging-masking

FI;

ENDFOR;

4-76

Vol. 2B

MOVDQU,VMOVDQU8/16/32/64—Move Unaligned Packed Integer Values

INSTRUCTION SET REFERENCE, M-U

VMOVDQU32 (EVEX encoded versions, load-form)

(KL, VL) = (4, 128), (8, 256), (16, 512)

FOR j := 0 TO KL-1

i := j * 32

IF k1[j] OR *no writemask*

THEN DEST[i+31:i] := SRC[i+31:i]

ELSE

IF *merging-masking*

; merging-masking

THEN *DEST[i+31:i] remains unchanged*

ELSE DEST[i+31:i] := 0

; zeroing-masking

FI;

ENDFOR

DEST[MAXVL-1:VL] := 0

VMOVDQU64 (EVEX encoded versions, register-copy form)

(KL, VL) = (2, 128), (4, 256), (8, 512)

FOR j := 0 TO KL-1

i := j * 64

IF k1[j] OR *no writemask*

THEN DEST[i+63:i] := SRC[i+63:i]

ELSE

IF *merging-masking*

; merging-masking

THEN *DEST[i+63:i] remains unchanged*

ELSE DEST[i+63:i] := 0

; zeroing-masking

FI;

ENDFOR

DEST[MAXVL-1:VL] := 0

VMOVDQU64 (EVEX encoded versions, store-form)

(KL, VL) = (2, 128), (4, 256), (8, 512)

FOR j := 0 TO KL-1

i := j * 64

IF k1[j] OR *no writemask*

THEN DEST[i+63:i] := SRC[i+63:i]

ELSE *DEST[i+63:i] remains unchanged*

; merging-masking

FI;

ENDFOR;

MOVDQU,VMOVDQU8/16/32/64—Move Unaligned Packed Integer Values

Vol. 2B

4-77

INSTRUCTION SET REFERENCE, M-U

VMOVDQU64 (EVEX encoded versions, load-form)

(KL, VL) = (2, 128), (4, 256), (8, 512)

FOR j := 0 TO KL-1

i := j * 64

IF k1[j] OR *no writemask*

THEN DEST[i+63:i] := SRC[i+63:i]

ELSE

IF *merging-masking*

; merging-masking

THEN *DEST[i+63:i] remains unchanged*

ELSE DEST[i+63:i] := 0

; zeroing-masking

FI;

ENDFOR

DEST[MAXVL-1:VL] := 0

VMOVDQU (VEX.256 encoded version, load - and register copy)

DEST[255:0] := SRC[255:0]

DEST[MAXVL-1:256] := 0

VMOVDQU (VEX.256 encoded version, store-form)

DEST[255:0] := SRC[255:0]

VMOVDQU (VEX.128 encoded version)

DEST[127:0] := SRC[127:0]

DEST[MAXVL-1:128] := 0

VMOVDQU (128-bit load- and register-copy- form Legacy SSE version)

DEST[127:0] := SRC[127:0]

DEST[MAXVL-1:128] (Unmodified)

(V)MOVDQU (128-bit store-form version)

DEST[127:0] := SRC[127:0]

Intel C/C++ Compiler Intrinsic Equivalent

VMOVDQU16 __m512i _mm512_mask_loadu_epi16(__m512i s, __mmask32 k, void * sa);

VMOVDQU16 __m512i _mm512_maskz_loadu_epi16( __mmask32 k, void * sa);

VMOVDQU16 void _mm512_mask_storeu_epi16(void * d, __mmask32 k, __m512i a);

VMOVDQU16 __m256i _mm256_mask_loadu_epi16(__m256i s, __mmask16 k, void * sa);

VMOVDQU16 __m256i _mm256_maskz_loadu_epi16( __mmask16 k, void * sa);

VMOVDQU16 void _mm256_mask_storeu_epi16(void * d, __mmask16 k, __m256i a);

VMOVDQU16 __m128i _mm_mask_loadu_epi16(__m128i s, __mmask8 k, void * sa);

VMOVDQU16 __m128i _mm_maskz_loadu_epi16( __mmask8 k, void * sa);

VMOVDQU16 void _mm_mask_storeu_epi16(void * d, __mmask8 k, __m128i a);

VMOVDQU32 __m512i _mm512_loadu_epi32( void * sa);

VMOVDQU32 __m512i _mm512_mask_loadu_epi32(__m512i s, __mmask16 k, void * sa);

VMOVDQU32 __m512i _mm512_maskz_loadu_epi32( __mmask16 k, void * sa);

VMOVDQU32 void _mm512_storeu_epi32(void * d, __m512i a);

VMOVDQU32 void _mm512_mask_storeu_epi32(void * d, __mmask16 k, __m512i a);

VMOVDQU32 __m256i _mm256_mask_loadu_epi32(__m256i s, __mmask8 k, void * sa);

VMOVDQU32 __m256i _mm256_maskz_loadu_epi32( __mmask8 k, void * sa);

VMOVDQU32 void _mm256_storeu_epi32(void * d, __m256i a);

VMOVDQU32 void _mm256_mask_storeu_epi32(void * d, __mmask8 k, __m256i a);

VMOVDQU32 __m128i _mm_mask_loadu_epi32(__m128i s, __mmask8 k, void * sa);

VMOVDQU32 __m128i _mm_maskz_loadu_epi32( __mmask8 k, void * sa);

4-78

Vol. 2B

MOVDQU,VMOVDQU8/16/32/64—Move Unaligned Packed Integer Values

INSTRUCTION SET REFERENCE, M-U

VMOVDQU32 void _mm_storeu_epi32(void * d, __m128i a);

VMOVDQU32 void _mm_mask_storeu_epi32(void * d, __mmask8 k, __m128i a);

VMOVDQU64 __m512i _mm512_loadu_epi64( void * sa);

VMOVDQU64 __m512i _mm512_mask_loadu_epi64(__m512i s, __mmask8 k, void * sa);

VMOVDQU64 __m512i _mm512_maskz_loadu_epi64( __mmask8 k, void * sa);

VMOVDQU64 void _mm512_storeu_epi64(void * d, __m512i a);

VMOVDQU64 void _mm512_mask_storeu_epi64(void * d, __mmask8 k, __m512i a);

VMOVDQU64 __m256i _mm256_mask_loadu_epi64(__m256i s, __mmask8 k, void * sa);

VMOVDQU64 __m256i _mm256_maskz_loadu_epi64( __mmask8 k, void * sa);

VMOVDQU64 void _mm256_storeu_epi64(void * d, __m256i a);

VMOVDQU64 void _mm256_mask_storeu_epi64(void * d, __mmask8 k, __m256i a);

VMOVDQU64 __m128i _mm_mask_loadu_epi64(__m128i s, __mmask8 k, void * sa);

VMOVDQU64 __m128i _mm_maskz_loadu_epi64( __mmask8 k, void * sa);

VMOVDQU64 void _mm_storeu_epi64(void * d, __m128i a);

VMOVDQU64 void _mm_mask_storeu_epi64(void * d, __mmask8 k, __m128i a);

VMOVDQU8 __m512i _mm512_mask_loadu_epi8(__m512i s, __mmask64 k, void * sa);

VMOVDQU8 __m512i _mm512_maskz_loadu_epi8( __mmask64 k, void * sa);

VMOVDQU8 void _mm512_mask_storeu_epi8(void * d, __mmask64 k, __m512i a);

VMOVDQU8 __m256i _mm256_mask_loadu_epi8(__m256i s, __mmask32 k, void * sa);

VMOVDQU8 __m256i _mm256_maskz_loadu_epi8( __mmask32 k, void * sa);

VMOVDQU8 void _mm256_mask_storeu_epi8(void * d, __mmask32 k, __m256i a);

VMOVDQU8 __m128i _mm_mask_loadu_epi8(__m128i s, __mmask16 k, void * sa);

VMOVDQU8 __m128i _mm_maskz_loadu_epi8( __mmask16 k, void * sa);

VMOVDQU8 void _mm_mask_storeu_epi8(void * d, __mmask16 k, __m128i a);

MOVDQU __m256i _mm256_loadu_si256 (__m256i * p);

MOVDQU _mm256_storeu_si256(_m256i *p, __m256i a);

MOVDQU __m128i _mm_loadu_si128 (__m128i * p);

MOVDQU _mm_storeu_si128(__m128i *p, __m128i a);

SIMD Floating-Point Exceptions

None

Other Exceptions

Non-EVEX-encoded instruction, see Table 2-21, “Type 4 Class Exception Conditions”.

EVEX-encoded instruction, see Exceptions Type E4.nb in Table 2-49, “Type E4 Class Exception Conditions”.

Additionally:

#UD

If EVEX.vvvv != 1111B or VEX.vvvv != 1111B.

MOVDQU,VMOVDQU8/16/32/64—Move Unaligned Packed Integer Values

Vol. 2B

4-79

INSTRUCTION SET REFERENCE, M-U

MOVDQ2Q—Move Quadword from XMM to MMX Technology Register

Opcode

Instruction

Op/

64-Bit

Compat/

Description

Mode

Leg Mode

F2 0F D6 /r

MOVDQ2Q mm, xmm

Valid

Move low quadword from xmm to mmx

Instruction Operand Encoding

Op/En

Operand 1

Operand 2

Operand 3

Operand 4

ModRM:reg (w)

ModRM:r/m (r)

N/A

Description

Moves the low quadword from the source operand (second operand) to the destination operand (first operand). The

source operand is an XMM register and the destination operand is an MMX technology register.

This instruction causes a transition from x87 FPU to MMX technology operation (that is, the x87 FPU top-of-stack

pointer is set to 0 and the x87 FPU tag word is set to all 0s [valid]). If this instruction is executed while an x87 FPU

floating-point exception is pending, the exception is handled before the MOVDQ2Q instruction is executed.

In 64-bit mode, use of the REX.R prefix permits this instruction to access additional registers (XMM8-XMM15).

Operation

DEST := SRC[63:0];

Intel C/C++ Compiler Intrinsic Equivalent

MOVDQ2Q:

__m64 _mm_movepi64_pi64 ( __m128i a)

SIMD Floating-Point Exceptions

None.

Protected Mode Exceptions

#NM

If CR0.TS[bit 3] = 1.

#UD

If CR0.EM[bit 2] = 1.

If CR4.OSFXSR[bit 9] = 0.

If CPUID.01H:EDX.SSE2[bit 26] = 0.

If the LOCK prefix is used.

#MF

If there is a pending x87 FPU exception.

Real-Address Mode Exceptions

Same exceptions as in protected mode.

Virtual-8086 Mode Exceptions

Same exceptions as in protected mode.

Compatibility Mode Exceptions

Same exceptions as in protected mode.

64-Bit Mode Exceptions

Same exceptions as in protected mode.

4-80

Vol. 2B

MOVDQ2Q—Move Quadword from XMM to MMX Technology Register

INSTRUCTION SET REFERENCE, M-U

MOVHLPS—Move Packed Single Precision Floating-Point Values High to Low

Opcode/

Op /

64/32

CPUID

Description

Instruction

bit Mode

Feature

Support

Flag

NP 0F 12 /r

V/V

SSE

Move two packed single precision floating-point values

MOVHLPS xmm1, xmm2

from high quadword of xmm2 to low quadword of xmm1.

VEX.128.0F.WIG 12 /r

RVM

V/V

AVX

Merge two packed single precision floating-point values

VMOVHLPS xmm1, xmm2, xmm3

from high quadword of xmm3 and low quadword of xmm2.

EVEX.128.0F.W0 12 /r

RVM

V/V

AVX512F

Merge two packed single precision floating-point values

VMOVHLPS xmm1, xmm2, xmm3

from high quadword of xmm3 and low quadword of xmm2.

Instruction Operand Encoding¹

Op/En

Operand 1

Operand 2

Operand 3

Operand 4

ModRM:reg (w)

ModRM:r/m (r)

N/A

VEX.vvvv (r) /

RVM

ModRM:reg (w)

ModRM:r/m (r)

N/A

EVEX.vvvv (r)

Description

This instruction cannot be used for memory to register moves.

128-bit two-argument form:

Moves two packed single precision floating-point values from the high quadword of the second XMM argument

(second operand) to the low quadword of the first XMM register (first argument). The quadword at bits 127:64 of

the destination operand is left unchanged. Bits (MAXVL-1:128) of the corresponding destination register remain

unchanged.

128-bit and EVEX three-argument form:

Moves two packed single precision floating-point values from the high quadword of the third XMM argument (third

operand) to the low quadword of the destination (first operand). Copies the high quadword from the second XMM

argument (second operand) to the high quadword of the destination (first operand). Bits (MAXVL-1:128) of the

corresponding destination register are zeroed.

If VMOVHLPS is encoded with VEX.L or EVEX.L’L= 1, an attempt to execute the instruction encoded with VEX.L or

EVEX.L’L= 1 will cause an #UD exception.

Operation

MOVHLPS (128-bit two-argument form)

DEST[63:0] := SRC[127:64]

DEST[MAXVL-1:64] (Unmodified)

VMOVHLPS (128-bit three-argument form - VEX & EVEX)

DEST[63:0] := SRC2[127:64]

DEST[127:64] := SRC1[127:64]

DEST[MAXVL-1:128] := 0

Intel C/C++ Compiler Intrinsic Equivalent

MOVHLPS __m128 _mm_movehl_ps(__m128 a, __m128 b)

SIMD Floating-Point Exceptions

None

1. ModRM.MOD = 011B required.

MOVHLPS—Move Packed Single Precision Floating-Point Values High to Low

Vol. 2B

4-81

INSTRUCTION SET REFERENCE, M-U

MOVHPD—Move High Packed Double Precision Floating-Point Value

Opcode/

Op / En

64/32

CPUID

Description

Instruction

bit Mode

Feature

Support

Flag

66 0F 16 /r

V/V

SSE2

Move double precision floating-point value from m64

MOVHPD xmm1, m64

to high quadword of xmm1.

VEX.128.66.0F.WIG 16 /r

V/V

AVX

Merge double precision floating-point value from m64

VMOVHPD xmm2, xmm1, m64

and the low quadword of xmm1.

EVEX.128.66.0F.W1 16 /r

V/V

AVX512F

Merge double precision floating-point value from m64

VMOVHPD xmm2, xmm1, m64

and the low quadword of xmm1.

66 0F 17 /r

V/V

SSE2

Move double precision floating-point value from high

MOVHPD m64, xmm1

quadword of xmm1 to m64.

VEX.128.66.0F.WIG 17 /r

V/V

AVX

Move double precision floating-point value from high

VMOVHPD m64, xmm1

quadword of xmm1 to m64.

EVEX.128.66.0F.W1 17 /r

V/V

AVX512F

Move double precision floating-point value from high

VMOVHPD m64, xmm1

quadword of xmm1 to m64.

Instruction Operand Encoding

Op/En

Tuple Type

Operand 1

Operand 2

Operand 3

Operand 4

N/A

ModRM:reg (r, w)

ModRM:r/m (r)

N/A

ModRM:reg (w)

VEX.vvvv (r)

ModRM:r/m (r)

N/A

ModRM:r/m (w)

ModRM:reg (r)

N/A

Tuple1 Scalar

ModRM:reg (w)

EVEX.vvvv (r)

ModRM:r/m (r)

N/A

Tuple1 Scalar

ModRM:r/m (w)

ModRM:reg (r)

N/A

Description

This instruction cannot be used for register to register or memory to memory moves.

128-bit Legacy SSE load:

Moves a double precision floating-point value from the source 64-bit memory operand and stores it in the high 64-

bits of the destination XMM register. The lower 64bits of the XMM register are preserved. Bits (MAXVL-1:128) of the

corresponding destination register are preserved.

VEX.128 & EVEX encoded load:

Loads a double precision floating-point value from the source 64-bit memory operand (the third operand) and

stores it in the upper 64-bits of the destination XMM register (first operand). The low 64-bits from the first source

operand (second operand) are copied to the low 64-bits of the destination. Bits (MAXVL-1:128) of the corre-

sponding destination register are zeroed.

128-bit store:

Stores a double precision floating-point value from the high 64-bits of the XMM register source (second operand)

to the 64-bit memory location (first operand).

Note: VMOVHPD (store) (VEX.128.66.0F 17 /r) is legal and has the same behavior as the existing 66 0F 17 store.

For VMOVHPD (store) VEX.vvvv and EVEX.vvvv are reserved and must be 1111b otherwise instruction will #UD.

If VMOVHPD is encoded with VEX.L or EVEX.L’L= 1, an attempt to execute the instruction encoded with VEX.L or

EVEX.L’L= 1 will cause an #UD exception.

MOVHPD—Move High Packed Double Precision Floating-Point Value

Vol. 2B

4-83

INSTRUCTION SET REFERENCE, M-U

Operation

MOVHPD (128-bit Legacy SSE load)

DEST[63:0] (Unmodified)

DEST[127:64] := SRC[63:0]

DEST[MAXVL-1:128] (Unmodified)

VMOVHPD (VEX.128 & EVEX encoded load)

DEST[63:0] := SRC1[63:0]

DEST[127:64] := SRC2[63:0]

DEST[MAXVL-1:128] := 0

VMOVHPD (store)

DEST[63:0] := SRC[127:64]

Intel C/C++ Compiler Intrinsic Equivalent

MOVHPD __m128d _mm_loadh_pd ( __m128d a, double *p)

MOVHPD void _mm_storeh_pd (double *p, __m128d a)

SIMD Floating-Point Exceptions

None

Other Exceptions

Non-EVEX-encoded instruction, see Table 2-22, “Type 5 Class Exception Conditions”; additionally:

#UD

If VEX.L = 1.

EVEX-encoded instruction, see Table 2-57, “Type E9NF Class Exception Conditions”.

4-84

Vol. 2B

MOVHPD—Move High Packed Double Precision Floating-Point Value

INSTRUCTION SET REFERENCE, M-U

MOVHPS—Move High Packed Single Precision Floating-Point Values

Opcode/

Op / En

64/32

CPUID

Description

Instruction

bit Mode

Feature

Support

Flag

NP 0F 16 /r

V/V

SSE

Move two packed single precision floating-point values

MOVHPS xmm1, m64

from m64 to high quadword of xmm1.

VEX.128.0F.WIG 16 /r

V/V

AVX

Merge two packed single precision floating-point values

VMOVHPS xmm2, xmm1, m64

from m64 and the low quadword of xmm1.

EVEX.128.0F.W0 16 /r

V/V

AVX512F

Merge two packed single precision floating-point values

VMOVHPS xmm2, xmm1, m64

from m64 and the low quadword of xmm1.

NP 0F 17 /r

V/V

SSE

Move two packed single precision floating-point values

MOVHPS m64, xmm1

from high quadword of xmm1 to m64.

VEX.128.0F.WIG 17 /r

V/V

AVX

Move two packed single precision floating-point values

VMOVHPS m64, xmm1

from high quadword of xmm1 to m64.

EVEX.128.0F.W0 17 /r

V/V

AVX512F

Move two packed single precision floating-point values

VMOVHPS m64, xmm1

from high quadword of xmm1 to m64.

Instruction Operand Encoding

Op/En

Tuple Type

Operand 1

Operand 2

Operand 3

Operand 4

N/A

ModRM:reg (r, w)

ModRM:r/m (r)

N/A

ModRM:reg (w)

VEX.vvvv (r)

ModRM:r/m (r)

N/A

ModRM:r/m (w)

ModRM:reg (r)

N/A

Tuple2

ModRM:reg (w)

EVEX.vvvv (r)

ModRM:r/m (r)

N/A

Tuple2

ModRM:r/m (w)

ModRM:reg (r)

N/A

Description

This instruction cannot be used for register to register or memory to memory moves.

128-bit Legacy SSE load:

Moves two packed single precision floating-point values from the source 64-bit memory operand and stores them

in the high 64-bits of the destination XMM register. The lower 64bits of the XMM register are preserved. Bits

(MAXVL-1:128) of the corresponding destination register are preserved.

VEX.128 & EVEX encoded load:

Loads two single precision floating-point values from the source 64-bit memory operand (the third operand) and

stores it in the upper 64-bits of the destination XMM register (first operand). The low 64-bits from the first source

operand (the second operand) are copied to the lower 64-bits of the destination. Bits (MAXVL-1:128) of the corre-

sponding destination register are zeroed.

128-bit store:

Stores two packed single precision floating-point values from the high 64-bits of the XMM register source (second

operand) to the 64-bit memory location (first operand).

Note: VMOVHPS (store) (VEX.128.0F 17 /r) is legal and has the same behavior as the existing 0F 17 store. For

VMOVHPS (store) VEX.vvvv and EVEX.vvvv are reserved and must be 1111b otherwise instruction will #UD.

If VMOVHPS is encoded with VEX.L or EVEX.L’L= 1, an attempt to execute the instruction encoded with VEX.L or

EVEX.L’L= 1 will cause an #UD exception.

MOVHPS—Move High Packed Single Precision Floating-Point Values

Vol. 2B

4-85

INSTRUCTION SET REFERENCE, M-U

Operation

MOVHPS (128-bit Legacy SSE load)

DEST[63:0] (Unmodified)

DEST[127:64] := SRC[63:0]

DEST[MAXVL-1:128] (Unmodified)

VMOVHPS (VEX.128 and EVEX encoded load)

DEST[63:0] := SRC1[63:0]

DEST[127:64] := SRC2[63:0]

DEST[MAXVL-1:128] := 0

VMOVHPS (store)

DEST[63:0] := SRC[127:64]

Intel C/C++ Compiler Intrinsic Equivalent

MOVHPS __m128 _mm_loadh_pi ( __m128 a, __m64 *p)

MOVHPS void _mm_storeh_pi (__m64 *p, __m128 a)

SIMD Floating-Point Exceptions

None

Other Exceptions

Non-EVEX-encoded instruction, see Table 2-22, “Type 5 Class Exception Conditions”; additionally:

#UD

If VEX.L = 1.

EVEX-encoded instruction, see Table 2-57, “Type E9NF Class Exception Conditions”.

4-86

Vol. 2B

MOVHPS—Move High Packed Single Precision Floating-Point Values

INSTRUCTION SET REFERENCE, M-U

MOVLHPS—Move Packed Single Precision Floating-Point Values Low to High

Opcode/

Op /

64/32

CPUID

Description

Instruction

bit Mode

Feature

Support

Flag

NP 0F 16 /r

V/V

SSE

Move two packed single precision floating-point values from

MOVLHPS xmm1, xmm2

low quadword of xmm2 to high quadword of xmm1.

VEX.128.0F.WIG 16 /r

RVM

V/V

AVX

Merge two packed single precision floating-point values

VMOVLHPS xmm1, xmm2, xmm3

from low quadword of xmm3 and low quadword of xmm2.

EVEX.128.0F.W0 16 /r

RVM

V/V

AVX512F

Merge two packed single precision floating-point values

VMOVLHPS xmm1, xmm2, xmm3

from low quadword of xmm3 and low quadword of xmm2.

Instruction Operand Encoding¹

Op/En

Operand 1

Operand 2

Operand 3

Operand 4

ModRM:reg (w)

ModRM:r/m (r)

N/A

VEX.vvvv (r) /

RVM

ModRM:reg (w)

ModRM:r/m (r)

N/A

EVEX.vvvv (r)

Description

This instruction cannot be used for memory to register moves.

128-bit two-argument form:

Moves two packed single precision floating-point values from the low quadword of the second XMM argument

(second operand) to the high quadword of the first XMM register (first argument). The low quadword of the desti-

nation operand is left unchanged. Bits (MAXVL-1:128) of the corresponding destination register are unmodified.

128-bit three-argument forms:

Moves two packed single precision floating-point values from the low quadword of the third XMM argument (third

operand) to the high quadword of the destination (first operand). Copies the low quadword from the second XMM

argument (second operand) to the low quadword of the destination (first operand). Bits (MAXVL-1:128) of the

corresponding destination register are zeroed.

If VMOVLHPS is encoded with VEX.L or EVEX.L’L= 1, an attempt to execute the instruction encoded with VEX.L or

EVEX.L’L= 1 will cause an #UD exception.

Operation

MOVLHPS (128-bit two-argument form)

DEST[63:0] (Unmodified)

DEST[127:64] := SRC[63:0]

DEST[MAXVL-1:128] (Unmodified)

VMOVLHPS (128-bit three-argument form - VEX & EVEX)

DEST[63:0] := SRC1[63:0]

DEST[127:64] := SRC2[63:0]

DEST[MAXVL-1:128] := 0

Intel C/C++ Compiler Intrinsic Equivalent

MOVLHPS __m128 _mm_movelh_ps(__m128 a, __m128 b)

SIMD Floating-Point Exceptions

None

1. ModRM.MOD = 011B required

MOVLHPS—Move Packed Single Precision Floating-Point Values Low to High

Vol. 2B

4-87

INSTRUCTION SET REFERENCE, M-U

MOVLPD—Move Low Packed Double Precision Floating-Point Value

Opcode/

Op / En

64/32

CPUID

Description

Instruction

bit Mode

Feature

Support

Flag

66 0F 12 /r

V/V

SSE2

Move double precision floating-point value from m64 to

MOVLPD xmm1, m64

low quadword of xmm1.

VEX.128.66.0F.WIG 12 /r

V/V

AVX

Merge double precision floating-point value from m64

VMOVLPD xmm2, xmm1, m64

and the high quadword of xmm1.

EVEX.128.66.0F.W1 12 /r

V/V

AVX512F

Merge double precision floating-point value from m64

VMOVLPD xmm2, xmm1, m64

and the high quadword of xmm1.

66 0F 13/r

V/V

SSE2

Move double precision floating-point value from low

MOVLPD m64, xmm1

quadword of xmm1 to m64.

VEX.128.66.0F.WIG 13/r

V/V

AVX

Move double precision floating-point value from low

VMOVLPD m64, xmm1

quadword of xmm1 to m64.

EVEX.128.66.0F.W1 13/r

V/V

AVX512F

Move double precision floating-point value from low

VMOVLPD m64, xmm1

quadword of xmm1 to m64.

Instruction Operand Encoding

Op/En

Tuple Type

Operand 1

Operand 2

Operand 3

Operand 4

N/A

ModRM:reg (r, w)

ModRM:r/m (r)

N/A

ModRM:r/m (r)

VEX.vvvv (r)

ModRM:r/m (r)

N/A

ModRM:r/m (w)

ModRM:reg (r)

N/A

Tuple1 Scalar

ModRM:reg (w)

EVEX.vvvv (r)

ModRM:r/m (r)

N/A

Tuple1 Scalar

ModRM:r/m (w)

ModRM:reg (r)

N/A

Description

This instruction cannot be used for register to register or memory to memory moves.

128-bit Legacy SSE load:

Moves a double precision floating-point value from the source 64-bit memory operand and stores it in the low 64-

bits of the destination XMM register. The upper 64bits of the XMM register are preserved. Bits (MAXVL-1:128) of the

corresponding destination register are preserved.

VEX.128 & EVEX encoded load:

Loads a double precision floating-point value from the source 64-bit memory operand (third operand), merges it

with the upper 64-bits of the first source XMM register (second operand), and stores it in the low 128-bits of the

destination XMM register (first operand). Bits (MAXVL-1:128) of the corresponding destination register are zeroed.

128-bit store:

Stores a double precision floating-point value from the low 64-bits of the XMM register source (second operand) to

the 64-bit memory location (first operand).

Note: VMOVLPD (store) (VEX.128.66.0F 13 /r) is legal and has the same behavior as the existing 66 0F 13 store.

For VMOVLPD (store) VEX.vvvv and EVEX.vvvv are reserved and must be 1111b otherwise instruction will #UD.

If VMOVLPD is encoded with VEX.L or EVEX.L’L= 1, an attempt to execute the instruction encoded with VEX.L or

EVEX.L’L= 1 will cause an #UD exception.

Operation

MOVLPD (128-bit Legacy SSE load)

DEST[63:0] := SRC[63:0]

DEST[MAXVL-1:64] (Unmodified)

MOVLPD—Move Low Packed Double Precision Floating-Point Value

Vol. 2B

4-89

INSTRUCTION SET REFERENCE, M-U

MOVLPS—Move Low Packed Single Precision Floating-Point Values

Opcode/

Op / En

64/32

CPUID

Description

Instruction

bit Mode

Feature

Support

Flag

NP 0F 12 /r

V/V

SSE

Move two packed single precision floating-point values

MOVLPS xmm1, m64

from m64 to low quadword of xmm1.

VEX.128.0F.WIG 12 /r

V/V

AVX

Merge two packed single precision floating-point values

VMOVLPS xmm2, xmm1, m64

from m64 and the high quadword of xmm1.

EVEX.128.0F.W0 12 /r

V/V

AVX512F

Merge two packed single precision floating-point values

VMOVLPS xmm2, xmm1, m64

from m64 and the high quadword of xmm1.

0F 13/r

V/V

SSE

Move two packed single precision floating-point values

MOVLPS m64, xmm1

from low quadword of xmm1 to m64.

VEX.128.0F.WIG 13/r

V/V

AVX

Move two packed single precision floating-point values

VMOVLPS m64, xmm1

from low quadword of xmm1 to m64.

EVEX.128.0F.W0 13/r

V/V

AVX512F

Move two packed single precision floating-point values

VMOVLPS m64, xmm1

from low quadword of xmm1 to m64.

Instruction Operand Encoding

Op/En

Tuple Type

Operand 1

Operand 2

Operand 3

Operand 4

N/A

ModRM:reg (r, w)

ModRM:r/m (r)

N/A

ModRM:reg (w)

VEX.vvvv (r)

ModRM:r/m (r)

N/A

ModRM:r/m (w)

ModRM:reg (r)

N/A

Tuple2

ModRM:reg (w)

EVEX.vvvv (r)

ModRM:r/m (r)

N/A

Tuple2

ModRM:r/m (w)

ModRM:reg (r)

N/A

Description

This instruction cannot be used for register to register or memory to memory moves.

128-bit Legacy SSE load:

Moves two packed single precision floating-point values from the source 64-bit memory operand and stores them

in the low 64-bits of the destination XMM register. The upper 64bits of the XMM register are preserved. Bits

(MAXVL-1:128) of the corresponding destination register are preserved.

VEX.128 & EVEX encoded load:

Loads two packed single precision floating-point values from the source 64-bit memory operand (the third

operand), merges them with the upper 64-bits of the first source operand (the second operand), and stores them

in the low 128-bits of the destination register (the first operand). Bits (MAXVL-1:128) of the corresponding desti-

nation register are zeroed.

128-bit store:

Loads two packed single precision floating-point values from the low 64-bits of the XMM register source (second

operand) to the 64-bit memory location (first operand).

Note: VMOVLPS (store) (VEX.128.0F 13 /r) is legal and has the same behavior as the existing 0F 13 store. For

VMOVLPS (store) VEX.vvvv and EVEX.vvvv are reserved and must be 1111b otherwise instruction will #UD.

If VMOVLPS is encoded with VEX.L or EVEX.L’L= 1, an attempt to execute the instruction encoded with VEX.L or

EVEX.L’L= 1 will cause an #UD exception.

MOVLPS—Move Low Packed Single Precision Floating-Point Values

Vol. 2B

4-91

INSTRUCTION SET REFERENCE, M-U

MOVMSKPD—Extract Packed Double Precision Floating-Point Sign Mask

Opcode/

Op/

64/32-bit

CPUID

Description

Instruction

Mode

Feature

Flag

66 0F 50 /r

V/V

SSE2

Extract 2-bit sign mask from xmm and store in reg. The

upper bits of r32 or r64 are filled with zeros.

MOVMSKPD reg, xmm

VEX.128.66.0F.WIG 50 /r

V/V

AVX

Extract 2-bit sign mask from xmm2 and store in reg.

The upper bits of r32 or r64 are zeroed.

VMOVMSKPD reg, xmm2

VEX.256.66.0F.WIG 50 /r

V/V

AVX

Extract 4-bit sign mask from ymm2 and store in reg.

The upper bits of r32 or r64 are zeroed.

VMOVMSKPD reg, ymm2

Instruction Operand Encoding

Op/En

Operand 1

Operand 2

Operand 3

Operand 4

ModRM:reg (w)

ModRM:r/m (r)

N/A

Description

Extracts the sign bits from the packed double precision floating-point values in the source operand (second

operand), formats them into a 2-bit mask, and stores the mask in the destination operand (first operand). The

source operand is an XMM register, and the destination operand is a general-purpose register. The mask is stored

in the 2 low-order bits of the destination operand. Zero-extend the upper bits of the destination.

In 64-bit mode, the instruction can access additional registers (XMM8-XMM15, R8-R15) when used with a REX.R

prefix. The default operand size is 64-bit in 64-bit mode.

128-bit versions: The source operand is a YMM register. The destination operand is a general purpose register.

VEX.256 encoded version: The source operand is a YMM register. The destination operand is a general purpose

Note: In VEX-encoded versions, VEX.vvvv is reserved and must be 1111b, otherwise instructions will #UD.

Operation

(V)MOVMSKPD (128-bit versions)

DEST[0] := SRC[63]

DEST[1] := SRC[127]

IF DEST = r32

THEN DEST[31:2] := 0;

ELSE DEST[63:2] := 0;

VMOVMSKPD (VEX.256 encoded version)

DEST[0] := SRC[63]

DEST[1] := SRC[127]

DEST[2] := SRC[191]

DEST[3] := SRC[255]

IF DEST = r32

THEN DEST[31:4] := 0;

ELSE DEST[63:4] := 0;

MOVMSKPD—Extract Packed Double Precision Floating-Point Sign Mask

Vol. 2B

4-93

INSTRUCTION SET REFERENCE, M-U

MOVMSKPS—Extract Packed Single Precision Floating-Point Sign Mask

Opcode/

Op/

64/32-bit

CPUID

Description

Instruction

Mode

Feature

Flag

NP 0F 50 /r

V/V

SSE

Extract 4-bit sign mask from xmm and store in reg.

The upper bits of r32 or r64 are filled with zeros.

MOVMSKPS reg, xmm

VEX.128.0F.WIG 50 /r

V/V

AVX

Extract 4-bit sign mask from xmm2 and store in reg.

The upper bits of r32 or r64 are zeroed.

VMOVMSKPS reg, xmm2

VEX.256.0F.WIG 50 /r

V/V

AVX

Extract 8-bit sign mask from ymm2 and store in reg.

The upper bits of r32 or r64 are zeroed.

VMOVMSKPS reg, ymm2

Instruction Operand Encoding¹

Op/En

Operand 1

Operand 2

Operand 3

Operand 4

ModRM:reg (w)

ModRM:r/m (r)

N/A

Description

Extracts the sign bits from the packed single precision floating-point values in the source operand (second

operand), formats them into a 4- or 8-bit mask, and stores the mask in the destination operand (first operand).

The source operand is an XMM or YMM register, and the destination operand is a general-purpose register. The

mask is stored in the 4 or 8 low-order bits of the destination operand. The upper bits of the destination operand

beyond the mask are filled with zeros.

In 64-bit mode, the instruction can access additional registers (XMM8-XMM15, R8-R15) when used with a REX.R

prefix. The default operand size is 64-bit in 64-bit mode.

128-bit versions: The source operand is a YMM register. The destination operand is a general purpose register.

VEX.256 encoded version: The source operand is a YMM register. The destination operand is a general purpose

Note: In VEX-encoded versions, VEX.vvvv is reserved and must be 1111b, otherwise instructions will #UD.

Operation

DEST[0] := SRC[31];

DEST[1] := SRC[63];

DEST[2] := SRC[95];

DEST[3] := SRC[127];

IF DEST = r32

THEN DEST[31:4] := ZeroExtend;

ELSE DEST[63:4] := ZeroExtend;

FI;

1. ModRM.MOD = 011B required

MOVMSKPS—Extract Packed Single Precision Floating-Point Sign Mask

Vol. 2B

4-95

INSTRUCTION SET REFERENCE, M-U

(V)MOVMSKPS (128-bit version)

DEST[0] := SRC[31]

DEST[1] := SRC[63]

DEST[2] := SRC[95]

DEST[3] := SRC[127]

IF DEST = r32

THEN DEST[31:4] := 0;

ELSE DEST[63:4] := 0;

VMOVMSKPS (VEX.256 encoded version)

DEST[0] := SRC[31]

DEST[1] := SRC[63]

DEST[2] := SRC[95]

DEST[3] := SRC[127]

DEST[4] := SRC[159]

DEST[5] := SRC[191]

DEST[6] := SRC[223]

DEST[7] := SRC[255]

IF DEST = r32

THEN DEST[31:8] := 0;

ELSE DEST[63:8] := 0;

Intel C/C++ Compiler Intrinsic Equivalent

int _mm_movemask_ps(__m128 a)

int _mm256_movemask_ps(__m256 a)

SIMD Floating-Point Exceptions

None.

Other Exceptions

See Table 2-24, “Type 7 Class Exception Conditions”; additionally:

#UD

If VEX.vvvv ≠ 1111B.

4-96

Vol. 2B

MOVMSKPS—Extract Packed Single Precision Floating-Point Sign Mask

INSTRUCTION SET REFERENCE, M-U

MOVNTDQA—Load Double Quadword Non-Temporal Aligned Hint

Opcode/

Op /

64/32

CPUID

Description

Instruction

bit Mode

Feature Flag

Support

66 0F 38 2A /r

V/V

SSE4_1

Move double quadword from m128 to xmm1 using non-

MOVNTDQA xmm1, m128

temporal hint if WC memory type.

VEX.128.66.0F38.WIG 2A /r

V/V

AVX

Move double quadword from m128 to xmm using non-

VMOVNTDQA xmm1, m128

temporal hint if WC memory type.

VEX.256.66.0F38.WIG 2A /r

V/V

AVX2

Move 256-bit data from m256 to ymm using non-temporal

VMOVNTDQA ymm1, m256

hint if WC memory type.

EVEX.128.66.0F38.W0 2A /r

V/V

AVX512VL

Move 128-bit data from m128 to xmm using non-temporal

VMOVNTDQA xmm1, m128

AVX512F

hint if WC memory type.

EVEX.256.66.0F38.W0 2A /r

V/V

AVX512VL

Move 256-bit data from m256 to ymm using non-temporal

VMOVNTDQA ymm1, m256

AVX512F

hint if WC memory type.

EVEX.512.66.0F38.W0 2A /r

V/V

AVX512F

Move 512-bit data from m512 to zmm using non-temporal

VMOVNTDQA zmm1, m512

hint if WC memory type.

Instruction Operand Encoding¹

Op/En

Tuple Type

Operand 1

Operand 2

Operand 3

Operand 4

N/A

ModRM:reg (w)

ModRM:r/m (r)

N/A

Full Mem

ModRM:reg (w)

ModRM:r/m (r)

N/A

Description

MOVNTDQA loads a double quadword from the source operand (second operand) to the destination operand (first

operand) using a non-temporal hint if the memory source is WC (write combining) memory type. For WC memory

type, the nontemporal hint may be implemented by loading a temporary internal buffer with the equivalent of an

aligned cache line without filling this data to the cache. Any memory-type aliased lines in the cache will be snooped

and flushed. Subsequent MOVNTDQA reads to unread portions of the WC cache line will receive data from the

temporary internal buffer if data is available. The temporary internal buffer may be flushed by the processor at any

time for any reason, for example:

• A load operation other than a MOVNTDQA which references memory already resident in a temporary internal

buffer.

• A non-WC reference to memory already resident in a temporary internal buffer.

• Interleaving of reads and writes to a single temporary internal buffer.

• Repeated (V)MOVNTDQA loads of a particular 16-byte item in a streaming line.

• Certain micro-architectural conditions including resource shortages, detection of

a mis-speculation condition, and various fault conditions

The non-temporal hint is implemented by using a write combining (WC) memory type protocol when reading the

data from memory. Using this protocol, the processor does not read the data into the cache hierarchy, nor does it

fetch the corresponding cache line from memory into the cache hierarchy. The memory type of the region being

read can override the non-temporal hint, if the memory address specified for the non-temporal read is not a WC

memory region. Information on non-temporal reads and writes can be found in “Caching of Temporal vs. Non-

Temporal Data” in Chapter 10 in the Intel® 64 and IA-32 Architecture Software Developer’s Manual, Volume 3A.

Because the WC protocol uses a weakly-ordered memory consistency model, a fencing operation implemented with

a MFENCE instruction should be used in conjunction with MOVNTDQA instructions if multiple processors might use

different memory types for the referenced memory locations or to synchronize reads of a processor with writes by

other agents in the system. A processor’s implementation of the streaming load hint does not override the effective

memory type, but the implementation of the hint is processor dependent. For example, a processor implementa-

tion may choose to ignore the hint and process the instruction as a normal MOVDQA for any memory type. Alter-

1. ModRM.MOD != 011B

MOVNTDQA—Load Double Quadword Non-Temporal Aligned Hint

Vol. 2B

4-97

INSTRUCTION SET REFERENCE, M-U

natively, another implementation may optimize cache reads generated by MOVNTDQA on WB memory type to

reduce cache evictions.

The 128-bit (V)MOVNTDQA addresses must be 16-byte aligned or the instruction will cause a #GP.

The 256-bit VMOVNTDQA addresses must be 32-byte aligned or the instruction will cause a #GP.

The 512-bit VMOVNTDQA addresses must be 64-byte aligned or the instruction will cause a #GP.

Operation

MOVNTDQA (128bit- Legacy SSE form)

DEST := SRC

DEST[MAXVL-1:128] (Unmodified)

VMOVNTDQA (VEX.128 and EVEX.128 encoded form)

DEST := SRC

DEST[MAXVL-1:128] := 0

VMOVNTDQA (VEX.256 and EVEX.256 encoded forms)

DEST[255:0] := SRC[255:0]

DEST[MAXVL-1:256] := 0

VMOVNTDQA (EVEX.512 encoded form)

DEST[511:0] := SRC[511:0]

DEST[MAXVL-1:512] := 0

Intel C/C++ Compiler Intrinsic Equivalent

VMOVNTDQA __m512i _mm512_stream_load_si512(__m512i const* p);

MOVNTDQA __m128i _mm_stream_load_si128 (const __m128i *p);

VMOVNTDQA __m256i _mm256_stream_load_si256 (__m256i const* p);

SIMD Floating-Point Exceptions

None

Other Exceptions

Non-EVEX-encoded instruction, see Table 2-18, “Type 1 Class Exception Conditions”.

EVEX-encoded instruction, see Table 2-45, “Type E1NF Class Exception Conditions”.

Additionally:

#UD

If VEX.vvvv != 1111B or EVEX.vvvv != 1111B.

4-98

Vol. 2B

MOVNTDQA—Load Double Quadword Non-Temporal Aligned Hint

INSTRUCTION SET REFERENCE, M-U

MOVNTDQ—Store Packed Integers Using Non-Temporal Hint

Opcode/

Op /

64/32

CPUID

Description

Instruction

bit Mode

Feature Flag

Support

66 0F E7 /r

V/V

SSE2

Move packed integer values in xmm1 to m128 using non-

MOVNTDQ m128, xmm1

temporal hint.

VEX.128.66.0F.WIG E7 /r

V/V

AVX

Move packed integer values in xmm1 to m128 using non-

VMOVNTDQ m128, xmm1

temporal hint.

VEX.256.66.0F.WIG E7 /r

V/V

AVX

Move packed integer values in ymm1 to m256 using non-

VMOVNTDQ m256, ymm1

temporal hint.

EVEX.128.66.0F.W0 E7 /r

V/V

AVX512VL

Move packed integer values in xmm1 to m128 using non-

VMOVNTDQ m128, xmm1

AVX512F

temporal hint.

EVEX.256.66.0F.W0 E7 /r

V/V

AVX512VL

Move packed integer values in zmm1 to m256 using non-

VMOVNTDQ m256, ymm1

AVX512F

temporal hint.

EVEX.512.66.0F.W0 E7 /r

V/V

AVX512F

Move packed integer values in zmm1 to m512 using non-

VMOVNTDQ m512, zmm1

temporal hint.

Instruction Operand Encoding¹

Op/En

Tuple Type

Operand 1

Operand 2

Operand 3

Operand 4

N/A

ModRM:r/m (w)

ModRM:reg (r)

N/A

Full Mem

ModRM:r/m (w)

ModRM:reg (r)

N/A

Description

Moves the packed integers in the source operand (second operand) to the destination operand (first operand) using

a non-temporal hint to prevent caching of the data during the write to memory. The source operand is an XMM

words, or quadwords). The destination operand is a 128-bit, 256-bit or 512-bit memory location. The memory

operand must be aligned on a 16-byte (128-bit version), 32-byte (VEX.256 encoded version) or 64-byte (512-bit

version) boundary otherwise a general-protection exception (#GP) will be generated.

The non-temporal hint is implemented by using a write combining (WC) memory type protocol when writing the

data to memory. Using this protocol, the processor does not write the data into the cache hierarchy, nor does it

fetch the corresponding cache line from memory into the cache hierarchy. The memory type of the region being

written to can override the non-temporal hint, if the memory address specified for the non-temporal store is in an

uncacheable (UC) or write protected (WP) memory region. For more information on non-temporal stores, see

“Caching of Temporal vs. Non-Temporal Data” in Chapter 10 in the IA-32 Intel Architecture Software Developer’s

Manual, Volume 1.

Because the WC protocol uses a weakly-ordered memory consistency model, a fencing operation implemented with

the SFENCE or MFENCE instruction should be used in conjunction with VMOVNTDQ instructions if multiple proces-

sors might use different memory types to read/write the destination memory locations.

Note: VEX.vvvv and EVEX.vvvv are reserved and must be 1111b, VEX.L must be 0; otherwise instructions will

#UD.

Operation

VMOVNTDQ(EVEX encoded versions)

VL = 128, 256, 512

DEST[VL-1:0] := SRC[VL-1:0]

DEST[MAXVL-1:VL] := 0

1. ModRM.MOD != 011B

MOVNTDQ—Store Packed Integers Using Non-Temporal Hint

Vol. 2B

4-99

INSTRUCTION SET REFERENCE, M-U

MOVNTI—Store Doubleword Using Non-Temporal Hint

Opcode /

Op/

64/32 bit

CPUID

Description

Instruction

Mode

Feature

Support

Flag

NP 0F C3 /r

V/V

SSE2

Move doubleword from r32 to m32 using non-temporal

hint.

MOVNTI m32, r32

NP REX.W + 0F C3 /r

V/N.E.

SSE2

Move quadword from r64 to m64 using non-temporal

hint.

MOVNTI m64, r64

Instruction Operand Encoding

Op/En

Operand 1

Operand 2

Operand 3

Operand 4

ModRM:r/m (w)

ModRM:reg (r)

N/A

Description

Moves the doubleword integer in the source operand (second operand) to the destination operand (first operand)

using a non-temporal hint to minimize cache pollution during the write to memory. The source operand is a

general-purpose register. The destination operand is a 32-bit memory location.

The non-temporal hint is implemented by using a write combining (WC) memory type protocol when writing the

data to memory. Using this protocol, the processor does not write the data into the cache hierarchy, nor does it

fetch the corresponding cache line from memory into the cache hierarchy. The memory type of the region being

written to can override the non-temporal hint, if the memory address specified for the non-temporal store is in an

uncacheable (UC) or write protected (WP) memory region. For more information on non-temporal stores, see

“Caching of Temporal vs. Non-Temporal Data” in Chapter 10 in the Intel® 64 and IA-32 Architectures Software

Developer’s Manual, Volume 1.

Because the WC protocol uses a weakly-ordered memory consistency model, a fencing operation implemented with

the SFENCE or MFENCE instruction should be used in conjunction with MOVNTI instructions if multiple processors

might use different memory types to read/write the destination memory locations.

In 64-bit mode, the instruction’s default operation size is 32 bits. Use of the REX.R prefix permits access to addi-

tional registers (R8-R15). Use of the REX.W prefix promotes operation to 64 bits. See the summary chart at the

beginning of this section for encoding data and limits.

Operation

DEST := SRC;

Intel C/C++ Compiler Intrinsic Equivalent

MOVNTI:

void _mm_stream_si32 (int *p, int a)

MOVNTI:

void _mm_stream_si64(__int64 *p, __int64 a)

SIMD Floating-Point Exceptions

None.

Protected Mode Exceptions

#GP(0)

For an illegal memory operand effective address in the CS, DS, ES, FS or GS segments.

#SS(0)

For an illegal address in the SS segment.

#PF(fault-code)

For a page fault.

#UD

If CPUID.01H:EDX.SSE2[bit 26] = 0.

If the LOCK prefix is used.

MOVNTI—Store Doubleword Using Non-Temporal Hint

Vol. 2B

4-101

INSTRUCTION SET REFERENCE, M-U

Real-Address Mode Exceptions

#GP

If any part of the operand lies outside the effective address space from 0 to FFFFH.

#UD

If CPUID.01H:EDX.SSE2[bit 26] = 0.

If the LOCK prefix is used.

Virtual-8086 Mode Exceptions

Same exceptions as in real address mode.

#PF(fault-code)

For a page fault.

Compatibility Mode Exceptions

Same exceptions as in protected mode.

64-Bit Mode Exceptions

#SS(0)

If a memory address referencing the SS segment is in a non-canonical form.

#GP(0)

If the memory address is in a non-canonical form.

#PF(fault-code)

For a page fault.

#UD

If CPUID.01H:EDX.SSE2[bit 26] = 0.

If the LOCK prefix is used.

#AC(0)

If alignment checking is enabled and an unaligned memory reference is made while the

current privilege level is 3.

4-102

Vol. 2B

MOVNTI—Store Doubleword Using Non-Temporal Hint

INSTRUCTION SET REFERENCE, M-U

MOVNTPD—Store Packed Double Precision Floating-Point Values Using Non-Temporal Hint

Opcode/

Op /

64/32

CPUID

Description

Instruction

bit Mode

Feature

Support

Flag

66 0F 2B /r

V/V

SSE2

Move packed double precision values in xmm1 to m128 using

MOVNTPD m128, xmm1

non-temporal hint.

VEX.128.66.0F.WIG 2B /r

V/V

AVX

Move packed double precision values in xmm1 to m128 using

VMOVNTPD m128, xmm1

non-temporal hint.

VEX.256.66.0F.WIG 2B /r

V/V

AVX

Move packed double precision values in ymm1 to m256 using

VMOVNTPD m256, ymm1

non-temporal hint.

EVEX.128.66.0F.W1 2B /r

V/V

AVX512VL

Move packed double precision values in xmm1 to m128 using

VMOVNTPD m128, xmm1

AVX512F

non-temporal hint.

EVEX.256.66.0F.W1 2B /r

V/V

AVX512VL

Move packed double precision values in ymm1 to m256 using

VMOVNTPD m256, ymm1

AVX512F

non-temporal hint.

EVEX.512.66.0F.W1 2B /r

V/V

AVX512F

Move packed double precision values in zmm1 to m512 using

VMOVNTPD m512, zmm1

non-temporal hint.

Instruction Operand Encoding¹

Op/En

Tuple Type

Operand 1

Operand 2

Operand 3

Operand 4

N/A

ModRM:r/m (w)

ModRM:reg (r)

N/A

Full Mem

ModRM:r/m (w)

ModRM:reg (r)

N/A

Description

Moves the packed double precision floating-point values in the source operand (second operand) to the destination

operand (first operand) using a non-temporal hint to prevent caching of the data during the write to memory. The

source operand is an XMM register, YMM register or ZMM register, which is assumed to contain packed double preci-

sion, floating-pointing data. The destination operand is a 128-bit, 256-bit or 512-bit memory location. The memory

operand must be aligned on a 16-byte (128-bit version), 32-byte (VEX.256 encoded version) or 64-byte

(EVEX.512 encoded version) boundary otherwise a general-protection exception (#GP) will be generated.

The non-temporal hint is implemented by using a write combining (WC) memory type protocol when writing the

data to memory. Using this protocol, the processor does not write the data into the cache hierarchy, nor does it

fetch the corresponding cache line from memory into the cache hierarchy. The memory type of the region being

written to can override the non-temporal hint, if the memory address specified for the non-temporal store is in an

uncacheable (UC) or write protected (WP) memory region. For more information on non-temporal stores, see

“Caching of Temporal vs. Non-Temporal Data” in Chapter 10 in the IA-32 Intel Architecture Software Developer’s

Manual, Volume 1.

Because the WC protocol uses a weakly-ordered memory consistency model, a fencing operation implemented with

the SFENCE or MFENCE instruction should be used in conjunction with MOVNTPD instructions if multiple processors

might use different memory types to read/write the destination memory locations.

Note: VEX.vvvv and EVEX.vvvv are reserved and must be 1111b, VEX.L must be 0; otherwise instructions will

#UD.

Operation

VMOVNTPD (EVEX encoded versions)

VL = 128, 256, 512

DEST[VL-1:0] := SRC[VL-1:0]

DEST[MAXVL-1:VL] := 0

1. ModRM.MOD != 011B

MOVNTPD—Store Packed Double Precision Floating-Point Values Using Non-Temporal Hint

Vol. 2B

4-103

INSTRUCTION SET REFERENCE, M-U

MOVNTPS—Store Packed Single Precision Floating-Point Values Using Non-Temporal Hint

Opcode/

Op /

64/32

CPUID

Description

Instruction

bit Mode

Feature

Support

Flag

NP 0F 2B /r

V/V

SSE

Move packed single precision values xmm1 to mem using

MOVNTPS m128, xmm1

non-temporal hint.

VEX.128.0F.WIG 2B /r

V/V

AVX

Move packed single precision values xmm1 to mem using

VMOVNTPS m128, xmm1

non-temporal hint.

VEX.256.0F.WIG 2B /r

V/V

AVX

Move packed single precision values ymm1 to mem using

VMOVNTPS m256, ymm1

non-temporal hint.

EVEX.128.0F.W0 2B /r

V/V

AVX512VL

Move packed single precision values in xmm1 to m128

VMOVNTPS m128, xmm1

AVX512F

using non-temporal hint.

EVEX.256.0F.W0 2B /r

V/V

AVX512VL

Move packed single precision values in ymm1 to m256

VMOVNTPS m256, ymm1

AVX512F

using non-temporal hint.

EVEX.512.0F.W0 2B /r

V/V

AVX512F

Move packed single precision values in zmm1 to m512

VMOVNTPS m512, zmm1

using non-temporal hint.

Instruction Operand Encoding¹

Op/En

Tuple Type

Operand 1

Operand 2

Operand 3

Operand 4

N/A

ModRM:r/m (w)

ModRM:reg (r)

N/A

Full Mem

ModRM:r/m (w)

ModRM:reg (r)

N/A

Description

Moves the packed single precision floating-point values in the source operand (second operand) to the destination

operand (first operand) using a non-temporal hint to prevent caching of the data during the write to memory. The

source operand is an XMM register, YMM register or ZMM register, which is assumed to contain packed single preci-

sion, floating-pointing. The destination operand is a 128-bit, 256-bit or 512-bit memory location. The memory