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Intel 64 and IA-32 Architectures. Software Developer’s Manual (Collection, 2023) - page 70

INSTRUCTION SET REFERENCE, A-L

CVTSD2SS—Convert Scalar Double Precision Floating-Point Value to Scalar Single Precision

Floating-Point Value

Opcode/

Op /

64/32

CPUID

Description

Instruction

En

bit Mode

Feature

Support

Flag

F2 0F 5A /r

A

V/V

SSE2

Convert one double precision floating-point value in

CVTSD2SS xmm1, xmm2/m64

xmm2/m64 to one single precision floating-point value

in xmm1.

VEX.LIG.F2.0F.WIG 5A /r

B

V/V

AVX

Convert one double precision floating-point value in

VCVTSD2SS xmm1,xmm2,

xmm3/m64 to one single precision floating-point value

xmm3/m64

and merge with high bits in xmm2.

EVEX.LLIG.F2.0F.W1 5A /r

C

V/V

AVX512F

Convert one double precision floating-point value in

VCVTSD2SS xmm1 {k1}{z}, xmm2,

xmm3/m64 to one single precision floating-point value

xmm3/m64{er}

and merge with high bits in xmm2 under writemask k1.

Instruction Operand Encoding

Op/En

Tuple Type

Operand 1

Operand 2

Operand 3

Operand 4

A

N/A

ModRM:reg (r, w)

ModRM:r/m (r)

N/A

N/A

B

N/A

ModRM:reg (w)

VEX.vvvv (r)

ModRM:r/m (r)

N/A

C

Tuple1 Scalar

ModRM:reg (w)

EVEX.vvvv (r)

ModRM:r/m (r)

N/A

Description

Converts a double precision floating-point value in the “convert-from” source operand (the second operand in SSE2

version, otherwise the third operand) to a single precision floating-point value in the destination operand.

When the “convert-from” operand is an XMM register, the double precision floating-point value is contained in the

low quadword of the register. The result is stored in the low doubleword of the destination operand. When the

conversion is inexact, the value returned is rounded according to the rounding control bits in the MXCSR register.

128-bit Legacy SSE version: The “convert-from” source operand (the second operand) is an XMM register or

memory location. Bits (MAXVL-1:32) of the corresponding destination register remain unchanged. The destination

operand is an XMM register.

VEX.128 and EVEX encoded versions: The “convert-from” source operand (the third operand) can be an XMM

register or a 64-bit memory location. The first source and destination operands are XMM registers. Bits (127:32) of

the XMM register destination are copied from the corresponding bits in the first source operand. Bits (MAXVL-

1:128) of the destination register are zeroed.

EVEX encoded version: the converted result in written to the low doubleword element of the destination under the

writemask.

Software should ensure VCVTSD2SS is encoded with VEX.L=0. Encoding VCVTSD2SS with VEX.L=1 may encounter

unpredictable behavior across different processor generations.

CVTSD2SS—Convert Scalar Double Precision Floating-Point Value to Scalar Single Precision Floating-Point Value

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INSTRUCTION SET REFERENCE, A-L

CVTSI2SD—Convert Doubleword Integer to Scalar Double Precision Floating-Point Value

Opcode/

Op /

64/32

CPUID

Description

Instruction

En

bit Mode

Feature

Support

Flag

F2 0F 2A /r

A

V/V

SSE2

Convert one signed doubleword integer from

CVTSI2SD xmm1, r32/m32

r32/m32 to one double precision floating-point

value in xmm1.

F2 REX.W 0F 2A /r

A

V/N.E.

SSE2

Convert one signed quadword integer from r/m64

CVTSI2SD xmm1, r/m64

to one double precision floating-point value in

xmm1.

VEX.LIG.F2.0F.W0 2A /r

B

V/V

AVX

Convert one signed doubleword integer from

VCVTSI2SD xmm1, xmm2, r/m32

r/m32 to one double precision floating-point

value in xmm1.

VEX.LIG.F2.0F.W1 2A /r

B

V/N.E.¹

AVX

Convert one signed quadword integer from r/m64

VCVTSI2SD xmm1, xmm2, r/m64

to one double precision floating-point value in

xmm1.

EVEX.LLIG.F2.0F.W0 2A /r

C

V/V

AVX512F

Convert one signed doubleword integer from

VCVTSI2SD xmm1, xmm2, r/m32

r/m32 to one double precision floating-point

value in xmm1.

EVEX.LLIG.F2.0F.W1 2A /r

C

V/N.E.¹

AVX512F

Convert one signed quadword integer from r/m64

VCVTSI2SD xmm1, xmm2, r/m64{er}

to one double precision floating-point value in

xmm1.

NOTES:

1. VEX.W1/EVEX.W1 in non-64 bit is ignored; the instructions behaves as if the W0 version is used.

Instruction Operand Encoding

Op/En

Tuple Type

Operand 1

Operand 2

Operand 3

Operand 4

A

N/A

ModRM:reg (w)

ModRM:r/m (r)

N/A

N/A

B

N/A

ModRM:reg (w)

VEX.vvvv (r)

ModRM:r/m (r)

N/A

C

Tuple1 Scalar

ModRM:reg (w)

EVEX.vvvv (r)

ModRM:r/m (r)

N/A

Description

Converts a signed doubleword integer (or signed quadword integer if operand size is 64 bits) in the “convert-from”

source operand to a double precision floating-point value in the destination operand. The result is stored in the low

quadword of the destination operand, and the high quadword left unchanged. When conversion is inexact, the

value returned is rounded according to the rounding control bits in the MXCSR register.

The second source operand can be a general-purpose register or a 32/64-bit memory location. The first source and

destination operands are XMM registers.

128-bit Legacy SSE version: Use of the REX.W prefix promotes the instruction to 64-bit operands. The “convert-

from” source operand (the second operand) is a general-purpose register or memory location. The destination is

an XMM register Bits (MAXVL-1:64) of the corresponding destination register remain unchanged.

VEX.128 and EVEX encoded versions: The “convert-from” source operand (the third operand) can be a general-

purpose register or a memory location. The first source and destination operands are XMM registers. Bits (127:64)

of the XMM register destination are copied from the corresponding bits in the first source operand. Bits (MAXVL-

1:128) of the destination register are zeroed.

EVEX.W0 version: attempt to encode this instruction with EVEX embedded rounding is ignored.

VEX.W1 and EVEX.W1 versions: promotes the instruction to use 64-bit input value in 64-bit mode.

Software should ensure VCVTSI2SD is encoded with VEX.L=0. Encoding VCVTSI2SD with VEX.L=1 may encounter

unpredictable behavior across different processor generations.

CVTSI2SD—Convert Doubleword Integer to Scalar Double Precision Floating-Point Value

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INSTRUCTION SET REFERENCE, A-L

CVTSI2SS—Convert Doubleword Integer to Scalar Single Precision Floating-Point Value

Opcode/

Op /

64/32

CPUID

Description

Instruction

En

bit Mode

Feature

Support

Flag

F3 0F 2A /r

A

V/V

SSE

Convert one signed doubleword integer from r/m32

CVTSI2SS xmm1, r/m32

to one single precision floating-point value in xmm1.

F3 REX.W 0F 2A /r

A

V/N.E.

SSE

Convert one signed quadword integer from r/m64

CVTSI2SS xmm1, r/m64

to one single precision floating-point value in xmm1.

VEX.LIG.F3.0F.W0 2A /r

B

V/V

AVX

Convert one signed doubleword integer from r/m32

VCVTSI2SS xmm1, xmm2, r/m32

to one single precision floating-point value in xmm1.

VEX.LIG.F3.0F.W1 2A /r

B

V/N.E.¹

AVX

Convert one signed quadword integer from r/m64

VCVTSI2SS xmm1, xmm2, r/m64

to one single precision floating-point value in xmm1.

EVEX.LLIG.F3.0F.W0 2A /r

C

V/V

AVX512F

Convert one signed doubleword integer from r/m32

VCVTSI2SS xmm1, xmm2, r/m32{er}

to one single precision floating-point value in xmm1.

EVEX.LLIG.F3.0F.W1 2A /r

C

V/N.E.¹

AVX512F

Convert one signed quadword integer from r/m64

VCVTSI2SS xmm1, xmm2, r/m64{er}

to one single precision floating-point value in xmm1.

NOTES:

1. VEX.W1/EVEX.W1 in non-64 bit is ignored; the instructions behaves as if the W0 version is used.

Instruction Operand Encoding

Op/En

Tuple Type

Operand 1

Operand 2

Operand 3

Operand 4

A

N/A

ModRM:reg (w)

ModRM:r/m (r)

N/A

N/A

B

N/A

ModRM:reg (w)

VEX.vvvv (r)

ModRM:r/m (r)

N/A

C

Tuple1 Scalar

ModRM:reg (w)

EVEX.vvvv (r)

ModRM:r/m (r)

N/A

Description

Converts a signed doubleword integer (or signed quadword integer if operand size is 64 bits) in the “convert-from”

source operand to a single precision floating-point value in the destination operand (first operand). The “convert-

from” source operand can be a general-purpose register or a memory location. The destination operand is an XMM

register. The result is stored in the low doubleword of the destination operand, and the upper three doublewords

are left unchanged. When a conversion is inexact, the value returned is rounded according to the rounding control

bits in the MXCSR register or the embedded rounding control bits.

128-bit Legacy SSE version: In 64-bit mode, Use of the REX.W prefix promotes the instruction to use 64-bit input

value. The “convert-from” source operand (the second operand) is a general-purpose register or memory location.

Bits (MAXVL-1:32) of the corresponding destination register remain unchanged.

VEX.128 and EVEX encoded versions: The “convert-from” source operand (the third operand) can be a general-

purpose register or a memory location. The first source and destination operands are XMM registers. Bits (127:32)

of the XMM register destination are copied from corresponding bits in the first source operand. Bits (MAXVL-1:128)

of the destination register are zeroed.

EVEX encoded version: the converted result in written to the low doubleword element of the destination under the

writemask.

Software should ensure VCVTSI2SS is encoded with VEX.L=0. Encoding VCVTSI2SS with VEX.L=1 may encounter

unpredictable behavior across different processor generations.

CVTSI2SS—Convert Doubleword Integer to Scalar Single Precision Floating-Point Value

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INSTRUCTION SET REFERENCE, A-L

CVTSS2SD—Convert Scalar Single Precision Floating-Point Value to Scalar Double Precision

Floating-Point Value

Opcode/

Op /

64/32

CPUID

Description

Instruction

En

bit Mode

Feature

Support

Flag

F3 0F 5A /r

A

V/V

SSE2

Convert one single precision floating-point value in

CVTSS2SD xmm1, xmm2/m32

xmm2/m32 to one double precision floating-point value

in xmm1.

VEX.LIG.F3.0F.WIG 5A /r

B

V/V

AVX

Convert one single precision floating-point value in

VCVTSS2SD xmm1, xmm2,

xmm3/m32 to one double precision floating-point value

xmm3/m32

and merge with high bits of xmm2.

EVEX.LLIG.F3.0F.W0 5A /r

C

V/V

AVX512F

Convert one single precision floating-point value in

VCVTSS2SD xmm1 {k1}{z}, xmm2,

xmm3/m32 to one double precision floating-point value

xmm3/m32{sae}

and merge with high bits of xmm2 under writemask k1.

Instruction Operand Encoding

Op/En

Tuple Type

Operand 1

Operand 2

Operand 3

Operand 4

A

N/A

ModRM:reg (r, w)

ModRM:r/m (r)

N/A

N/A

B

N/A

ModRM:reg (w)

VEX.vvvv (r)

ModRM:r/m (r)

N/A

C

Tuple1 Scalar

ModRM:reg (w)

EVEX.vvvv (r)

ModRM:r/m (r)

N/A

Description

Converts a single precision floating-point value in the “convert-from” source operand to a double precision floating-

point value in the destination operand. When the “convert-from” source operand is an XMM register, the single

precision floating-point value is contained in the low doubleword of the register. The result is stored in the low

quadword of the destination operand.

128-bit Legacy SSE version: The “convert-from” source operand (the second operand) is an XMM register or

memory location. Bits (MAXVL-1:64) of the corresponding destination register remain unchanged. The destination

operand is an XMM register.

VEX.128 and EVEX encoded versions: The “convert-from” source operand (the third operand) can be an XMM

register or a 32-bit memory location. The first source and destination operands are XMM registers. Bits (127:64) of

the XMM register destination are copied from the corresponding bits in the first source operand. Bits (MAXVL-

1:128) of the destination register are zeroed.

Software should ensure VCVTSS2SD is encoded with VEX.L=0. Encoding VCVTSS2SD with VEX.L=1 may encounter

unpredictable behavior across different processor generations.

Operation

VCVTSS2SD (EVEX encoded version)

IF k1[0] or *no writemask*

THEN DEST[63:0] := Convert_Single_Precision_To_Double_Precision_Floating_Point(SRC2[31:0]);

ELSE

IF *merging-masking*

; merging-masking

THEN *DEST[63:0] remains unchanged*

ELSE

; zeroing-masking

THEN DEST[63:0] = 0

FI;

FI;

DEST[127:64] := SRC1[127:64]

DEST[MAXVL-1:128] := 0

CVTSS2SD—Convert Scalar Single Precision Floating-Point Value to Scalar Double Precision Floating-Point Value

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INSTRUCTION SET REFERENCE, A-L

CVTSS2SI—Convert Scalar Single Precision Floating-Point Value to Doubleword Integer

Opcode/

Op /

64/32

CPUID

Description

Instruction

En

bit Mode

Feature

Support

Flag

F3 0F 2D /r

A

V/V

SSE

Convert one single precision floating-point value from

CVTSS2SI r32, xmm1/m32

xmm1/m32 to one signed doubleword integer in r32.

F3 REX.W 0F 2D /r

A

V/N.E.

SSE

Convert one single precision floating-point value from

CVTSS2SI r64, xmm1/m32

xmm1/m32 to one signed quadword integer in r64.

VEX.LIG.F3.0F.W0 2D /r ¹

A

V/V

AVX

Convert one single precision floating-point value from

VCVTSS2SI r32, xmm1/m32

xmm1/m32 to one signed doubleword integer in r32.

VEX.LIG.F3.0F.W1 2D /r ¹

A

V/N.E.²

AVX

Convert one single precision floating-point value from

VCVTSS2SI r64, xmm1/m32

xmm1/m32 to one signed quadword integer in r64.

EVEX.LLIG.F3.0F.W0 2D /r

B

V/V

AVX512F

Convert one single precision floating-point value from

VCVTSS2SI r32, xmm1/m32{er}

xmm1/m32 to one signed doubleword integer in r32.

EVEX.LLIG.F3.0F.W1 2D /r

B

V/N.E.²

AVX512F

Convert one single precision floating-point value from

VCVTSS2SI r64, xmm1/m32{er}

xmm1/m32 to one signed quadword integer in r64.

NOTES:

1. Software should ensure VCVTSS2SI is encoded with VEX.L=0. Encoding VCVTSS2SI with VEX.L=1 may

encounter unpredictable behavior across different processor generations.

2. VEX.W1/EVEX.W1 in non-64 bit is ignored; the instructions behaves as if the W0 version is used.

Instruction Operand Encoding

Op/En

Tuple Type

Operand 1

Operand 2

Operand 3

Operand 4

A

N/A

ModRM:reg (w)

ModRM:r/m (r)

N/A

N/A

B

Tuple1 Fixed

ModRM:reg (w)

ModRM:r/m (r)

N/A

N/A

Description

Converts a single precision floating-point value in the source operand (the second operand) to a signed doubleword

integer (or signed quadword integer if operand size is 64 bits) in the destination operand (the first operand). The

source operand can be an XMM register or a memory location. The destination operand is a general-purpose

register. When the source operand is an XMM register, the single precision floating-point value is contained in the

low doubleword of the register.

When a conversion is inexact, the value returned is rounded according to the rounding control bits in the MXCSR

register or the embedded rounding control bits. If a converted result cannot be represented in the destination

format, the floating-point invalid exception is raised, and if this exception is masked, the indefinite integer value

(2^w-1, where w represents the number of bits in the destination format) is returned.

Legacy SSE instructions: In 64-bit mode, Use of the REX.W prefix promotes the instruction to produce 64-bit data.

See the summary chart at the beginning of this section for encoding data and limits.

VEX.W1 and EVEX.W1 versions: promotes the instruction to produce 64-bit data in 64-bit mode.

Note: VEX.vvvv and EVEX.vvvv are reserved and must be 1111b, otherwise instructions will #UD.

Software should ensure VCVTSS2SI is encoded with VEX.L=0. Encoding VCVTSS2SI with VEX.L=1 may encounter

unpredictable behavior across different processor generations.

CVTSS2SI—Convert Scalar Single Precision Floating-Point Value to Doubleword Integer

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INSTRUCTION SET REFERENCE, A-L

CVTTPD2DQ—Convert with Truncation Packed Double Precision Floating-Point Values to

Packed Doubleword Integers

Opcode/

Op /

64/32

CPUID

Description

Instruction

En

bit Mode

Feature

Support

Flag

66 0F E6 /r

A

V/V

SSE2

Convert two packed double precision floating-point

CVTTPD2DQ xmm1, xmm2/m128

values in xmm2/mem to two signed doubleword

integers in xmm1 using truncation.

VEX.128.66.0F.WIG E6 /r

A

V/V

AVX

Convert two packed double precision floating-point

VCVTTPD2DQ xmm1, xmm2/m128

values in xmm2/mem to two signed doubleword

integers in xmm1 using truncation.

VEX.256.66.0F.WIG E6 /r

A

V/V

AVX

Convert four packed double precision floating-point

VCVTTPD2DQ xmm1, ymm2/m256

values in ymm2/mem to four signed doubleword

integers in xmm1 using truncation.

EVEX.128.66.0F.W1 E6 /r

B

V/V

AVX512VL

Convert two packed double precision floating-point

VCVTTPD2DQ xmm1 {k1}{z},

AVX512F

values in xmm2/m128/m64bcst to two signed

xmm2/m128/m64bcst

doubleword integers in xmm1 using truncation subject

to writemask k1.

EVEX.256.66.0F.W1 E6 /r

B

V/V

AVX512VL

Convert four packed double precision floating-point

VCVTTPD2DQ xmm1 {k1}{z},

AVX512F

values in ymm2/m256/m64bcst to four signed

ymm2/m256/m64bcst

doubleword integers in xmm1 using truncation subject

to writemask k1.

EVEX.512.66.0F.W1 E6 /r

B

V/V

AVX512F

Convert eight packed double precision floating-point

VCVTTPD2DQ ymm1 {k1}{z},

values in zmm2/m512/m64bcst to eight signed

zmm2/m512/m64bcst{sae}

doubleword integers in ymm1 using truncation subject

to writemask k1.

Instruction Operand Encoding

Op/En

Tuple Type

Operand 1

Operand 2

Operand 3

Operand 4

A

N/A

ModRM:reg (w)

ModRM:r/m (r)

N/A

N/A

B

Full

ModRM:reg (w)

ModRM:r/m (r)

N/A

N/A

Description

Converts two, four or eight packed double precision floating-point values in the source operand (second operand)

to two, four or eight packed signed doubleword integers in the destination operand (first operand).

When a conversion is inexact, a truncated (round toward zero) value is returned. If a converted result is larger than

the maximum signed doubleword integer, the floating-point invalid exception is raised, and if this exception is

masked, the indefinite integer value (80000000H) is returned.

EVEX encoded versions: The source operand is a ZMM/YMM/XMM register, a 512/256/128-bit memory location, or

a 512/256/128-bit vector broadcasted from a 64-bit memory location. The destination operand is a

YMM/XMM/XMM (low 64 bits) register conditionally updated with writemask k1. The upper bits (MAXVL-1:256) of

the corresponding destination are zeroed.

VEX.256 encoded version: The source operand is a YMM register or 256- bit memory location. The destination

operand is an XMM register. The upper bits (MAXVL-1:128) of the corresponding ZMM register destination are

zeroed.

VEX.128 encoded version: The source operand is an XMM register or 128- bit memory location. The destination

operand is a XMM register. The upper bits (MAXVL-1:64) of the corresponding ZMM register destination are zeroed.

128-bit Legacy SSE version: The source operand is an XMM register or 128- bit memory location. The destination

operand is an XMM register. The upper bits (MAXVL-1:128) of the corresponding ZMM register destination are

unmodified.

Note: VEX.vvvv and EVEX.vvvv are reserved and must be 1111b, otherwise instructions will #UD.

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INSTRUCTION SET REFERENCE, A-L

SRC

X3

X2

X1

X0

DEST

0

X3

X2

X1

X0

Figure 3-15. VCVTTPD2DQ (VEX.256 encoded version)

Operation

VCVTTPD2DQ (EVEX encoded versions) when src operand is a register

(KL, VL) = (2, 128), (4, 256), (8, 512)

FOR j := 0 TO KL-1

i := j * 32

k := j * 64

IF k1[j] OR *no writemask*

THEN DEST[i+31:i] :=

Convert_Double_Precision_Floating_Point_To_Integer_Truncate(SRC[k+63:k])

ELSE

IF *merging-masking*

; merging-masking

THEN *DEST[i+31:i] remains unchanged*

ELSE

; zeroing-masking

DEST[i+31:i] := 0

FI

FI;

ENDFOR

DEST[MAXVL-1:VL/2] := 0

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CVTTPD2DQ—Convert with Truncation Packed Double Precision Floating-Point Values to Packed Doubleword Integers

INSTRUCTION SET REFERENCE, A-L

CVTTPD2PI—Convert With Truncation Packed Double Precision Floating-Point Values to Packed

Dword Integers

Opcode/

Op/

64-Bit

Compat/

Description

Instruction

En

Mode

Leg Mode

66 0F 2C /r

RM

Valid

Valid

Convert two packer double precision floating-

CVTTPD2PI mm, xmm/m128

point values from xmm/m128 to two packed

signed doubleword integers in mm using

truncation.

Instruction Operand Encoding

Op/En

Operand 1

Operand 2

Operand 3

Operand 4

RM

ModRM:reg (w)

ModRM:r/m (r)

N/A

N/A

Description

Converts two packed double precision floating-point values in the source operand (second operand) to two packed

signed doubleword integers in the destination operand (first operand). The source operand can be an XMM register

or a 128-bit memory location. The destination operand is an MMX technology register.

When a conversion is inexact, a truncated (round toward zero) result is returned. If a converted result is larger

than the maximum signed doubleword integer, the floating-point invalid exception is raised, and if this exception is

masked, the indefinite integer value (80000000H) is returned.

This instruction causes a transition from x87 FPU to MMX technology operation (that is, the x87 FPU top-of-stack

pointer is set to 0 and the x87 FPU tag word is set to all 0s [valid]). If this instruction is executed while an x87 FPU

floating-point exception is pending, the exception is handled before the CVTTPD2PI instruction is executed.

In 64-bit mode, use of the REX.R prefix permits this instruction to access additional registers (XMM8-XMM15).

Operation

DEST[31:0] := Convert_Double_Precision_Floating_Point_To_Integer32_Truncate(SRC[63:0]);

DEST[63:32] := Convert_Double_Precision_Floating_Point_To_Integer32_

Truncate(SRC[127:64]);

Intel C/C++ Compiler Intrinsic Equivalent

CVTTPD1PI:

__m64 _mm_cvttpd_pi32(__m128d a)

SIMD Floating-Point Exceptions

Invalid, Precision

Other Mode Exceptions

See Table 23-4, “Exception Conditions for Legacy SIMD/MMX Instructions with FP Exception and 16-Byte Align-

ment” in the Intel® 64 and IA-32 Architectures Software Developer’s Manual, Volume 3B.

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INSTRUCTION SET REFERENCE, A-L

CVTTPS2DQ—Convert With Truncation Packed Single Precision Floating-Point Values to Packed

Signed Doubleword Integer Values

Opcode/

Op /

64/32

CPUID

Description

Instruction

En

bit Mode

Feature

Support

Flag

F3 0F 5B /r

A

V/V

SSE2

Convert four packed single precision floating-point

CVTTPS2DQ xmm1, xmm2/m128

values from xmm2/mem to four packed signed

doubleword values in xmm1 using truncation.

VEX.128.F3.0F.WIG 5B /r

A

V/V

AVX

Convert four packed single precision floating-point

VCVTTPS2DQ xmm1, xmm2/m128

values from xmm2/mem to four packed signed

doubleword values in xmm1 using truncation.

VEX.256.F3.0F.WIG 5B /r

A

V/V

AVX

Convert eight packed single precision floating-point

VCVTTPS2DQ ymm1, ymm2/m256

values from ymm2/mem to eight packed signed

doubleword values in ymm1 using truncation.

EVEX.128.F3.0F.W0 5B /r

B

V/V

AVX512VL

Convert four packed single precision floating-point

VCVTTPS2DQ xmm1 {k1}{z},

AVX512F

values from xmm2/m128/m32bcst to four packed

xmm2/m128/m32bcst

signed doubleword values in xmm1 using truncation

subject to writemask k1.

EVEX.256.F3.0F.W0 5B /r

B

V/V

AVX512VL

Convert eight packed single precision floating-point

VCVTTPS2DQ ymm1 {k1}{z},

AVX512F

values from ymm2/m256/m32bcst to eight packed

ymm2/m256/m32bcst

signed doubleword values in ymm1 using truncation

subject to writemask k1.

EVEX.512.F3.0F.W0 5B /r

B

V/V

AVX512F

Convert sixteen packed single precision floating-point

VCVTTPS2DQ zmm1 {k1}{z},

values from zmm2/m512/m32bcst to sixteen packed

zmm2/m512/m32bcst {sae}

signed doubleword values in zmm1 using truncation

subject to writemask k1.

Instruction Operand Encoding

Op/En

Tuple Type

Operand 1

Operand 2

Operand 3

Operand 4

A

N/A

ModRM:reg (w)

ModRM:r/m (r)

N/A

N/A

B

Full

ModRM:reg (w)

ModRM:r/m (r)

N/A

N/A

Description

Converts four, eight or sixteen packed single precision floating-point values in the source operand to four, eight or

sixteen signed doubleword integers in the destination operand.

When a conversion is inexact, a truncated (round toward zero) value is returned. If a converted result is larger than

the maximum signed doubleword integer, the floating-point invalid exception is raised, and if this exception is

masked, the indefinite integer value (80000000H) is returned.

EVEX encoded versions: The source operand is a ZMM/YMM/XMM register, a 512/256/128-bit memory location or

a 512/256/128-bit vector broadcasted from a 32-bit memory location. The destination operand is a

ZMM/YMM/XMM register conditionally updated with writemask k1.

VEX.256 encoded version: The source operand is a YMM register or 256- bit memory location. The destination

operand is a YMM register. The upper bits (MAXVL-1:256) of the corresponding ZMM register destination are

zeroed.

VEX.128 encoded version: The source operand is an XMM register or 128- bit memory location. The destination

operand is a XMM register. The upper bits (MAXVL-1:128) of the corresponding ZMM register destination are

zeroed.

128-bit Legacy SSE version: The source operand is an XMM register or 128- bit memory location. The destination

operand is an XMM register. The upper bits (MAXVL-1:128) of the corresponding ZMM register destination are

unmodified.

Note: VEX.vvvv and EVEX.vvvv are reserved and must be 1111b otherwise instructions will #UD.

CVTTPS2DQ—Convert With Truncation Packed Single Precision Floating-Point Values to Packed Signed Doubleword Integer Values

3-306

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INSTRUCTION SET REFERENCE, A-L

CVTTPS2PI—Convert With Truncation Packed Single Precision Floating-Point Values to Packed

Dword Integers

Opcode/

Op/

64-Bit

Compat/

Description

Instruction

En

Mode

Leg Mode

NP 0F 2C /r

RM

Valid

Valid

Convert two single precision floating-point

values from xmm/m64 to two signed

CVTTPS2PI mm, xmm/m64

doubleword signed integers in mm using

truncation.

Instruction Operand Encoding

Op/En

Operand 1

Operand 2

Operand 3

Operand 4

RM

ModRM:reg (w)

ModRM:r/m (r)

N/A

N/A

Description

Converts two packed single precision floating-point values in the source operand (second operand) to two packed

signed doubleword integers in the destination operand (first operand). The source operand can be an XMM register

or a 64-bit memory location. The destination operand is an MMX technology register. When the source operand is

an XMM register, the two single precision floating-point values are contained in the low quadword of the register.

When a conversion is inexact, a truncated (round toward zero) result is returned. If a converted result is larger

than the maximum signed doubleword integer, the floating-point invalid exception is raised, and if this exception is

masked, the indefinite integer value (80000000H) is returned.

This instruction causes a transition from x87 FPU to MMX technology operation (that is, the x87 FPU top-of-stack

pointer is set to 0 and the x87 FPU tag word is set to all 0s [valid]). If this instruction is executed while an x87 FPU

floating-point exception is pending, the exception is handled before the CVTTPS2PI instruction is executed.

In 64-bit mode, use of the REX.R prefix permits this instruction to access additional registers (XMM8-XMM15).

Operation

DEST[31:0] := Convert_Single_Precision_Floating_Point_To_Integer_Truncate(SRC[31:0]);

DEST[63:32] := Convert_Single_Precision_Floating_Point_To_Integer_Truncate(SRC[63:32]);

Intel C/C++ Compiler Intrinsic Equivalent

CVTTPS2PI:

__m64 _mm_cvttps_pi32(__m128 a)

SIMD Floating-Point Exceptions

Invalid, Precision

Other Exceptions

See Table 23-5, “Exception Conditions for Legacy SIMD/MMX Instructions with XMM and FP Exception” in the

Intel® 64 and IA-32 Architectures Software Developer’s Manual, Volume 3B.

CVTTPS2PI—Convert With Truncation Packed Single Precision Floating-Point Values to Packed Dword Integers

Vol. 2A

3-309

INSTRUCTION SET REFERENCE, A-L

CVTTSD2SI—Convert With Truncation Scalar Double Precision Floating-Point Value to Signed

Integer

Opcode/

Op /

64/32

CPUID

Description

Instruction

En

bit Mode

Feature

Support

Flag

F2 0F 2C /r

A

V/V

SSE2

Convert one double precision floating-point value from

CVTTSD2SI r32, xmm1/m64

xmm1/m64 to one signed doubleword integer in r32

using truncation.

F2 REX.W 0F 2C /r

A

V/N.E.

SSE2

Convert one double precision floating-point value from

CVTTSD2SI r64, xmm1/m64

xmm1/m64 to one signed quadword integer in r64

using truncation.

VEX.LIG.F2.0F.W0 2C /r ¹

A

V/V

AVX

Convert one double precision floating-point value from

VCVTTSD2SI r32, xmm1/m64

xmm1/m64 to one signed doubleword integer in r32

using truncation.

VEX.LIG.F2.0F.W1 2C /r ¹

B

V/N.E.²

AVX

Convert one double precision floating-point value from

VCVTTSD2SI r64, xmm1/m64

xmm1/m64 to one signed quadword integer in r64

using truncation.

EVEX.LLIG.F2.0F.W0 2C /r

B

V/V

AVX512F

Convert one double precision floating-point value from

VCVTTSD2SI r32, xmm1/m64{sae}

xmm1/m64 to one signed doubleword integer in r32

using truncation.

EVEX.LLIG.F2.0F.W1 2C /r

B

V/N.E.²

AVX512F

Convert one double precision floating-point value from

VCVTTSD2SI r64, xmm1/m64{sae}

xmm1/m64 to one signed quadword integer in r64

using truncation.

NOTES:

1. Software should ensure VCVTTSD2SI is encoded with VEX.L=0. Encoding VCVTTSD2SI with VEX.L=1 may encounter unpredictable

behavior across different processor generations.

2. For this specific instruction, VEX.W/EVEX.W in non-64 bit is ignored; the instructions behaves as if the W0 version is used.

Instruction Operand Encoding

Op/En

Tuple Type

Operand 1

Operand 2

Operand 3

Operand 4

A

N/A

ModRM:reg (w)

ModRM:r/m (r)

N/A

N/A

B

Tuple1 Fixed

ModRM:reg (w)

ModRM:r/m (r)

N/A

N/A

Description

Converts a double precision floating-point value in the source operand (the second operand) to a signed double-

word integer (or signed quadword integer if operand size is 64 bits) in the destination operand (the first operand).

The source operand can be an XMM register or a 64-bit memory location. The destination operand is a general

purpose register. When the source operand is an XMM register, the double precision floating-point value is

contained in the low quadword of the register.

When a conversion is inexact, the value returned is rounded according to the rounding control bits in the MXCSR

register.

If a converted result exceeds the range limits of signed doubleword integer (in non-64-bit modes or 64-bit mode

with REX.W/VEX.W/EVEX.W=0), the floating-point invalid exception is raised, and if this exception is masked, the

indefinite integer value (80000000H) is returned.

If a converted result exceeds the range limits of signed quadword integer (in 64-bit mode and

REX.W/VEX.W/EVEX.W = 1), the floating-point invalid exception is raised, and if this exception is masked, the

indefinite integer value (80000000_00000000H) is returned.

Legacy SSE instructions: In 64-bit mode, Use of the REX.W prefix promotes the instruction to 64-bit operation. See

the summary chart at the beginning of this section for encoding data and limits.

VEX.W1 and EVEX.W1 versions: promotes the instruction to produce 64-bit data in 64-bit mode.

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CVTTSD2SI—Convert With Truncation Scalar Double Precision Floating-Point Value to Signed Integer

INSTRUCTION SET REFERENCE, A-L

CVTTSS2SI—Convert With Truncation Scalar Single Precision Floating-Point Value to Integer

Opcode/

Op /

64/32

CPUID

Description

Instruction

En

bit Mode

Feature

Support

Flag

F3 0F 2C /r

A

V/V

SSE

Convert one single precision floating-point value from

CVTTSS2SI r32, xmm1/m32

xmm1/m32 to one signed doubleword integer in r32

using truncation.

F3 REX.W 0F 2C /r

A

V/N.E.

SSE

Convert one single precision floating-point value from

CVTTSS2SI r64, xmm1/m32

xmm1/m32 to one signed quadword integer in r64

using truncation.

VEX.LIG.F3.0F.W0 2C /r ¹

A

V/V

AVX

Convert one single precision floating-point value from

VCVTTSS2SI r32, xmm1/m32

xmm1/m32 to one signed doubleword integer in r32

using truncation.

VEX.LIG.F3.0F.W1 2C /r ¹

A

V/N.E.²

AVX

Convert one single precision floating-point value from

VCVTTSS2SI r64, xmm1/m32

xmm1/m32 to one signed quadword integer in r64

using truncation.

EVEX.LLIG.F3.0F.W0 2C /r

B

V/V

AVX512F

Convert one single precision floating-point value from

VCVTTSS2SI r32, xmm1/m32{sae}

xmm1/m32 to one signed doubleword integer in r32

using truncation.

EVEX.LLIG.F3.0F.W1 2C /r

B

V/N.E.²

AVX512F

Convert one single precision floating-point value from

VCVTTSS2SI r64, xmm1/m32{sae}

xmm1/m32 to one signed quadword integer in r64

using truncation.

NOTES:

1. Software should ensure VCVTTSS2SI is encoded with VEX.L=0. Encoding VCVTTSS2SI with VEX.L=1 may encounter unpredictable

behavior across different processor generations.

2. For this specific instruction, VEX.W/EVEX.W in non-64 bit is ignored; the instructions behaves as if the W0 version is used.

Instruction Operand Encoding

Op/En

Tuple Type

Operand 1

Operand 2

Operand 3

Operand 4

A

N/A

ModRM:reg (w)

ModRM:r/m (r)

N/A

N/A

B

Tuple1 Fixed

ModRM:reg (w)

ModRM:r/m (r)

N/A

N/A

Description

Converts a single precision floating-point value in the source operand (the second operand) to a signed doubleword

integer (or signed quadword integer if operand size is 64 bits) in the destination operand (the first operand). The

source operand can be an XMM register or a 32-bit memory location. The destination operand is a general purpose

register. When the source operand is an XMM register, the single precision floating-point value is contained in the

low doubleword of the register.

When a conversion is inexact, a truncated (round toward zero) result is returned. If a converted result is larger than

the maximum signed doubleword integer, the floating-point invalid exception is raised. If this exception is masked,

the indefinite integer value (80000000H or 80000000_00000000H if operand size is 64 bits) is returned.

Legacy SSE instructions: In 64-bit mode, Use of the REX.W prefix promotes the instruction to 64-bit operation. See

the summary chart at the beginning of this section for encoding data and limits.

VEX.W1 and EVEX.W1 versions: promotes the instruction to produce 64-bit data in 64-bit mode.

Note: VEX.vvvv and EVEX.vvvv are reserved and must be 1111b, otherwise instructions will #UD.

Software should ensure VCVTTSS2SI is encoded with VEX.L=0. Encoding VCVTTSS2SI with VEX.L=1 may

encounter unpredictable behavior across different processor generations.

3-312

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CVTTSS2SI—Convert With Truncation Scalar Single Precision Floating-Point Value to Integer

INSTRUCTION SET REFERENCE, A-L

CWD/CDQ/CQO—Convert Word to Doubleword/Convert Doubleword to Quadword

Opcode

Instruction

Op/

64-Bit

Compat/

Description

En

Mode

Leg Mode

99

CWD

ZO

Valid

Valid

DX:AX := sign-extend of AX.

99

CDQ

ZO

Valid

Valid

EDX:EAX := sign-extend of EAX.

REX.W + 99

CQO

ZO

Valid

N.E.

RDX:RAX:= sign-extend of RAX.

Instruction Operand Encoding

Op/En

Operand 1

Operand 2

Operand 3

Operand 4

ZO

N/A

N/A

N/A

N/A

Description

Doubles the size of the operand in register AX, EAX, or RAX (depending on the operand size) by means of sign

extension and stores the result in registers DX:AX, EDX:EAX, or RDX:RAX, respectively. The CWD instruction

copies the sign (bit 15) of the value in the AX register into every bit position in the DX register. The CDQ instruction

copies the sign (bit 31) of the value in the EAX register into every bit position in the EDX register. The CQO instruc-

tion (available in 64-bit mode only) copies the sign (bit 63) of the value in the RAX register into every bit position

in the RDX register.

The CWD instruction can be used to produce a doubleword dividend from a word before word division. The CDQ

instruction can be used to produce a quadword dividend from a doubleword before doubleword division. The CQO

instruction can be used to produce a double quadword dividend from a quadword before a quadword division.

The CWD and CDQ mnemonics reference the same opcode. The CWD instruction is intended for use when the

operand-size attribute is 16 and the CDQ instruction for when the operand-size attribute is 32. Some assemblers

may force the operand size to 16 when CWD is used and to 32 when CDQ is used. Others may treat these

mnemonics as synonyms (CWD/CDQ) and use the current setting of the operand-size attribute to determine the

size of values to be converted, regardless of the mnemonic used.

In 64-bit mode, use of the REX.W prefix promotes operation to 64 bits. The CQO mnemonics reference the same

opcode as CWD/CDQ. See the summary chart at the beginning of this section for encoding data and limits.

Operation

IF OperandSize = 16 (* CWD instruction *)

THEN

DX := SignExtend(AX);

ELSE IF OperandSize = 32 (* CDQ instruction *)

EDX := SignExtend(EAX); FI;

ELSE IF 64-Bit Mode and OperandSize = 64 (* CQO instruction*)

RDX := SignExtend(RAX); FI;

FI;

Flags Affected

None

Exceptions (All Operating Modes)

#UD

If the LOCK prefix is used.

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CWD/CDQ/CQO—Convert Word to Doubleword/Convert Doubleword to Quadword

INSTRUCTION SET REFERENCE, A-L

DAA—Decimal Adjust AL After Addition

Opcode

Instruction

Op/

64-Bit

Compat/

Description

En

Mode

Leg Mode

27

DAA

ZO

Invalid

Valid

Decimal adjust AL after addition.

Instruction Operand Encoding

Op/En

Operand 1

Operand 2

Operand 3

Operand 4

ZO

N/A

N/A

N/A

N/A

Description

Adjusts the sum of two packed BCD values to create a packed BCD result. The AL register is the implied source and

destination operand. The DAA instruction is only useful when it follows an ADD instruction that adds (binary addi-

tion) two 2-digit, packed BCD values and stores a byte result in the AL register. The DAA instruction then adjusts

the contents of the AL register to contain the correct 2-digit, packed BCD result. If a decimal carry is detected, the

CF and AF flags are set accordingly.

This instruction executes as described above in compatibility mode and legacy mode. It is not valid in 64-bit mode.

Operation

IF 64-Bit Mode

THEN

#UD;

ELSE

old_AL := AL;

old_CF := CF;

CF := 0;

IF (((AL AND 0FH) > 9) or AF = 1)

THEN

AL := AL + 6;

CF := old_CF or (Carry from AL := AL + 6);

AF := 1;

ELSE

AF := 0;

FI;

IF ((old_AL > 99H) or (old_CF = 1))

THEN

AL := AL + 60H;

CF := 1;

ELSE

CF := 0;

FI;

FI;

Example

ADD AL, BL Before: AL=79H BL=35H EFLAGS(OSZAPC)=XXXXXX

After: AL=AEH BL=35H EFLAGS(0SZAPC)=110000

DAA

Before: AL=AEH BL=35H EFLAGS(OSZAPC)=110000

After: AL=14H BL=35H EFLAGS(0SZAPC)=X00111

DAA

Before: AL=2EH BL=35H EFLAGS(OSZAPC)=110000

After: AL=34H BL=35H EFLAGS(0SZAPC)=X00101

DAA—Decimal Adjust AL After Addition

Vol. 2A

3-315

INSTRUCTION SET REFERENCE, A-L

DAS—Decimal Adjust AL After Subtraction

Opcode

Instruction

Op/

64-Bit

Compat/

Description

En

Mode

Leg Mode

2F

DAS

ZO

Invalid

Valid

Decimal adjust AL after subtraction.

Instruction Operand Encoding

Op/En

Operand 1

Operand 2

Operand 3

Operand 4

ZO

N/A

N/A

N/A

N/A

Description

Adjusts the result of the subtraction of two packed BCD values to create a packed BCD result. The AL register is the

implied source and destination operand. The DAS instruction is only useful when it follows a SUB instruction that

subtracts (binary subtraction) one 2-digit, packed BCD value from another and stores a byte result in the AL

register. The DAS instruction then adjusts the contents of the AL register to contain the correct 2-digit, packed BCD

result. If a decimal borrow is detected, the CF and AF flags are set accordingly.

This instruction executes as described above in compatibility mode and legacy mode. It is not valid in 64-bit mode.

Operation

IF 64-Bit Mode

THEN

#UD;

ELSE

old_AL := AL;

old_CF := CF;

CF := 0;

IF (((AL AND 0FH) > 9) or AF = 1)

THEN

AL := AL - 6;

CF := old_CF or (Borrow from AL := AL − 6);

AF := 1;

ELSE

AF := 0;

FI;

IF ((old_AL > 99H) or (old_CF = 1))

THEN

AL := AL − 60H;

CF := 1;

FI;

FI;

Example

SUB AL, BL Before: AL = 35H, BL = 47H, EFLAGS(OSZAPC) = XXXXXX

After: AL = EEH, BL = 47H, EFLAGS(0SZAPC) = 010111

DAA

Before: AL = EEH, BL = 47H, EFLAGS(OSZAPC) = 010111

After: AL = 88H, BL = 47H, EFLAGS(0SZAPC) = X10111

Flags Affected

The CF and AF flags are set if the adjustment of the value results in a decimal borrow in either digit of the result

(see the “Operation” section above). The SF, ZF, and PF flags are set according to the result. The OF flag is unde-

fined.

DAS—Decimal Adjust AL After Subtraction

Vol. 2A

3-317

INSTRUCTION SET REFERENCE, A-L

DEC—Decrement by 1

Opcode

Instruction

Op/

64-Bit

Compat/

Description

En

Mode

Leg Mode

FE /1

DEC r/m8

M

Valid

Valid

Decrement r/m8 by 1.

REX + FE /1

DEC r/m8^*

M

Valid

N.E.

Decrement r/m8 by 1.

FF /1

DEC r/m16

M

Valid

Valid

Decrement r/m16 by 1.

FF /1

DEC r/m32

M

Valid

Valid

Decrement r/m32 by 1.

REX.W + FF /1

DEC r/m64

M

Valid

N.E.

Decrement r/m64 by 1.

48+rw

DEC r16

O

N.E.

Valid

Decrement r16 by 1.

48+rd

DEC r32

O

N.E.

Valid

Decrement r32 by 1.

NOTES:

* In 64-bit mode, r/m8 can not be encoded to access the following byte registers if a REX prefix is used: AH, BH, CH, DH.

Instruction Operand Encoding

Op/En

Operand 1

Operand 2

Operand 3

Operand 4

M

ModRM:r/m (r, w)

N/A

N/A

N/A

O

opcode + rd (r, w)

N/A

N/A

N/A

Description

Subtracts 1 from the destination operand, while preserving the state of the CF flag. The destination operand can be

a register or a memory location. This instruction allows a loop counter to be updated without disturbing the CF flag.

(To perform a decrement operation that updates the CF flag, use a SUB instruction with an immediate operand of

1.)

This instruction can be used with a LOCK prefix to allow the instruction to be executed atomically.

In 64-bit mode, DEC r16 and DEC r32 are not encodable (because opcodes 48H through 4FH are REX prefixes).

Otherwise, the instruction’s 64-bit mode default operation size is 32 bits. Use of the REX.R prefix permits access to

additional registers (R8-R15). Use of the REX.W prefix promotes operation to 64 bits.

See the summary chart at the beginning of this section for encoding data and limits.

Operation

DEST := DEST - 1;

Flags Affected

The CF flag is not affected. The OF, SF, ZF, AF, and PF flags are set according to the result.

Protected Mode Exceptions

#GP(0)

If the destination operand is located in a non-writable segment.

If a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit.

If the DS, ES, FS, or GS register contains a NULL segment selector.

#SS(0)

If a memory operand effective address is outside the SS segment limit.

#PF(fault-code)

If a page fault occurs.

#AC(0)

If alignment checking is enabled and an unaligned memory reference is made while the

current privilege level is 3.

#UD

If the LOCK prefix is used but the destination is not a memory operand.

DEC—Decrement by 1

Vol. 2A

3-319

INSTRUCTION SET REFERENCE, A-L

DIV—Unsigned Divide

Opcode

Instruction

Op/

64-Bit

Compat/

Description

En

Mode

Leg Mode

F6 /6

DIV r/m8

M

Valid

Valid

Unsigned divide AX by r/m8, with result

stored in AL := Quotient, AH := Remainder.

REX + F6 /6

DIV r/m8¹

M

Valid

N.E.

Unsigned divide AX by r/m8, with result

stored in AL := Quotient, AH := Remainder.

F7 /6

DIV r/m16

M

Valid

Valid

Unsigned divide DX:AX by r/m16, with result

stored in AX := Quotient, DX := Remainder.

F7 /6

DIV r/m32

M

Valid

Valid

Unsigned divide EDX:EAX by r/m32, with

result stored in EAX := Quotient, EDX :=

Remainder.

REX.W + F7 /6

DIV r/m64

M

Valid

N.E.

Unsigned divide RDX:RAX by r/m64, with

result stored in RAX := Quotient, RDX :=

Remainder.

NOTES:

1. In 64-bit mode, r/m8 can not be encoded to access the following byte registers if a REX prefix is used: AH, BH, CH, DH.

Instruction Operand Encoding

Op/En

Operand 1

Operand 2

Operand 3

Operand 4

M

ModRM:r/m (w)

N/A

N/A

N/A

Description

Divides unsigned the value in the AX, DX:AX, EDX:EAX, or RDX:RAX registers (dividend) by the source operand

(divisor) and stores the result in the AX (AH:AL), DX:AX, EDX:EAX, or RDX:RAX registers. The source operand can

be a general-purpose register or a memory location. The action of this instruction depends on the operand size

(dividend/divisor). Division using 64-bit operand is available only in 64-bit mode.

Non-integral results are truncated (chopped) towards 0. The remainder is always less than the divisor in magni-

tude. Overflow is indicated with the #DE (divide error) exception rather than with the CF flag.

In 64-bit mode, the instruction’s default operation size is 32 bits. Use of the REX.R prefix permits access to addi-

tional registers (R8-R15). Use of the REX.W prefix promotes operation to 64 bits. In 64-bit mode when REX.W is

applied, the instruction divides the unsigned value in RDX:RAX by the source operand and stores the quotient in

RAX, the remainder in RDX.

See the summary chart at the beginning of this section for encoding data and limits. See Table 3-15.

Table 3-15. DIV Action

Maximum

Operand Size

Dividend

Divisor

Quotient

Remainder

Quotient

Word/byte

AX

r/m8

AL

AH

255

Doubleword/word

DX:AX

r/m16

AX

DX

65,535

Quadword/doubleword

EDX:EAX

r/m32

EAX

EDX

2³² − 1

Doublequadword/

RDX:RAX

r/m64

RAX

RDX

2⁶⁴ − 1

quadword

DIV—Unsigned Divide

Vol. 2A

3-321

INSTRUCTION SET REFERENCE, A-L

DIVPD—Divide Packed Double Precision Floating-Point Values

Opcode/

Op /

64/32

CPUID

Description

Instruction

En

bit Mode

Feature

Support

Flag

66 0F 5E /r

A

V/V

SSE2

Divide packed double precision floating-point values

DIVPD xmm1, xmm2/m128

in xmm1 by packed double precision floating-point

values in xmm2/mem.

VEX.128.66.0F.WIG 5E /r

B

V/V

AVX

Divide packed double precision floating-point values

VDIVPD xmm1, xmm2, xmm3/m128

in xmm2 by packed double precision floating-point

values in xmm3/mem.

VEX.256.66.0F.WIG 5E /r

B

V/V

AVX

Divide packed double precision floating-point values

VDIVPD ymm1, ymm2, ymm3/m256

in ymm2 by packed double precision floating-point

values in ymm3/mem.

EVEX.128.66.0F.W1 5E /r

C

V/V

AVX512VL

Divide packed double precision floating-point values

VDIVPD xmm1 {k1}{z}, xmm2,

AVX512F

in xmm2 by packed double precision floating-point

xmm3/m128/m64bcst

values in xmm3/m128/m64bcst and write results to

xmm1 subject to writemask k1.

EVEX.256.66.0F.W1 5E /r

C

V/V

AVX512VL

Divide packed double precision floating-point values

VDIVPD ymm1 {k1}{z}, ymm2,

AVX512F

in ymm2 by packed double precision floating-point

ymm3/m256/m64bcst

values in ymm3/m256/m64bcst and write results to

ymm1 subject to writemask k1.

EVEX.512.66.0F.W1 5E /r

C

V/V

AVX512F

Divide packed double precision floating-point values

VDIVPD zmm1 {k1}{z}, zmm2,

in zmm2 by packed double precision floating-point

zmm3/m512/m64bcst{er}

values in zmm3/m512/m64bcst and write results to

zmm1 subject to writemask k1.

Instruction Operand Encoding

Op/En

Tuple Type

Operand 1

Operand 2

Operand 3

Operand 4

A

N/A

ModRM:reg (r, w)

ModRM:r/m (r)

N/A

N/A

B

N/A

ModRM:reg (w)

VEX.vvvv (r)

ModRM:r/m (r)

N/A

C

Full

ModRM:reg (w)

EVEX.vvvv (r)

ModRM:r/m (r)

N/A

Description

Performs a SIMD divide of the double precision floating-point values in the first source operand by the floating-

point values in the second source operand (the third operand). Results are written to the destination operand (the

first operand).

EVEX encoded versions: The first source operand (the second operand) is a ZMM/YMM/XMM register. The second

source operand can be a ZMM/YMM/XMM register, a 512/256/128-bit memory location or a 512/256/128-bit vector

broadcasted from a 64-bit memory location. The destination operand is a ZMM/YMM/XMM register conditionally

updated with writemask k1.

VEX.256 encoded version: The first source operand (the second operand) is a YMM register. The second source

operand can be a YMM register or a 256-bit memory location. The destination operand is a YMM register. The upper

bits (MAXVL-1:256) of the corresponding destination are zeroed.

VEX.128 encoded version: The first source operand (the second operand) is a XMM register. The second source

operand can be a XMM register or a 128-bit memory location. The destination operand is a XMM register. The upper

bits (MAXVL-1:128) of the corresponding destination are zeroed.

128-bit Legacy SSE version: The second source operand (the second operand) can be an XMM register or an 128-

bit memory location. The destination is the same as the first source operand. The upper bits (MAXVL-1:128) of the

corresponding destination are unmodified.

3-324

Vol. 2A

DIVPD—Divide Packed Double Precision Floating-Point Values

INSTRUCTION SET REFERENCE, A-L

DIVPS—Divide Packed Single Precision Floating-Point Values

Opcode/

Op /

64/32

CPUID

Description

Instruction

En

bit Mode

Feature

Support

Flag

NP 0F 5E /r

A

V/V

SSE

Divide packed single precision floating-point values

DIVPS xmm1, xmm2/m128

in xmm1 by packed single precision floating-point

values in xmm2/mem.

VEX.128.0F.WIG 5E /r

B

V/V

AVX

Divide packed single precision floating-point values

VDIVPS xmm1, xmm2, xmm3/m128

in xmm2 by packed single precision floating-point

values in xmm3/mem.

VEX.256.0F.WIG 5E /r

B

V/V

AVX

Divide packed single precision floating-point values

VDIVPS ymm1, ymm2, ymm3/m256

in ymm2 by packed single precision floating-point

values in ymm3/mem.

EVEX.128.0F.W0 5E /r

C

V/V

AVX512VL

Divide packed single precision floating-point values

VDIVPS xmm1 {k1}{z}, xmm2,

AVX512F

in xmm2 by packed single precision floating-point

xmm3/m128/m32bcst

values in xmm3/m128/m32bcst and write results to

xmm1 subject to writemask k1.

EVEX.256.0F.W0 5E /r

C

V/V

AVX512VL

Divide packed single precision floating-point values

VDIVPS ymm1 {k1}{z}, ymm2,

AVX512F

in ymm2 by packed single precision floating-point

ymm3/m256/m32bcst

values in ymm3/m256/m32bcst and write results to

ymm1 subject to writemask k1.

EVEX.512.0F.W0 5E /r

C

V/V

AVX512F

Divide packed single precision floating-point values

VDIVPS zmm1 {k1}{z}, zmm2,

in zmm2 by packed single precision floating-point

zmm3/m512/m32bcst{er}

values in zmm3/m512/m32bcst and write results to

zmm1 subject to writemask k1.

Instruction Operand Encoding

Op/En

Tuple Type

Operand 1

Operand 2

Operand 3

Operand 4

A

N/A

ModRM:reg (r, w)

ModRM:r/m (r)

N/A

N/A

B

N/A

ModRM:reg (w)

VEX.vvvv (r)

ModRM:r/m (r)

N/A

C

Full

ModRM:reg (w)

EVEX.vvvv (r)

ModRM:r/m (r)

N/A

Description

Performs a SIMD divide of the four, eight or sixteen packed single precision floating-point values in the first source

operand (the second operand) by the four, eight or sixteen packed single precision floating-point values in the

second source operand (the third operand). Results are written to the destination operand (the first operand).

EVEX encoded versions: The first source operand (the second operand) is a ZMM/YMM/XMM register. The second

source operand can be a ZMM/YMM/XMM register, a 512/256/128-bit memory location or a 512/256/128-bit vector

broadcasted from a 32-bit memory location. The destination operand is a ZMM/YMM/XMM register conditionally

updated with writemask k1.

VEX.256 encoded version: The first source operand is a YMM register. The second source operand can be a YMM

register or a 256-bit memory location. The destination operand is a YMM register.

VEX.128 encoded version: The first source operand is a XMM register. The second source operand can be a XMM

register or a 128-bit memory location. The destination operand is a XMM register. The upper bits (MAXVL-1:128) of

the corresponding ZMM register destination are zeroed.

128-bit Legacy SSE version: The second source can be an XMM register or an 128-bit memory location. The desti-

nation is not distinct from the first source XMM register and the upper bits (MAXVL-1:128) of the corresponding

ZMM register destination are unmodified.

DIVPS—Divide Packed Single Precision Floating-Point Values

Vol. 2A

3-327

INSTRUCTION SET REFERENCE, A-L

DIVSD—Divide Scalar Double Precision Floating-Point Value

Opcode/

Op /

64/32

CPUID

Description

Instruction

En

bit Mode

Feature

Support

Flag

F2 0F 5E /r

A

V/V

SSE2

Divide low double precision floating-point value in

DIVSD xmm1, xmm2/m64

xmm1 by low double precision floating-point value in

xmm2/m64.

VEX.LIG.F2.0F.WIG 5E /r

B

V/V

AVX

Divide low double precision floating-point value in

VDIVSD xmm1, xmm2, xmm3/m64

xmm2 by low double precision floating-point value in

xmm3/m64.

EVEX.LLIG.F2.0F.W1 5E /r

C

V/V

AVX512F

Divide low double precision floating-point value in

VDIVSD xmm1 {k1}{z}, xmm2,

xmm2 by low double precision floating-point value in

xmm3/m64{er}

xmm3/m64.

Instruction Operand Encoding

Op/En

Tuple Type

Operand 1

Operand 2

Operand 3

Operand 4

A

N/A

ModRM:reg (r, w)

ModRM:r/m (r)

N/A

N/A

B

N/A

ModRM:reg (w)

VEX.vvvv (r)

ModRM:r/m (r)

N/A

C

Tuple1 Scalar

ModRM:reg (w)

EVEX.vvvv (r)

ModRM:r/m (r)

N/A

Description

Divides the low double precision floating-point value in the first source operand by the low double precision

floating-point value in the second source operand, and stores the double precision floating-point result in the desti-

nation operand. The second source operand can be an XMM register or a 64-bit memory location. The first source

and destination are XMM registers.

128-bit Legacy SSE version: The first source operand and the destination operand are the same. Bits (MAXVL-

1:64) of the corresponding ZMM destination register remain unchanged.

VEX.128 encoded version: The first source operand is an xmm register encoded by VEX.vvvv. The quadword at bits

127:64 of the destination operand is copied from the corresponding quadword of the first source operand. Bits

(MAXVL-1:128) of the destination register are zeroed.

EVEX.128 encoded version: The first source operand is an xmm register encoded by EVEX.vvvv. The quadword

element of the destination operand at bits 127:64 are copied from the first source operand. Bits (MAXVL-1:128) of

the destination register are zeroed.

EVEX version: The low quadword element of the destination is updated according to the writemask.

Software should ensure VDIVSD is encoded with VEX.L=0. Encoding VDIVSD with VEX.L=1 may encounter unpre-

dictable behavior across different processor generations.

3-330

Vol. 2A

DIVSD—Divide Scalar Double Precision Floating-Point Value

INSTRUCTION SET REFERENCE, A-L

DIVSS—Divide Scalar Single Precision Floating-Point Values

Opcode/

Op /

64/32

CPUID

Description

Instruction

En

bit Mode

Feature

Support

Flag

F3 0F 5E /r

A

V/V

SSE

Divide low single precision floating-point value in

DIVSS xmm1, xmm2/m32

xmm1 by low single precision floating-point value in

xmm2/m32.

VEX.LIG.F3.0F.WIG 5E /r

B

V/V

AVX

Divide low single precision floating-point value in

VDIVSS xmm1, xmm2, xmm3/m32

xmm2 by low single precision floating-point value in

xmm3/m32.

EVEX.LLIG.F3.0F.W0 5E /r

C

V/V

AVX512F

Divide low single precision floating-point value in

VDIVSS xmm1 {k1}{z}, xmm2,

xmm2 by low single precision floating-point value in

xmm3/m32{er}

xmm3/m32.

Instruction Operand Encoding

Op/En

Tuple Type

Operand 1

Operand 2

Operand 3

Operand 4

A

N/A

ModRM:reg (r, w)

ModRM:r/m (r)

N/A

N/A

B

N/A

ModRM:reg (w)

VEX.vvvv (r)

ModRM:r/m (r)

N/A

C

Tuple1 Scalar

ModRM:reg (w)

EVEX.vvvv (r)

ModRM:r/m (r)

N/A

Description

Divides the low single precision floating-point value in the first source operand by the low single precision floating-

point value in the second source operand, and stores the single precision floating-point result in the destination

operand. The second source operand can be an XMM register or a 32-bit memory location.

128-bit Legacy SSE version: The first source operand and the destination operand are the same. Bits (MAXVL-

1:32) of the corresponding YMM destination register remain unchanged.

VEX.128 encoded version: The first source operand is an xmm register encoded by VEX.vvvv. The three high-order

doublewords of the destination operand are copied from the first source operand. Bits (MAXVL-1:128) of the desti-

nation register are zeroed.

EVEX.128 encoded version: The first source operand is an xmm register encoded by EVEX.vvvv. The doubleword

elements of the destination operand at bits 127:32 are copied from the first source operand. Bits (MAXVL-1:128)

of the destination register are zeroed.

EVEX version: The low doubleword element of the destination is updated according to the writemask.

Software should ensure VDIVSS is encoded with VEX.L=0. Encoding VDIVSS with VEX.L=1 may encounter unpre-

dictable behavior across different processor generations.

3-332

Vol. 2A

DIVSS—Divide Scalar Single Precision Floating-Point Values

INSTRUCTION SET REFERENCE, A-L

DPPD—Dot Product of Packed Double Precision Floating-Point Values

Opcode/

Op/

64/32-bit

CPUID

Description

Instruction

En

Mode

Feature

Flag

66 0F 3A 41 /r ib

RMI

V/V

SSE4_1

Selectively multiply packed double precision

floating-point values from xmm1 with packed

DPPD xmm1, xmm2/m128, imm8

double precision floating-point values from

xmm2, add and selectively store the packed

double precision floating-point values to

xmm1.

VEX.128.66.0F3A.WIG 41 /r ib

RVMI

V/V

AVX

Selectively multiply packed double precision

floating-point values from xmm2 with packed

VDPPD xmm1,xmm2, xmm3/m128, imm8

double precision floating-point values from

xmm3, add and selectively store the packed

double precision floating-point values to

xmm1.

Instruction Operand Encoding

Op/En

Operand 1

Operand 2

Operand 3

Operand 4

RMI

ModRM:reg (r, w)

ModRM:r/m (r)

imm8

N/A

RVMI

ModRM:reg (w)

VEX.vvvv (r)

ModRM:r/m (r)

imm8

Description

Conditionally multiplies the packed double precision floating-point values in the destination operand (first operand)

with the packed double precision floating-point values in the source (second operand) depending on a mask

extracted from bits [5:4] of the immediate operand (third operand). If a condition mask bit is zero, the corre-

sponding multiplication is replaced by a value of 0.0 in the manner described by Section 12.8.4 of Intel® 64 and

IA-32 Architectures Software Developer’s Manual, Volume 1.

The two resulting double precision values are summed into an intermediate result. The intermediate result is condi-

tionally broadcasted to the destination using a broadcast mask specified by bits [1:0] of the immediate byte.

If a broadcast mask bit is “1”, the intermediate result is copied to the corresponding qword element in the destina-

tion operand. If a broadcast mask bit is zero, the corresponding element in the destination is set to zero.

DPPD follows the NaN forwarding rules stated in the Software Developer’s Manual, vol. 1, table 4.7. These rules do

not cover horizontal prioritization of NaNs. Horizontal propagation of NaNs to the destination and the positioning of

those NaNs in the destination is implementation dependent. NaNs on the input sources or computationally gener-

ated NaNs will have at least one NaN propagated to the destination.

128-bit Legacy SSE version: The second source can be an XMM register or an 128-bit memory location. The desti-

nation is not distinct from the first source XMM register and the upper bits (MAXVL-1:128) of the corresponding

YMM register destination are unmodified.

VEX.128 encoded version: the first source operand is an XMM register or 128-bit memory location. The destination

operand is an XMM register. The upper bits (MAXVL-1:128) of the corresponding YMM register destination are

zeroed.

If VDPPD is encoded with VEX.L= 1, an attempt to execute the instruction encoded with VEX.L= 1 will cause an

#UD exception.

3-334

Vol. 2A

DPPD—Dot Product of Packed Double Precision Floating-Point Values

INSTRUCTION SET REFERENCE, A-L

DPPS—Dot Product of Packed Single Precision Floating-Point Values

Opcode/

Op/

64/32-bit

CPUID

Description

Instruction

En

Mode

Feature

Flag

66 0F 3A 40 /r ib

RMI

V/V

SSE4_1

Selectively multiply packed single precision

floating-point values from xmm1 with packed

DPPS xmm1, xmm2/m128, imm8

single precision floating-point values from

xmm2, add and selectively store the packed

single precision floating-point values or zero

values to xmm1.

VEX.128.66.0F3A.WIG 40 /r ib

RVMI

V/V

AVX

Multiply packed single precision floating-point

values from xmm1 with packed single

VDPPS xmm1,xmm2, xmm3/m128, imm8

precision floating-point values from

xmm2/mem selectively add and store to

xmm1.

VEX.256.66.0F3A.WIG 40 /r ib

RVMI

V/V

AVX

Multiply packed single precision floating-point

values from ymm2 with packed single

VDPPS ymm1, ymm2, ymm3/m256, imm8

precision floating-point values from

ymm3/mem, selectively add pairs of elements

and store to ymm1.

Instruction Operand Encoding

Op/En

Operand 1

Operand 2

Operand 3

Operand 4

RMI

ModRM:reg (r, w)

ModRM:r/m (r)

imm8

N/A

RVMI

ModRM:reg (w)

VEX.vvvv (r)

ModRM:r/m (r)

imm8

Description

Conditionally multiplies the packed single precision floating-point values in the destination operand (first operand)

with the packed single precision floats in the source (second operand) depending on a mask extracted from the

high 4 bits of the immediate byte (third operand). If a condition mask bit in imm8[7:4] is zero, the corresponding

multiplication is replaced by a value of 0.0 in the manner described by Section 12.8.4 of Intel® 64 and IA-32 Archi-

tectures Software Developer’s Manual, Volume 1.

The four resulting single precision values are summed into an intermediate result. The intermediate result is condi-

tionally broadcasted to the destination using a broadcast mask specified by bits [3:0] of the immediate byte.

If a broadcast mask bit is “1”, the intermediate result is copied to the corresponding dword element in the destina-

tion operand. If a broadcast mask bit is zero, the corresponding element in the destination is set to zero.

DPPS follows the NaN forwarding rules stated in the Software Developer’s Manual, vol. 1, table 4.7. These rules do

not cover horizontal prioritization of NaNs. Horizontal propagation of NaNs to the destination and the positioning of

those NaNs in the destination is implementation dependent. NaNs on the input sources or computationally gener-

ated NaNs will have at least one NaN propagated to the destination.

128-bit Legacy SSE version: The second source can be an XMM register or an 128-bit memory location. The desti-

nation is not distinct from the first source XMM register and the upper bits (MAXVL-1:128) of the corresponding

YMM register destination are unmodified.

VEX.128 encoded version: the first source operand is an XMM register or 128-bit memory location. The destination

operand is an XMM register. The upper bits (MAXVL-1:128) of the corresponding YMM register destination are

zeroed.

VEX.256 encoded version: The first source operand is a YMM register. The second source operand can be a YMM

register or a 256-bit memory location. The destination operand is a YMM register.

3-336

Vol. 2A

DPPS—Dot Product of Packed Single Precision Floating-Point Values

INSTRUCTION SET REFERENCE, A-L

EMMS—Empty MMX Technology State

Opcode

Instruction

Op/

64-Bit

Compat/

Description

En

Mode

Leg Mode

NP 0F 77

EMMS

ZO

Valid

Valid

Set the x87 FPU tag word to empty.

Instruction Operand Encoding

Op/En

Operand 1

Operand 2

Operand 3

Operand 4

ZO

N/A

N/A

N/A

N/A

Description

Sets the values of all the tags in the x87 FPU tag word to empty (all 1s). This operation marks the x87 FPU data

registers (which are aliased to the MMX technology registers) as available for use by x87 FPU floating-point instruc-

tions. (See Figure 8-7 in the Intel® 64 and IA-32 Architectures Software Developer’s Manual, Volume 1, for the

format of the x87 FPU tag word.) All other MMX instructions (other than the EMMS instruction) set all the tags in

x87 FPU tag word to valid (all 0s).

The EMMS instruction must be used to clear the MMX technology state at the end of all MMX technology procedures

or subroutines and before calling other procedures or subroutines that may execute x87 floating-point instructions.

If a floating-point instruction loads one of the registers in the x87 FPU data register stack before the x87 FPU tag

word has been reset by the EMMS instruction, an x87 floating-point register stack overflow can occur that will

result in an x87 floating-point exception or incorrect result.

EMMS operation is the same in non-64-bit modes and 64-bit mode.

Operation

x87FPUTagWord := FFFFH;

Intel C/C++ Compiler Intrinsic Equivalent

void _mm_empty()

Flags Affected

None

Protected Mode Exceptions

#UD

If CR0.EM[bit 2] = 1.

#NM

If CR0.TS[bit 3] = 1.

#MF

If there is a pending FPU exception.

#UD

If the LOCK prefix is used.

Real-Address Mode Exceptions

Same exceptions as in protected mode.

Virtual-8086 Mode Exceptions

Same exceptions as in protected mode.

Compatibility Mode Exceptions

Same exceptions as in protected mode.

64-Bit Mode Exceptions

Same exceptions as in protected mode.

EMMS—Empty MMX Technology State

Vol. 2A

3-339

INSTRUCTION SET REFERENCE, A-L

ENCODEKEY128—Encode 128-Bit Key With Key Locker

Opcode/

Op/

64/32-bit

CPUID

Description

Instruction

En

Mode

Feature

Flag

F3 0F 38 FA 11:rrr:bbb

A

V/V

AESKLE

Wrap a 128-bit AES key from XMM0 into a key handle

ENCODEKEY128 r32, r32, <XMM0-2>,

and output handle in XMM0—2.

<XMM4-6>

Instruction Operand Encoding

Op/En

Tuple

Operand 1

Operand 2

Operand 3

Operands 4—5

Operands 6—7

A

N/A

ModRM:reg (w)

ModRM:r/m (r)

Implicit XMM0 (r, w)

Implicit XMM1—2 (w)

Implicit XMM4—6 (w)

Description

The ENCODEKEY128¹ instruction wraps a 128-bit AES key from the implicit operand XMM0 into a key handle that

is then stored in the implicit destination operands XMM0-2.

The explicit source operand specifies handle restrictions, if any.

The explicit destination operand is populated with information on the source of the key and its attributes. XMM4

through XMM6 are reserved for future usages and software should not rely upon them being zeroed.

Operation

ENCODEKEY128

#GP (0) if a reserved bit² in SRC[31:0] is set

InputKey[127:0] := XMM0;

KeyMetadata[2:0] = SRC[2:0];

KeyMetadata[23:3] = 0;

// Reserved for future usage

KeyMetadata[27:24] = 0;

// KeyType is AES-128 (value of 0)

KeyMetadata[127:28] = 0;

// Reserved for future usage

// KeyMetadata is the AAD input and InputKey is the Plaintext input for WrapKey128

Handle[383:0] := WrapKey128(InputKey[127:0], KeyMetadata[127:0], IWKey.Integrity Key[127:0], IWKey.Encryption Key[255:0]);

DEST[0] := IWKey.NoBackup;

DEST[4:1] := IWKey.KeySource[3:0];

DEST[31:5] = 0;

XMM0 := Handle[127:0];

// AAD

XMM1 := Handle[255:128]; // Integrity Tag

XMM2 := Handle[383:256]; // CipherText

XMM4 := 0;

// Reserved for future usage

XMM5 := 0;

// Reserved for future usage

XMM6 := 0;

// Reserved for future usage

RFLAGS.OF, SF, ZF, AF, PF, CF := 0;

Flags Affected

All arithmetic flags (OF, SF, ZF, AF, PF, CF) are cleared to 0. Although they are cleared for the currently defined oper-

ations, future extensions may report information in the flags.

1. Further details on Key Locker and usage of this instruction can be found here:

https://software.intel.com/content/www/us/en/develop/download/intel-key-locker-specification.html.

2. SRC[31:3] are currently reserved for future usages. SRC[2], which indicates a no-decrypt restriction, is reserved if CPUID.19H:EAX[2]

is 0. SRC[1], which indicates a no-encrypt restriction, is reserved if CPUID.19H:EAX[1] is 0. SRC[0], which indicates a CPL0-only

restriction, is reserved if CPUID.19H:EAX[0] is 0.

3-340

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ENCODEKEY128—Encode 128-Bit Key With Key Locker

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