Intel 64 and IA-32 Architectures. Software Developer’s Manual (Collection, 2023)

INSTRUCTION SET REFERENCE, A-L

31 30 29 28 27 26 25 24 23 22 21 20 19 18

17 16

14 13 12

11 10

ECX

RDRAND

F16C

AVX

OSXSAVE

XSAVE

AES

TSC-Deadline

POPCNT

MOVBE

x2APIC

SSE4_2 — SSE4.2

SSE4_1 — SSE4.1

DCA — Direct Cache Access

PCID — Process-context Identifiers

PDCM — Perf/Debug Capability MSR

xTPR Update Control

CMPXCHG16B

FMA — Fused Multiply Add

SDBG

CNXT-ID — L1 Context ID

SSSE3 — SSSE3 Extensions

TM2 — Thermal Monitor 2

EIST — Enhanced Intel SpeedStep® Technology

SMX — Safer Mode Extensions

VMX — Virtual Machine Extensions

DS-CPL — CPL Qualified Debug Store

MONITOR — MONITOR/MWAIT

DTES64 — 64-bit DS Area

PCLMULQDQ — Carryless Multiplication

SSE3 — SSE3 Extensions

OM16524b

Reserved

Figure 3-7. Feature Information Returned in the ECX Register

Table 3-10. Feature Information Returned in the ECX Register

Bit #

Mnemonic

Description

SSE3

Streaming SIMD Extensions 3 (SSE3). A value of 1 indicates the processor supports this

technology.

PCLMULQDQ

PCLMULQDQ. A value of 1 indicates the processor supports the PCLMULQDQ instruction.

DTES64

64-bit DS Area. A value of 1 indicates the processor supports DS area using 64-bit layout.

MONITOR

MONITOR/MWAIT. A value of 1 indicates the processor supports this feature.

DS-CPL

CPL Qualified Debug Store. A value of 1 indicates the processor supports the extensions to the

Debug Store feature to allow for branch message storage qualified by CPL.

VMX

Virtual Machine Extensions. A value of 1 indicates that the processor supports this technology.

SMX

Safer Mode Extensions. A value of 1 indicates that the processor supports this technology. See

Chapter 7, “Safer Mode Extensions Reference”.

EIST

Enhanced Intel SpeedStep® technology. A value of 1 indicates that the processor supports this

technology.

TM2

Thermal Monitor 2. A value of 1 indicates whether the processor supports this technology.

SSSE3

A value of 1 indicates the presence of the Supplemental Streaming SIMD Extensions 3 (SSSE3). A

value of 0 indicates the instruction extensions are not present in the processor.

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Table 3-10. Feature Information Returned in the ECX Register (Contd.)

Bit #

Mnemonic

Description

CNXT-ID

L1 Context ID. A value of 1 indicates the L1 data cache mode can be set to either adaptive mode

or shared mode. A value of 0 indicates this feature is not supported. See definition of the

IA32_MISC_ENABLE MSR Bit 24 (L1 Data Cache Context Mode) for details.

SDBG

A value of 1 indicates the processor supports IA32_DEBUG_INTERFACE MSR for silicon debug.

FMA

A value of 1 indicates the processor supports FMA extensions using YMM state.

CMPXCHG16B

CMPXCHG16B Available. A value of 1 indicates that the feature is available. See the

“CMPXCHG8B/CMPXCHG16B—Compare and Exchange Bytes” section in this chapter for a

description.

xTPR Update

xTPR Update Control. A value of 1 indicates that the processor supports changing

Control

IA32_MISC_ENABLE[bit 23].

PDCM

Perfmon and Debug Capability: A value of 1 indicates the processor supports the performance

and debug feature indication MSR IA32_PERF_CAPABILITIES.

Reserved

PCID

Process-context identifiers. A value of 1 indicates that the processor supports PCIDs and that

software may set CR4.PCIDE to 1.

DCA

A value of 1 indicates the processor supports the ability to prefetch data from a memory mapped

device.

SSE4_1

A value of 1 indicates that the processor supports SSE4.1.

SSE4_2

A value of 1 indicates that the processor supports SSE4.2.

x2APIC

A value of 1 indicates that the processor supports x2APIC feature.

MOVBE

A value of 1 indicates that the processor supports MOVBE instruction.

POPCNT

A value of 1 indicates that the processor supports the POPCNT instruction.

TSC-Deadline

A value of 1 indicates that the processor’s local APIC timer supports one-shot operation using a

TSC deadline value.

AESNI

A value of 1 indicates that the processor supports the AESNI instruction extensions.

XSAVE

A value of 1 indicates that the processor supports the XSAVE/XRSTOR processor extended states

feature, the XSETBV/XGETBV instructions, and XCR0.

OSXSAVE

A value of 1 indicates that the OS has set CR4.OSXSAVE[bit 18] to enable XSETBV/XGETBV

instructions to access XCR0 and to support processor extended state management using

XSAVE/XRSTOR.

AVX

A value of 1 indicates the processor supports the AVX instruction extensions.

F16C

A value of 1 indicates that processor supports 16-bit floating-point conversion instructions.

RDRAND

A value of 1 indicates that processor supports RDRAND instruction.

Not Used

Always returns 0.

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INSTRUCTION SET REFERENCE, A-L

3130292827262524 23 22 21 20 19 18 17 16 15 14 13 12 1110

EDX

PBE-Pend. Brk. EN.

TM-Therm. Monitor

HTT-Multi-threading

SS-Self Snoop

SSE2-SSE2 Extensions

SSE-SSE Extensions

FXSR-FXSAVE/FXRSTOR

MMX-MMX Technology

ACPI-Thermal Monitor and Clock Ctrl

DS-Debug Store

CLFSH-CLFLUSH instruction

PSN-Processor Serial Number

PSE-36 - Page Size Extension

PAT-Page Attribute Table

CMOV-Conditional Move/Compare Instruction

MCA-Machine Check Architecture

PGE-PTE Global Bit

MTRR-Memory Type Range Registers

SEP-SYSENTER and SYSEXIT

APIC-APIC on Chip

CX8-CMPXCHG8B Inst.

MCE-Machine Check Exception

PAE-Physical Address Extensions

MSR-RDMSR and WRMSR Support

TSC-Time Stamp Counter

PSE-Page Size Extensions

DE-Debugging Extensions

VME-Virtual-8086 Mode Enhancement

FPU-x87 FPU on Chip

Reserved

OM16523

Figure 3-8. Feature Information Returned in the EDX Register

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Table 3-11. More on Feature Information Returned in the EDX Register

Bit #

Mnemonic

Description

FPU

Floating-Point Unit On-Chip. The processor contains an x87 FPU.

VME

Virtual 8086 Mode Enhancements. Virtual 8086 mode enhancements, including CR4.VME for controlling the

feature, CR4.PVI for protected mode virtual interrupts, software interrupt indirection, expansion of the TSS

with the software indirection bitmap, and EFLAGS.VIF and EFLAGS.VIP flags.

Debugging Extensions. Support for I/O breakpoints, including CR4.DE for controlling the feature, and optional

trapping of accesses to DR4 and DR5.

PSE

Page Size Extension. Large pages of size 4 MByte are supported, including CR4.PSE for controlling the

feature, the defined dirty bit in PDE (Page Directory Entries), optional reserved bit trapping in CR3, PDEs, and

PTEs.

TSC

Time Stamp Counter. The RDTSC instruction is supported, including CR4.TSD for controlling privilege.

MSR

Model Specific Registers RDMSR and WRMSR Instructions. The RDMSR and WRMSR instructions are

supported. Some of the MSRs are implementation dependent.

PAE

Physical Address Extension. Physical addresses greater than 32 bits are supported: extended page table

entry formats, an extra level in the page translation tables is defined, 2-MByte pages are supported instead of

4 Mbyte pages if PAE bit is 1.

MCE

Machine Check Exception. Exception 18 is defined for Machine Checks, including CR4.MCE for controlling the

feature. This feature does not define the model-specific implementations of machine-check error logging,

reporting, and processor shutdowns. Machine Check exception handlers may have to depend on processor

version to do model specific processing of the exception, or test for the presence of the Machine Check feature.

CX8

CMPXCHG8B Instruction. The compare-and-exchange 8 bytes (64 bits) instruction is supported (implicitly

locked and atomic).

APIC

APIC On-Chip. The processor contains an Advanced Programmable Interrupt Controller (APIC), responding to

memory mapped commands in the physical address range FFFE0000H to FFFE0FFFH (by default - some

processors permit the APIC to be relocated).

Reserved

SEP

SYSENTER and SYSEXIT Instructions. The SYSENTER and SYSEXIT and associated MSRs are supported.

MTRR

Memory Type Range Registers. MTRRs are supported. The MTRRcap MSR contains feature bits that describe

what memory types are supported, how many variable MTRRs are supported, and whether fixed MTRRs are

supported.

PGE

Page Global Bit. The global bit is supported in paging-structure entries that map a page, indicating TLB entries

that are common to different processes and need not be flushed. The CR4.PGE bit controls this feature.

MCA

Machine Check Architecture. A value of 1 indicates the Machine Check Architecture of reporting machine

errors is supported. The MCG_CAP MSR contains feature bits describing how many banks of error reporting

MSRs are supported.

CMOV

Conditional Move Instructions. The conditional move instruction CMOV is supported. In addition, if x87 FPU is

present as indicated by the CPUID.FPU feature bit, then the FCOMI and FCMOV instructions are supported

PAT

Page Attribute Table. Page Attribute Table is supported. This feature augments the Memory Type Range

Registers (MTRRs), allowing an operating system to specify attributes of memory accessed through a linear

address on a 4KB granularity.

PSE-36

36-Bit Page Size Extension. 4-MByte pages addressing physical memory beyond 4 GBytes are supported with

32-bit paging. This feature indicates that upper bits of the physical address of a 4-MByte page are encoded in

bits 20:13 of the page-directory entry. Such physical addresses are limited by MAXPHYADDR and may be up to

40 bits in size.

PSN

Processor Serial Number. The processor supports the 96-bit processor identification number feature and the

feature is enabled.

CLFSH

CLFLUSH Instruction. CLFLUSH Instruction is supported.

Reserved

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Table 3-11. More on Feature Information Returned in the EDX Register (Contd.)

Bit #

Mnemonic

Description

Debug Store. The processor supports the ability to write debug information into a memory resident buffer.

This feature is used by the branch trace store (BTS) and processor event-based sampling (PEBS) facilities (see

Chapter 24, “Introduction to Virtual-Machine Extensions,” in the Intel® 64 and IA-32 Architectures Software

Developer’s Manual, Volume 3C).

ACPI

Thermal Monitor and Software Controlled Clock Facilities. The processor implements internal MSRs that

allow processor temperature to be monitored and processor performance to be modulated in predefined duty

cycles under software control.

MMX

Intel MMX Technology. The processor supports the Intel MMX technology.

FXSR

FXSAVE and FXRSTOR Instructions. The FXSAVE and FXRSTOR instructions are supported for fast save and

restore of the floating-point context. Presence of this bit also indicates that CR4.OSFXSR is available for an

operating system to indicate that it supports the FXSAVE and FXRSTOR instructions.

SSE

SSE. The processor supports the SSE extensions.

SSE2

SSE2. The processor supports the SSE2 extensions.

Self Snoop. The processor supports the management of conflicting memory types by performing a snoop of its

own cache structure for transactions issued to the bus.

HTT

Max APIC IDs reserved field is Valid. A value of 0 for HTT indicates there is only a single logical processor in

the package and software should assume only a single APIC ID is reserved. A value of 1 for HTT indicates the

value in CPUID.1.EBX[23:16] (the Maximum number of addressable IDs for logical processors in this package) is

valid for the package.

Thermal Monitor. The processor implements the thermal monitor automatic thermal control circuitry (TCC).

Reserved

PBE

Pending Break Enable. The processor supports the use of the FERR#/PBE# pin when the processor is in the

stop-clock state (STPCLK# is asserted) to signal the processor that an interrupt is pending and that the

processor should return to normal operation to handle the interrupt.

INPUT EAX = 02H: TLB/Cache/Prefetch Information Returned in EAX, EBX, ECX, EDX

When CPUID executes with EAX set to 02H, the processor returns information about the processor’s internal TLBs,

cache, and prefetch hardware in the EAX, EBX, ECX, and EDX registers. The information is reported in encoded

form and fall into the following categories:

• The least-significant byte in register EAX (register AL) will always return 01H. Software should ignore this value

and not interpret it as an informational descriptor.

• The most significant bit (bit 31) of each register indicates whether the register contains valid information (set

to 0) or is reserved (set to 1).

• If a register contains valid information, the information is contained in 1 byte descriptors. There are four types

of encoding values for the byte descriptor, the encoding type is noted in the second column of Table 3-12. Table

3-12 lists the encoding of these descriptors. Note that the order of descriptors in the EAX, EBX, ECX, and EDX

registers is not defined; that is, specific bytes are not designated to contain descriptors for specific cache,

prefetch, or TLB types. The descriptors may appear in any order. Note also a processor may report a general

descriptor type (FFH) and not report any byte descriptor of “cache type” via CPUID leaf 2.

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Table 3-12. Encoding of CPUID Leaf 2 Descriptors

Value

Type

Description

00H

General

Null descriptor, this byte contains no information

01H

TLB

Instruction TLB: 4 KByte pages, 4-way set associative, 32 entries

02H

TLB

Instruction TLB: 4 MByte pages, fully associative, 2 entries

03H

TLB

Data TLB: 4 KByte pages, 4-way set associative, 64 entries

04H

TLB

Data TLB: 4 MByte pages, 4-way set associative, 8 entries

05H

TLB

Data TLB1: 4 MByte pages, 4-way set associative, 32 entries

06H

Cache

1st-level instruction cache: 8 KBytes, 4-way set associative, 32 byte line size

08H

Cache

1st-level instruction cache: 16 KBytes, 4-way set associative, 32 byte line size

09H

Cache

1st-level instruction cache: 32KBytes, 4-way set associative, 64 byte line size

0AH

Cache

1st-level data cache: 8 KBytes, 2-way set associative, 32 byte line size

0BH

TLB

Instruction TLB: 4 MByte pages, 4-way set associative, 4 entries

0CH

Cache

1st-level data cache: 16 KBytes, 4-way set associative, 32 byte line size

0DH

Cache

1st-level data cache: 16 KBytes, 4-way set associative, 64 byte line size

0EH

Cache

1st-level data cache: 24 KBytes, 6-way set associative, 64 byte line size

1DH

Cache

2nd-level cache: 128 KBytes, 2-way set associative, 64 byte line size

21H

Cache

2nd-level cache: 256 KBytes, 8-way set associative, 64 byte line size

22H

Cache

3rd-level cache: 512 KBytes, 4-way set associative, 64 byte line size, 2 lines per sector

23H

Cache

3rd-level cache: 1 MBytes, 8-way set associative, 64 byte line size, 2 lines per sector

24H

Cache

2nd-level cache: 1 MBytes, 16-way set associative, 64 byte line size

25H

Cache

3rd-level cache: 2 MBytes, 8-way set associative, 64 byte line size, 2 lines per sector

29H

Cache

3rd-level cache: 4 MBytes, 8-way set associative, 64 byte line size, 2 lines per sector

2CH

Cache

1st-level data cache: 32 KBytes, 8-way set associative, 64 byte line size

30H

Cache

1st-level instruction cache: 32 KBytes, 8-way set associative, 64 byte line size

40H

Cache

No 2nd-level cache or, if processor contains a valid 2nd-level cache, no 3rd-level cache

41H

Cache

2nd-level cache: 128 KBytes, 4-way set associative, 32 byte line size

42H

Cache

2nd-level cache: 256 KBytes, 4-way set associative, 32 byte line size

43H

Cache

2nd-level cache: 512 KBytes, 4-way set associative, 32 byte line size

44H

Cache

2nd-level cache: 1 MByte, 4-way set associative, 32 byte line size

45H

Cache

2nd-level cache: 2 MByte, 4-way set associative, 32 byte line size

46H

Cache

3rd-level cache: 4 MByte, 4-way set associative, 64 byte line size

47H

Cache

3rd-level cache: 8 MByte, 8-way set associative, 64 byte line size

48H

Cache

2nd-level cache: 3MByte, 12-way set associative, 64 byte line size

49H

Cache

3rd-level cache: 4MB, 16-way set associative, 64-byte line size (Intel Xeon processor MP, Family 0FH, Model

06H);

2nd-level cache: 4 MByte, 16-way set associative, 64 byte line size

4AH

Cache

3rd-level cache: 6MByte, 12-way set associative, 64 byte line size

4BH

Cache

3rd-level cache: 8MByte, 16-way set associative, 64 byte line size

4CH

Cache

3rd-level cache: 12MByte, 12-way set associative, 64 byte line size

4DH

Cache

3rd-level cache: 16MByte, 16-way set associative, 64 byte line size

4EH

Cache

2nd-level cache: 6MByte, 24-way set associative, 64 byte line size

4FH

TLB

Instruction TLB: 4 KByte pages, 32 entries

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Table 3-12. Encoding of CPUID Leaf 2 Descriptors (Contd.)

Value

Type

Description

50H

TLB

Instruction TLB: 4 KByte and 2-MByte or 4-MByte pages, 64 entries

51H

TLB

Instruction TLB: 4 KByte and 2-MByte or 4-MByte pages, 128 entries

52H

TLB

Instruction TLB: 4 KByte and 2-MByte or 4-MByte pages, 256 entries

55H

TLB

Instruction TLB: 2-MByte or 4-MByte pages, fully associative, 7 entries

56H

TLB

Data TLB0: 4 MByte pages, 4-way set associative, 16 entries

57H

TLB

Data TLB0: 4 KByte pages, 4-way associative, 16 entries

59H

TLB

Data TLB0: 4 KByte pages, fully associative, 16 entries

5AH

TLB

Data TLB0: 2 MByte or 4 MByte pages, 4-way set associative, 32 entries

5BH

TLB

Data TLB: 4 KByte and 4 MByte pages, 64 entries

5CH

TLB

Data TLB: 4 KByte and 4 MByte pages,128 entries

5DH

TLB

Data TLB: 4 KByte and 4 MByte pages,256 entries

60H

Cache

1st-level data cache: 16 KByte, 8-way set associative, 64 byte line size

61H

TLB

Instruction TLB: 4 KByte pages, fully associative, 48 entries

63H

TLB

Data TLB: 2 MByte or 4 MByte pages, 4-way set associative, 32 entries and a separate array with 1 GByte

pages, 4-way set associative, 4 entries

64H

TLB

Data TLB: 4 KByte pages, 4-way set associative, 512 entries

66H

Cache

1st-level data cache: 8 KByte, 4-way set associative, 64 byte line size

67H

Cache

1st-level data cache: 16 KByte, 4-way set associative, 64 byte line size

68H

Cache

1st-level data cache: 32 KByte, 4-way set associative, 64 byte line size

6AH

Cache

uTLB: 4 KByte pages, 8-way set associative, 64 entries

6BH

Cache

DTLB: 4 KByte pages, 8-way set associative, 256 entries

6CH

Cache

DTLB: 2M/4M pages, 8-way set associative, 128 entries

6DH

Cache

DTLB: 1 GByte pages, fully associative, 16 entries

70H

Cache

Trace cache: 12 K-μop, 8-way set associative

71H

Cache

Trace cache: 16 K-μop, 8-way set associative

72H

Cache

Trace cache: 32 K-μop, 8-way set associative

76H

TLB

Instruction TLB: 2M/4M pages, fully associative, 8 entries

78H

Cache

2nd-level cache: 1 MByte, 4-way set associative, 64byte line size

79H

Cache

2nd-level cache: 128 KByte, 8-way set associative, 64 byte line size, 2 lines per sector

7AH

Cache

2nd-level cache: 256 KByte, 8-way set associative, 64 byte line size, 2 lines per sector

7BH

Cache

2nd-level cache: 512 KByte, 8-way set associative, 64 byte line size, 2 lines per sector

7CH

Cache

2nd-level cache: 1 MByte, 8-way set associative, 64 byte line size, 2 lines per sector

7DH

Cache

2nd-level cache: 2 MByte, 8-way set associative, 64byte line size

7FH

Cache

2nd-level cache: 512 KByte, 2-way set associative, 64-byte line size

80H

Cache

2nd-level cache: 512 KByte, 8-way set associative, 64-byte line size

82H

Cache

2nd-level cache: 256 KByte, 8-way set associative, 32 byte line size

83H

Cache

2nd-level cache: 512 KByte, 8-way set associative, 32 byte line size

84H

Cache

2nd-level cache: 1 MByte, 8-way set associative, 32 byte line size

85H

Cache

2nd-level cache: 2 MByte, 8-way set associative, 32 byte line size

86H

Cache

2nd-level cache: 512 KByte, 4-way set associative, 64 byte line size

87H

Cache

2nd-level cache: 1 MByte, 8-way set associative, 64 byte line size

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Table 3-12. Encoding of CPUID Leaf 2 Descriptors (Contd.)

Value

Type

Description

A0H

DTLB

DTLB: 4k pages, fully associative, 32 entries

B0H

TLB

Instruction TLB: 4 KByte pages, 4-way set associative, 128 entries

B1H

TLB

Instruction TLB: 2M pages, 4-way, 8 entries or 4M pages, 4-way, 4 entries

B2H

TLB

Instruction TLB: 4KByte pages, 4-way set associative, 64 entries

B3H

TLB

Data TLB: 4 KByte pages, 4-way set associative, 128 entries

B4H

TLB

Data TLB1: 4 KByte pages, 4-way associative, 256 entries

B5H

TLB

Instruction TLB: 4KByte pages, 8-way set associative, 64 entries

B6H

TLB

Instruction TLB: 4KByte pages, 8-way set associative, 128 entries

BAH

TLB

Data TLB1: 4 KByte pages, 4-way associative, 64 entries

C0H

TLB

Data TLB: 4 KByte and 4 MByte pages, 4-way associative, 8 entries

C1H

STLB

Shared 2nd-Level TLB: 4 KByte/2MByte pages, 8-way associative, 1024 entries

C2H

DTLB

DTLB: 4 KByte/2 MByte pages, 4-way associative, 16 entries

C3H

STLB

Shared 2nd-Level TLB: 4 KByte /2 MByte pages, 6-way associative, 1536 entries. Also 1GBbyte pages, 4-way,

16 entries.

C4H

DTLB

DTLB: 2M/4M Byte pages, 4-way associative, 32 entries

CAH

STLB

Shared 2nd-Level TLB: 4 KByte pages, 4-way associative, 512 entries

D0H

Cache

3rd-level cache: 512 KByte, 4-way set associative, 64 byte line size

D1H

Cache

3rd-level cache: 1 MByte, 4-way set associative, 64 byte line size

D2H

Cache

3rd-level cache: 2 MByte, 4-way set associative, 64 byte line size

D6H

Cache

3rd-level cache: 1 MByte, 8-way set associative, 64 byte line size

D7H

Cache

3rd-level cache: 2 MByte, 8-way set associative, 64 byte line size

D8H

Cache

3rd-level cache: 4 MByte, 8-way set associative, 64 byte line size

DCH

Cache

3rd-level cache: 1.5 MByte, 12-way set associative, 64 byte line size

DDH

Cache

3rd-level cache: 3 MByte, 12-way set associative, 64 byte line size

DEH

Cache

3rd-level cache: 6 MByte, 12-way set associative, 64 byte line size

E2H

Cache

3rd-level cache: 2 MByte, 16-way set associative, 64 byte line size

E3H

Cache

3rd-level cache: 4 MByte, 16-way set associative, 64 byte line size

E4H

Cache

3rd-level cache: 8 MByte, 16-way set associative, 64 byte line size

EAH

Cache

3rd-level cache: 12MByte, 24-way set associative, 64 byte line size

EBH

Cache

3rd-level cache: 18MByte, 24-way set associative, 64 byte line size

ECH

Cache

3rd-level cache: 24MByte, 24-way set associative, 64 byte line size

F0H

Prefetch

64-Byte prefetching

F1H

Prefetch

128-Byte prefetching

FEH

General

CPUID leaf 2 does not report TLB descriptor information; use CPUID leaf 18H to query TLB and other address

translation parameters.

FFH

General

CPUID leaf 2 does not report cache descriptor information, use CPUID leaf 4 to query cache parameters

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Example 3-1. Example of Cache and TLB Interpretation

The first member of the family of Pentium 4 processors returns the following information about caches and TLBs

when the CPUID executes with an input value of 2:

EAX

66 5B 50 01H

EBX

ECX

EDX

00 7A 70 00H

Which means:

• The least-significant byte (byte 0) of register EAX is set to 01H. This value should be ignored.

• The most-significant bit of all four registers (EAX, EBX, ECX, and EDX) is set to 0, indicating that each register

contains valid 1-byte descriptors.

• Bytes 1, 2, and 3 of register EAX indicate that the processor has:

— 50H - a 64-entry instruction TLB, for mapping 4-KByte and 2-MByte or 4-MByte pages.

— 5BH - a 64-entry data TLB, for mapping 4-KByte and 4-MByte pages.

— 66H - an 8-KByte 1st level data cache, 4-way set associative, with a 64-Byte cache line size.

• The descriptors in registers EBX and ECX are valid, but contain NULL descriptors.

• Bytes 0, 1, 2, and 3 of register EDX indicate that the processor has:

— 00H - NULL descriptor.

— 70H - Trace cache: 12 K-μop, 8-way set associative.

— 7AH - a 256-KByte 2nd level cache, 8-way set associative, with a sectored, 64-byte cache line size.

— 00H - NULL descriptor.

INPUT EAX = 04H: Returns Deterministic Cache Parameters for Each Level

When CPUID executes with EAX set to 04H and ECX contains an index value, the processor returns encoded data

that describe a set of deterministic cache parameters (for the cache level associated with the input in ECX). Valid

index values start from 0.

Software can enumerate the deterministic cache parameters for each level of the cache hierarchy starting with an

index value of 0, until the parameters report the value associated with the cache type field is 0. The architecturally

defined fields reported by deterministic cache parameters are documented in Table 3-8.

This Cache Size in Bytes

= (Ways + 1) * (Partitions + 1) * (Line_Size + 1) * (Sets + 1)

= (EBX[31:22] + 1) * (EBX[21:12] + 1) * (EBX[11:0] + 1) * (ECX + 1)

The CPUID leaf 04H also reports data that can be used to derive the topology of processor cores in a physical

package. This information is constant for all valid index values. Software can query the raw data reported by

executing CPUID with EAX=04H and ECX=0 and use it as part of the topology enumeration algorithm described in

Chapter 9, “Multiple-Processor Management,” in the Intel® 64 and IA-32 Architectures Software Developer’s

Manual, Volume 3A.

INPUT EAX = 05H: Returns MONITOR and MWAIT Features

When CPUID executes with EAX set to 05H, the processor returns information about features available to

MONITOR/MWAIT instructions. The MONITOR instruction is used for address-range monitoring in conjunction with

MWAIT instruction. The MWAIT instruction optionally provides additional extensions for advanced power manage-

ment. See Table 3-8.

INPUT EAX = 06H: Returns Thermal and Power Management Features

When CPUID executes with EAX set to 06H, the processor returns information about thermal and power manage-

ment features. See Table 3-8.

CPUID—CPU Identification

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INSTRUCTION SET REFERENCE, A-L

INPUT EAX = 07H: Returns Structured Extended Feature Enumeration Information

When CPUID executes with EAX set to 07H and ECX = 0, the processor returns information about the maximum

input value for sub-leaves that contain extended feature flags. See Table 3-8.

When CPUID executes with EAX set to 07H and the input value of ECX is invalid (see leaf 07H entry in Table 3-8),

the processor returns 0 in EAX/EBX/ECX/EDX. In subleaf 0, EAX returns the maximum input value of the highest

leaf 7 sub-leaf, and EBX, ECX & EDX contain information of extended feature flags.

INPUT EAX = 09H: Returns Direct Cache Access Information

When CPUID executes with EAX set to 09H, the processor returns information about Direct Cache Access capabili-

ties. See Table 3-8.

INPUT EAX = 0AH: Returns Architectural Performance Monitoring Features

When CPUID executes with EAX set to 0AH, the processor returns information about support for architectural

performance monitoring capabilities. Architectural performance monitoring is supported if the version ID (see Table

3-8) is greater than Pn 0. See Table 3-8.

For each version of architectural performance monitoring capability, software must enumerate this leaf to discover

the programming facilities and the architectural performance events available in the processor. The details are

described in Chapter 24, “Introduction to Virtual-Machine Extensions,” in the Intel® 64 and IA-32 Architectures

Software Developer’s Manual, Volume 3C.

INPUT EAX = 0BH: Returns Extended Topology Information

CPUID leaf 1FH is a preferred superset to leaf 0BH. Intel recommends first checking for the existence of Leaf 1FH

before using leaf 0BH.

When CPUID executes with EAX set to 0BH, the processor returns information about extended topology enumera-

tion data. Software must detect the presence of CPUID leaf 0BH by verifying (a) the highest leaf index supported

by CPUID is >= 0BH, and (b) CPUID.0BH:EBX[15:0] reports a non-zero value. See Table 3-8.

INPUT EAX = 0DH: Returns Processor Extended States Enumeration Information

When CPUID executes with EAX set to 0DH and ECX = 0, the processor returns information about the bit-vector

representation of all processor state extensions that are supported in the processor and storage size requirements

of the XSAVE/XRSTOR area. See Table 3-8.

When CPUID executes with EAX set to 0DH and ECX = n (n > 1, and is a valid sub-leaf index), the processor returns

information about the size and offset of each processor extended state save area within the XSAVE/XRSTOR area.

See Table 3-8. Software can use the forward-extendable technique depicted below to query the valid sub-leaves

and obtain size and offset information for each processor extended state save area:

For i = 2 to 62 // sub-leaf 1 is reserved

IF (CPUID.(EAX=0DH, ECX=0):VECTOR[i] = 1 ) // VECTOR is the 64-bit value of EDX:EAX

Execute CPUID.(EAX=0DH, ECX = i) to examine size and offset for sub-leaf i;

FI;

INPUT EAX = 0FH: Returns Intel Resource Director Technology (Intel RDT) Monitoring Enumeration Information

When CPUID executes with EAX set to 0FH and ECX = 0, the processor returns information about the bit-vector

representation of QoS monitoring resource types that are supported in the processor and maximum range of RMID

values the processor can use to monitor of any supported resource types. Each bit, starting from bit 1, corresponds

to a specific resource type if the bit is set. The bit position corresponds to the sub-leaf index (or ResID) that soft-

ware must use to query QoS monitoring capability available for that type. See Table 3-8.

When CPUID executes with EAX set to 0FH and ECX = n (n >= 1, and is a valid ResID), the processor returns infor-

mation software can use to program IA32_PQR_ASSOC, IA32_QM_EVTSEL MSRs before reading QoS data from the

IA32_QM_CTR MSR.

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INSTRUCTION SET REFERENCE, A-L

INPUT EAX = 10H: Returns Intel Resource Director Technology (Intel RDT) Allocation Enumeration Information

When CPUID executes with EAX set to 10H and ECX = 0, the processor returns information about the bit-vector

representation of QoS Enforcement resource types that are supported in the processor. Each bit, starting from bit

1, corresponds to a specific resource type if the bit is set. The bit position corresponds to the sub-leaf index (or

ResID) that software must use to query QoS enforcement capability available for that type. See Table 3-8.

When CPUID executes with EAX set to 10H and ECX = n (n >= 1, and is a valid ResID), the processor returns infor-

mation about available classes of service and range of QoS mask MSRs that software can use to configure each

class of services using capability bit masks in the QoS Mask registers, IA32_resourceType_Mask_n.

INPUT EAX = 12H: Returns Intel SGX Enumeration Information

When CPUID executes with EAX set to 12H and ECX = 0H, the processor returns information about Intel SGX capa-

bilities. See Table 3-8.

When CPUID executes with EAX set to 12H and ECX = 1H, the processor returns information about Intel SGX attri-

butes. See Table 3-8.

When CPUID executes with EAX set to 12H and ECX = n (n > 1), the processor returns information about Intel SGX

Enclave Page Cache. See Table 3-8.

INPUT EAX = 14H: Returns Intel Processor Trace Enumeration Information

When CPUID executes with EAX set to 14H and ECX = 0H, the processor returns information about Intel Processor

Trace extensions. See Table 3-8.

When CPUID executes with EAX set to 14H and ECX = n (n > 0 and less than the number of non-zero bits in

CPUID.(EAX=14H, ECX= 0H).EAX), the processor returns information about packet generation in Intel Processor

Trace. See Table 3-8.

INPUT EAX = 15H: Returns Time Stamp Counter and Nominal Core Crystal Clock Information

When CPUID executes with EAX set to 15H and ECX = 0H, the processor returns information about Time Stamp

Counter and Core Crystal Clock. See Table 3-8.

INPUT EAX = 16H: Returns Processor Frequency Information

When CPUID executes with EAX set to 16H, the processor returns information about Processor Frequency Informa-

tion. See Table 3-8.

INPUT EAX = 17H: Returns System-On-Chip Information

When CPUID executes with EAX set to 17H, the processor returns information about the System-On-Chip Vendor

Attribute Enumeration. See Table 3-8.

INPUT EAX = 18H: Returns Deterministic Address Translation Parameters Information

When CPUID executes with EAX set to 18H, the processor returns information about the Deterministic Address

Translation Parameters. See Table 3-8.

INPUT EAX = 19H: Returns Key Locker Information

When CPUID executes with EAX set to 19H, the processor returns information about Key Locker. See Table 3-8.

INPUT EAX = 1AH: Returns Native Model ID Information

When CPUID executes with EAX set to 1AH, the processor returns information about Native Model Identification.

See Table 3-8.

INPUT EAX = 1BH: Returns PCONFIG Information

When CPUID executes with EAX set to 1BH, the processor returns information about PCONFIG capabilities. This

information is enumerated in sub-leaves selected by the value of ECX (starting with 0).

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INSTRUCTION SET REFERENCE, A-L

Each sub-leaf of CPUID function 1BH enumerates its sub-leaf type in EAX. If a sub-leaf type is 0, the sub-leaf is

invalid and zero is returned in EBX, ECX, and EDX. In this case, all subsequent sub-leaves (selected by larger input

values of ECX) are also invalid.

The only valid sub-leaf type currently defined is 1, meaning target identifier, indicating that the sub-leaf enumer-

ates target identifiers for the PCONFIG instruction. Any non-zero value returned in EBX, ECX, or EDX indicates a

valid target of the PCONFIG instruction (any value of zero should be ignored). The only target identifier currently

defined is 1, indicating MKTME. See the “PCONFIG—Platform Configuration” instruction in Chapter 4 of the Intel®

64 and IA-32 Architectures Software Developer’s Manual, Volume 2B for more information.

INPUT EAX = 1CH: Returns Last Branch Record Information

When CPUID executes with EAX set to 1CH, the processor returns information about LBRs (the architectural

feature). See Table 3-8.

INPUT EAX = 1DH: Returns Tile Information

When CPUID executes with EAX set to 1DH and ECX = 0H, the processor returns information about tile

architecture. See Table 3-8.

When CPUID executes with EAX set to 1DH and ECX = 1H, the processor returns information about tile palette 1.

See Table 3-8.

INPUT EAX = 1EH: Returns TMUL Information

When CPUID executes with EAX set to 1EH and ECX = 0H, the processor returns information about TMUL

capabilities. See Table 3-8.

INPUT EAX = 1FH: Returns V2 Extended Topology Information

When CPUID executes with EAX set to 1FH, the processor returns information about extended topology enumera-

tion data. Software must detect the presence of CPUID leaf 1FH by verifying (a) the highest leaf index supported

by CPUID is >= 1FH, and (b) CPUID.1FH:EBX[15:0] reports a non-zero value. See Table 3-8.

INPUT EAX = 20H: Returns History Reset Information

When CPUID executes with EAX set to 20H, the processor returns information about History Reset. See Table 3-8.

METHODS FOR RETURNING BRANDING INFORMATION

Use the following techniques to access branding information:

1. Processor brand string method.

2. Processor brand index; this method uses a software supplied brand string table.

These two methods are discussed in the following sections. For methods that are available in early processors, see

Section: “Identification of Earlier IA-32 Processors” in Chapter 20 of the Intel® 64 and IA-32 Architectures Soft-

ware Developer’s Manual, Volume 1.

The Processor Brand String Method

Figure 3-9 describes the algorithm used for detection of the brand string. Processor brand identification software

should execute this algorithm on all Intel 64 and IA-32 processors.

This method (introduced with Pentium 4 processors) returns an ASCII brand identification string and the Processor

Base frequency of the processor to the EAX, EBX, ECX, and EDX registers.

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INSTRUCTION SET REFERENCE, A-L

Input: EAX=

0x80000000

CPUID

False

Processor Brand

IF (EAX & 0x80000000)

String Not

Supported

CPUID

True ≥

Function

Extended

Supported

EAX Return Value =

Max. Extended CPUID

Function Index

True

IF (EAX Return Value

Processor Brand

String Supported

≥ 0x80000004)

OM15194

Figure 3-9. Determination of Support for the Processor Brand String

How Brand Strings Work

To use the brand string method, execute CPUID with EAX input of 8000002H through 80000004H. For each input

value, CPUID returns 16 ASCII characters using EAX, EBX, ECX, and EDX. The returned string will be NULL-termi-

nated.

Table 3-13 shows the brand string that is returned by the first processor in the Pentium 4 processor family.

Table 3-13. Processor Brand String Returned with Pentium 4 Processor

EAX Input Value

Return Values

ASCII Equivalent

80000002H

EAX = 20202020H

“

”

EBX = 20202020H

“

”

ECX = 20202020H

“

”

EDX = 6E492020H

“nI

”

80000003H

EAX = 286C6574H

“(let”

EBX = 50202952H

“P )R”

ECX = 69746E65H

“itne”

EDX = 52286D75H

“R(mu”

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INSTRUCTION SET REFERENCE, A-L

Table 3-13. Processor Brand String Returned with Pentium 4 Processor (Contd.)

EAX Input Value

Return Values

ASCII Equivalent

80000004H

EAX = 20342029H

“ 4 )”

EBX = 20555043H

“ UPC”

ECX = 30303531H

“0051”

EDX = 007A484DH

“\0zHM”

Extracting the Processor Frequency from Brand Strings

Figure 3-10 provides an algorithm which software can use to extract the Processor Base frequency from the

processor brand string.

Scan "Brand String" in

Reverse Byte Order

"zHM", or

Match

"zHG", or

Substring

"zHT"

False

IF Substring Matched

Report Error

Determine "Freq"

If "zHM"

True

and "Multiplier"

Multiplier = 1 x 10⁶

If "zHG"

Multiplier = 1 x 10⁹

Determine "Multiplier"

If "zHT"

Multiplier = 1 x 10¹²

Scan Digits

Until Blank

Reverse Digits

Determine "Freq"

In Reverse Order

To Decimal Value

Processor Base

Frequency =

"Freq" = X.YZ if

"Freq" x "Multiplier"

Digits = "ZY.X"

Figure 3-10. Algorithm for Extracting Processor Frequency

The Processor Brand Index Method

The brand index method (introduced with Pentium^® III Xeon^® processors) provides an entry point into a brand

identification table that is maintained in memory by system software and is accessible from system- and user-level

code. In this table, each brand index is associate with an ASCII brand identification string that identifies the official

Intel family and model number of a processor.

When CPUID executes with EAX set to 1, the processor returns a brand index to the low byte in EBX. Software can

then use this index to locate the brand identification string for the processor in the brand identification table. The

first entry (brand index 0) in this table is reserved, allowing for backward compatibility with processors that do not

support the brand identification feature. Starting with processor signature family ID = 0FH, model = 03H, brand

index method is no longer supported. Use brand string method instead.

Table 3-14 shows brand indices that have identification strings associated with them.

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INSTRUCTION SET REFERENCE, A-L

Table 3-14. Mapping of Brand Indices; and Intel 64 and IA-32 Processor Brand Strings

Brand Index

Brand String

00H

This processor does not support the brand identification feature

01H

Intel(R) Celeron(R) processor¹

02H

Intel(R) Pentium(R) III processor¹

03H

Intel(R) Pentium(R) III Xeon(R) processor; If processor signature = 000006B1h, then Intel(R) Celeron(R)

processor

04H

Intel(R) Pentium(R) III processor

06H

Mobile Intel(R) Pentium(R) III processor-M

07H

Mobile Intel(R) Celeron(R) processor¹

08H

Intel(R) Pentium(R) 4 processor

09H

Intel(R) Pentium(R) 4 processor

0AH

Intel(R) Celeron(R) processor¹

0BH

Intel(R) Xeon(R) processor; If processor signature = 00000F13h, then Intel(R) Xeon(R) processor MP

0CH

Intel(R) Xeon(R) processor MP

0EH

Mobile Intel(R) Pentium(R) 4 processor-M; If processor signature = 00000F13h, then Intel(R) Xeon(R) processor

0FH

Mobile Intel(R) Celeron(R) processor¹

11H

Mobile Genuine Intel(R) processor

12H

Intel(R) Celeron(R) M processor

13H

Mobile Intel(R) Celeron(R) processor¹

14H

Intel(R) Celeron(R) processor

15H

Mobile Genuine Intel(R) processor

16H

Intel(R) Pentium(R) M processor

17H

Mobile Intel(R) Celeron(R) processor¹

18H - 0FFH

RESERVED

NOTES:

1. Indicates versions of these processors that were introduced after the Pentium III

IA-32 Architecture Compatibility

CPUID is not supported in early models of the Intel486 processor or in any IA-32 processor earlier than the

Intel486 processor.

Operation

IA32_BIOS_SIGN_ID MSR := Update with installed microcode revision number;

CASE (EAX) OF

EAX = 0:

EAX := Highest basic function input value understood by CPUID;

EBX := Vendor identification string;

EDX := Vendor identification string;

ECX := Vendor identification string;

BREAK;

EAX = 1H:

EAX[3:0] := Stepping ID;

EAX[7:4] := Model;

EAX[11:8] := Family;

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INSTRUCTION SET REFERENCE, A-L

EAX[13:12] := Processor type;

EAX[15:14] := Reserved;

EAX[19:16] := Extended Model;

EAX[27:20] := Extended Family;

EAX[31:28] := Reserved;

EBX[7:0] := Brand Index; (* Reserved if the value is zero. *)

EBX[15:8] := CLFLUSH Line Size;

EBX[16:23] := Reserved; (* Number of threads enabled = 2 if MT enable fuse set. *)

EBX[24:31] := Initial APIC ID;

ECX := Feature flags; (* See Figure 3-7. *)

EDX := Feature flags; (* See Figure 3-8. *)

BREAK;

EAX = 2H:

EAX := Cache and TLB information;

EBX := Cache and TLB information;

ECX := Cache and TLB information;

EDX := Cache and TLB information;

BREAK;

EAX = 3H:

EAX := Reserved;

EBX := Reserved;

ECX := ProcessorSerialNumber[31:0];

(* Pentium III processors only, otherwise reserved. *)

EDX := ProcessorSerialNumber[63:32];

(* Pentium III processors only, otherwise reserved. *

BREAK

EAX = 4H:

EAX := Deterministic Cache Parameters Leaf; (* See Table 3-8. *)

EBX := Deterministic Cache Parameters Leaf;

ECX := Deterministic Cache Parameters Leaf;

EDX := Deterministic Cache Parameters Leaf;

BREAK;

EAX = 5H:

EAX := MONITOR/MWAIT Leaf; (* See Table 3-8. *)

EBX := MONITOR/MWAIT Leaf;

ECX := MONITOR/MWAIT Leaf;

EDX := MONITOR/MWAIT Leaf;

BREAK;

EAX = 6H:

EAX := Thermal and Power Management Leaf; (* See Table 3-8. *)

EBX := Thermal and Power Management Leaf;

ECX := Thermal and Power Management Leaf;

EDX := Thermal and Power Management Leaf;

BREAK;

EAX = 7H:

EAX := Structured Extended Feature Flags Enumeration Leaf; (* See Table 3-8. *)

EBX := Structured Extended Feature Flags Enumeration Leaf;

ECX := Structured Extended Feature Flags Enumeration Leaf;

EDX := Structured Extended Feature Flags Enumeration Leaf;

BREAK;

EAX = 8H:

EAX := Reserved = 0;

EBX := Reserved = 0;

ECX := Reserved = 0;

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INSTRUCTION SET REFERENCE, A-L

EDX := Reserved = 0;

BREAK;

EAX = 9H:

EAX := Direct Cache Access Information Leaf; (* See Table 3-8. *)

EBX := Direct Cache Access Information Leaf;

ECX := Direct Cache Access Information Leaf;

EDX := Direct Cache Access Information Leaf;

BREAK;

EAX = AH:

EAX := Architectural Performance Monitoring Leaf; (* See Table 3-8. *)

EBX := Architectural Performance Monitoring Leaf;

ECX := Architectural Performance Monitoring Leaf;

EDX := Architectural Performance Monitoring Leaf;

BREAK

EAX = BH:

EAX := Extended Topology Enumeration Leaf; (* See Table 3-8. *)

EBX := Extended Topology Enumeration Leaf;

ECX := Extended Topology Enumeration Leaf;

EDX := Extended Topology Enumeration Leaf;

BREAK;

EAX = CH:

EAX := Reserved = 0;

EBX := Reserved = 0;

ECX := Reserved = 0;

EDX := Reserved = 0;

BREAK;

EAX = DH:

EAX := Processor Extended State Enumeration Leaf; (* See Table 3-8. *)

EBX := Processor Extended State Enumeration Leaf;

ECX := Processor Extended State Enumeration Leaf;

EDX := Processor Extended State Enumeration Leaf;

BREAK;

EAX = EH:

EAX := Reserved = 0;

EBX := Reserved = 0;

ECX := Reserved = 0;

EDX := Reserved = 0;

BREAK;

EAX = FH:

EAX := Intel Resource Director Technology Monitoring Enumeration Leaf; (* See Table 3-8. *)

EBX := Intel Resource Director Technology Monitoring Enumeration Leaf;

ECX := Intel Resource Director Technology Monitoring Enumeration Leaf;

EDX := Intel Resource Director Technology Monitoring Enumeration Leaf;

BREAK;

EAX = 10H:

EAX := Intel Resource Director Technology Allocation Enumeration Leaf; (* See Table 3-8. *)

EBX := Intel Resource Director Technology Allocation Enumeration Leaf;

ECX := Intel Resource Director Technology Allocation Enumeration Leaf;

EDX := Intel Resource Director Technology Allocation Enumeration Leaf;

BREAK;

EAX = 12H:

EAX := Intel SGX Enumeration Leaf; (* See Table 3-8. *)

EBX := Intel SGX Enumeration Leaf;

ECX := Intel SGX Enumeration Leaf;

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INSTRUCTION SET REFERENCE, A-L

EDX := Intel SGX Enumeration Leaf;

BREAK;

EAX = 14H:

EAX := Intel Processor Trace Enumeration Leaf; (* See Table 3-8. *)

EBX := Intel Processor Trace Enumeration Leaf;

ECX := Intel Processor Trace Enumeration Leaf;

EDX := Intel Processor Trace Enumeration Leaf;

BREAK;

EAX = 15H:

EAX := Time Stamp Counter and Nominal Core Crystal Clock Information Leaf; (* See Table 3-8. *)

EBX := Time Stamp Counter and Nominal Core Crystal Clock Information Leaf;

ECX := Time Stamp Counter and Nominal Core Crystal Clock Information Leaf;

EDX := Time Stamp Counter and Nominal Core Crystal Clock Information Leaf;

BREAK;

EAX = 16H:

EAX := Processor Frequency Information Enumeration Leaf; (* See Table 3-8. *)

EBX := Processor Frequency Information Enumeration Leaf;

ECX := Processor Frequency Information Enumeration Leaf;

EDX := Processor Frequency Information Enumeration Leaf;

BREAK;

EAX = 17H:

EAX := System-On-Chip Vendor Attribute Enumeration Leaf; (* See Table 3-8. *)

EBX := System-On-Chip Vendor Attribute Enumeration Leaf;

ECX := System-On-Chip Vendor Attribute Enumeration Leaf;

EDX := System-On-Chip Vendor Attribute Enumeration Leaf;

BREAK;

EAX = 18H:

EAX := Deterministic Address Translation Parameters Enumeration Leaf; (* See Table 3-8. *)

EBX := Deterministic Address Translation Parameters Enumeration Leaf;

ECX := Deterministic Address Translation Parameters Enumeration Leaf;

EDX := Deterministic Address Translation Parameters Enumeration Leaf;

BREAK;

EAX = 19H:

EAX := Key Locker Enumeration Leaf; (* See Table 3-8. *)

EBX := Key Locker Enumeration Leaf;

ECX := Key Locker Enumeration Leaf;

EDX := Key Locker Enumeration Leaf;

BREAK;

EAX = 1AH:

EAX := Native Model ID Enumeration Leaf; (* See Table 3-8. *)

EBX := Native Model ID Enumeration Leaf;

ECX := Native Model ID Enumeration Leaf;

EDX := Native Model ID Enumeration Leaf;

BREAK;

EAX = 1BH:

EAX := PCONFIG Information Enumeration Leaf; (* See “INPUT EAX = 1BH: Returns PCONFIG Information” on page 3-251. *)

EBX := PCONFIG Information Enumeration Leaf;

ECX := PCONFIG Information Enumeration Leaf;

EDX := PCONFIG Information Enumeration Leaf;

BREAK;

EAX = 1CH:

EAX := Last Branch Record Information Enumeration Leaf; (* See Table 3-8. *)

EBX := Last Branch Record Information Enumeration Leaf;

ECX := Last Branch Record Information Enumeration Leaf;

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INSTRUCTION SET REFERENCE, A-L

EDX := Last Branch Record Information Enumeration Leaf;

BREAK;

EAX = 1DH:

EAX := Tile Information Enumeration Leaf; (* See Table 3-8. *)

EBX := Tile Information Enumeration Leaf;

ECX := Tile Information Enumeration Leaf;

EDX := Tile Information Enumeration Leaf;

BREAK;

EAX = 1EH:

EAX := TMUL Information Enumeration Leaf; (* See Table 3-8. *)

EBX := TMUL Information Enumeration Leaf;

ECX := TMUL Information Enumeration Leaf;

EDX := TMUL Information Enumeration Leaf;

BREAK;

EAX = 1FH:

EAX := V2 Extended Topology Enumeration Leaf; (* See Table 3-8. *)

EBX := V2 Extended Topology Enumeration Leaf;

ECX := V2 Extended Topology Enumeration Leaf;

EDX := V2 Extended Topology Enumeration Leaf;

BREAK;

EAX = 20H:

EAX := Processor History Reset Sub-leaf; (* See Table 3-8. *)

EBX := Processor History Reset Sub-leaf;

ECX := Processor History Reset Sub-leaf;

EDX := Processor History Reset Sub-leaf;

BREAK;

EAX = 80000000H:

EAX := Highest extended function input value understood by CPUID;

EBX := Reserved;

ECX := Reserved;

EDX := Reserved;

BREAK;

EAX = 80000001H:

EAX := Reserved;

EBX := Reserved;

ECX := Extended Feature Bits (* See Table 3-8.*);

EDX := Extended Feature Bits (* See Table 3-8. *);

BREAK;

EAX = 80000002H:

EAX := Processor Brand String;

EBX := Processor Brand String, continued;

ECX := Processor Brand String, continued;

EDX := Processor Brand String, continued;

BREAK;

EAX = 80000003H:

EAX := Processor Brand String, continued;

EBX := Processor Brand String, continued;

ECX := Processor Brand String, continued;

EDX := Processor Brand String, continued;

BREAK;

EAX = 80000004H:

EAX := Processor Brand String, continued;

EBX := Processor Brand String, continued;

ECX := Processor Brand String, continued;

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INSTRUCTION SET REFERENCE, A-L

EDX := Processor Brand String, continued;

BREAK;

EAX = 80000005H:

EAX := Reserved = 0;

EBX := Reserved = 0;

ECX := Reserved = 0;

EDX := Reserved = 0;

BREAK;

EAX = 80000006H:

EAX := Reserved = 0;

EBX := Reserved = 0;

ECX := Cache information;

EDX := Reserved = 0;

BREAK;

EAX = 80000007H:

EAX := Reserved = 0;

EBX := Reserved = 0;

ECX := Reserved = 0;

EDX := Reserved = Misc Feature Flags;

BREAK;

EAX = 80000008H:

EAX := Reserved = Physical Address Size Information;

EBX := Reserved = Virtual Address Size Information;

ECX := Reserved = 0;

EDX := Reserved = 0;

BREAK;

EAX >= 40000000H and EAX <= 4FFFFFFFH:

DEFAULT: (* EAX = Value outside of recognized range for CPUID. *)

(* If the highest basic information leaf data depend on ECX input value, ECX is honored.*)

EAX := Reserved; (* Information returned for highest basic information leaf. *)

EBX := Reserved; (* Information returned for highest basic information leaf. *)

ECX := Reserved; (* Information returned for highest basic information leaf. *)

EDX := Reserved; (* Information returned for highest basic information leaf. *)

BREAK;

ESAC;

Flags Affected

None.

Exceptions (All Operating Modes)

#UD

If the LOCK prefix is used.

In earlier IA-32 processors that do not support the CPUID instruction, execution of the instruc-

tion results in an invalid opcode (#UD) exception being generated.

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INSTRUCTION SET REFERENCE, A-L

CRC32—Accumulate CRC32 Value

Opcode/

Op/

64-Bit

Compat/

Description

Instruction

Mode

Leg Mode

F2 0F 38 F0 /r

Valid

Accumulate CRC32 on r/m8.

CRC32 r32, r/m8

F2 REX 0F 38 F0 /r

Valid

N.E.

Accumulate CRC32 on r/m8.

CRC32 r32, r/m8¹

F2 0F 38 F1 /r

Valid

Accumulate CRC32 on r/m16.

CRC32 r32, r/m16

F2 0F 38 F1 /r

Valid

Accumulate CRC32 on r/m32.

CRC32 r32, r/m32

F2 REX.W 0F 38 F0 /r

Valid

N.E.

Accumulate CRC32 on r/m8.

CRC32 r64, r/m8

F2 REX.W 0F 38 F1 /r

Valid

N.E.

Accumulate CRC32 on r/m64.

CRC32 r64, r/m64

NOTES:

1. In 64-bit mode, r/m8 can not be encoded to access the following byte registers if a REX prefix is used: AH, BH, CH, DH.

Instruction Operand Encoding

Op/En

Operand 1

Operand 2

Operand 3

Operand 4

ModRM:reg (r, w)

ModRM:r/m (r)

N/A

Description

Starting with an initial value in the first operand (destination operand), accumulates a CRC32 (polynomial

11EDC6F41H) value for the second operand (source operand) and stores the result in the destination operand. The

source operand can be a register or a memory location. The destination operand must be an r32 or r64 register. If

the destination is an r64 register, then the 32-bit result is stored in the least significant double word and

00000000H is stored in the most significant double word of the r64 register.

The initial value supplied in the destination operand is a double word integer stored in the r32 register or the least

significant double word of the r64 register. To incrementally accumulate a CRC32 value, software retains the result

of the previous CRC32 operation in the destination operand, then executes the CRC32 instruction again with new

input data in the source operand. Data contained in the source operand is processed in reflected bit order. This

means that the most significant bit of the source operand is treated as the least significant bit of the quotient, and

so on, for all the bits of the source operand. Likewise, the result of the CRC operation is stored in the destination

operand in reflected bit order. This means that the most significant bit of the resulting CRC (bit 31) is stored in the

least significant bit of the destination operand (bit 0), and so on, for all the bits of the CRC.

Operation

Notes:

BIT_REFLECT64: DST[63-0] = SRC[0-63]

BIT_REFLECT32: DST[31-0] = SRC[0-31]

BIT_REFLECT16: DST[15-0] = SRC[0-15]

BIT_REFLECT8: DST[7-0] = SRC[0-7]

MOD2: Remainder from Polynomial division modulus 2

CRC32—Accumulate CRC32 Value

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3-261

INSTRUCTION SET REFERENCE, A-L

CRC32 instruction for 64-bit source operand and 64-bit destination operand:

TEMP1[63-0] := BIT_REFLECT64 (SRC[63-0])

TEMP2[31-0] := BIT_REFLECT32 (DEST[31-0])

TEMP3[95-0] := TEMP1[63-0] « 32

TEMP4[95-0] := TEMP2[31-0] « 64

TEMP5[95-0] := TEMP3[95-0] XOR TEMP4[95-0]

TEMP6[31-0] := TEMP5[95-0] MOD2 11EDC6F41H

DEST[31-0] := BIT_REFLECT (TEMP6[31-0])

DEST[63-32] := 00000000H

CRC32 instruction for 32-bit source operand and 32-bit destination operand:

TEMP1[31-0] := BIT_REFLECT32 (SRC[31-0])

TEMP2[31-0] := BIT_REFLECT32 (DEST[31-0])

TEMP3[63-0] := TEMP1[31-0] « 32

TEMP4[63-0] := TEMP2[31-0] « 32

TEMP5[63-0] := TEMP3[63-0] XOR TEMP4[63-0]

TEMP6[31-0] := TEMP5[63-0] MOD2 11EDC6F41H

DEST[31-0] := BIT_REFLECT (TEMP6[31-0])

CRC32 instruction for 16-bit source operand and 32-bit destination operand:

TEMP1[15-0] := BIT_REFLECT16 (SRC[15-0])

TEMP2[31-0] := BIT_REFLECT32 (DEST[31-0])

TEMP3[47-0] := TEMP1[15-0] « 32

TEMP4[47-0] := TEMP2[31-0] « 16

TEMP5[47-0] := TEMP3[47-0] XOR TEMP4[47-0]

TEMP6[31-0] := TEMP5[47-0] MOD2 11EDC6F41H

DEST[31-0] := BIT_REFLECT (TEMP6[31-0])

CRC32 instruction for 8-bit source operand and 64-bit destination operand:

TEMP1[7-0] := BIT_REFLECT8(SRC[7-0])

TEMP2[31-0] := BIT_REFLECT32 (DEST[31-0])

TEMP3[39-0] := TEMP1[7-0] « 32

TEMP4[39-0] := TEMP2[31-0] « 8

TEMP5[39-0] := TEMP3[39-0] XOR TEMP4[39-0]

TEMP6[31-0] := TEMP5[39-0] MOD2 11EDC6F41H

DEST[31-0] := BIT_REFLECT (TEMP6[31-0])

DEST[63-32] := 00000000H

CRC32 instruction for 8-bit source operand and 32-bit destination operand:

TEMP1[7-0] := BIT_REFLECT8(SRC[7-0])

TEMP2[31-0] := BIT_REFLECT32 (DEST[31-0])

TEMP3[39-0] := TEMP1[7-0] « 32

TEMP4[39-0] := TEMP2[31-0] « 8

TEMP5[39-0] := TEMP3[39-0] XOR TEMP4[39-0]

TEMP6[31-0] := TEMP5[39-0] MOD2 11EDC6F41H

DEST[31-0] := BIT_REFLECT (TEMP6[31-0])

Flags Affected

None

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CRC32—Accumulate CRC32 Value

INSTRUCTION SET REFERENCE, A-L

Intel C/C++ Compiler Intrinsic Equivalent

unsigned int _mm_crc32_u8( unsigned int crc, unsigned char data )

unsigned int _mm_crc32_u16( unsigned int crc, unsigned short data )

unsigned int _mm_crc32_u32( unsigned int crc, unsigned int data )

unsigned __int64 _mm_crc32_u64( unsigned __int64 crc, unsigned __int64 data )

SIMD Floating-Point Exceptions

None

Protected Mode Exceptions

#GP(0)

If a memory operand effective address is outside the CS, DS, ES, FS or GS segments.

#SS(0)

If a memory operand effective address is outside the SS segment limit.

#PF (fault-code)

For a page fault.

#AC(0)

If alignment checking is enabled and an unaligned memory reference is made while the

current privilege level is 3.

#UD

If CPUID.01H:ECX.SSE4_2 [Bit 20] = 0.

If LOCK prefix is used.

Real-Address Mode Exceptions

#GP(0)

If any part of the operand lies outside of the effective address space from 0 to 0FFFFH.

#SS(0)

If a memory operand effective address is outside the SS segment limit.

#UD

If CPUID.01H:ECX.SSE4_2 [Bit 20] = 0.

If LOCK prefix is used.

Virtual 8086 Mode Exceptions

#GP(0)

If any part of the operand lies outside of the effective address space from 0 to 0FFFFH.

#SS(0)

If a memory operand effective address is outside the SS segment limit.

#PF (fault-code)

For a page fault.

#AC(0)

If alignment checking is enabled and an unaligned memory reference is made.

#UD

If CPUID.01H:ECX.SSE4_2 [Bit 20] = 0.

If LOCK prefix is used.

Compatibility Mode Exceptions

Same exceptions as in Protected Mode.

64-Bit Mode Exceptions

#GP(0)

If the memory address is in a non-canonical form.

#SS(0)

If a memory address referencing the SS segment is in a non-canonical form.

#PF (fault-code)

For a page fault.

#AC(0)

If alignment checking is enabled and an unaligned memory reference is made while the

current privilege level is 3.

#UD

If CPUID.01H:ECX.SSE4_2 [Bit 20] = 0.

If LOCK prefix is used.

CRC32—Accumulate CRC32 Value

Vol. 2A

3-263

INSTRUCTION SET REFERENCE, A-L

CVTDQ2PD—Convert Packed Doubleword Integers to Packed Double Precision Floating-Point

Values

Opcode/

Op /

64/32

CPUID

Description

Instruction

bit Mode

Feature

Support

Flag

F3 0F E6 /r

V/V

SSE2

Convert two packed signed doubleword integers from

CVTDQ2PD xmm1, xmm2/m64

xmm2/mem to two packed double precision floating-

point values in xmm1.

VEX.128.F3.0F.WIG E6 /r

V/V

AVX

Convert two packed signed doubleword integers from

VCVTDQ2PD xmm1, xmm2/m64

xmm2/mem to two packed double precision floating-

point values in xmm1.

VEX.256.F3.0F.WIG E6 /r

V/V

AVX

Convert four packed signed doubleword integers from

VCVTDQ2PD ymm1, xmm2/m128

xmm2/mem to four packed double precision floating-

point values in ymm1.

EVEX.128.F3.0F.W0 E6 /r

V/V

AVX512VL

Convert 2 packed signed doubleword integers from

VCVTDQ2PD xmm1 {k1}{z},

AVX512F

xmm2/m64/m32bcst to eight packed double precision

xmm2/m64/m32bcst

floating-point values in xmm1 with writemask k1.

EVEX.256.F3.0F.W0 E6 /r

V/V

AVX512VL

Convert 4 packed signed doubleword integers from

VCVTDQ2PD ymm1 {k1}{z},

AVX512F

xmm2/m128/m32bcst to 4 packed double precision

xmm2/m128/m32bcst

floating-point values in ymm1 with writemask k1.

EVEX.512.F3.0F.W0 E6 /r

V/V

AVX512F

Convert eight packed signed doubleword integers from

VCVTDQ2PD zmm1 {k1}{z},

ymm2/m256/m32bcst to eight packed double precision

ymm2/m256/m32bcst

floating-point values in zmm1 with writemask k1.

Instruction Operand Encoding

Op/En

Tuple Type

Operand 1

Operand 2

Operand 3

Operand 4

N/A

ModRM:reg (w)

ModRM:r/m (r)

N/A

Half

ModRM:reg (w)

ModRM:r/m (r)

N/A

Description

Converts two, four or eight packed signed doubleword integers in the source operand (the second operand) to two,

four or eight packed double precision floating-point values in the destination operand (the first operand).

EVEX encoded versions: The source operand can be a YMM/XMM/XMM (low 64 bits) register, a 256/128/64-bit

memory location or a 256/128/64-bit vector broadcasted from a 32-bit memory location. The destination operand

is a ZMM/YMM/XMM register conditionally updated with writemask k1. Attempt to encode this instruction with EVEX

embedded rounding is ignored.

VEX.256 encoded version: The source operand is an XMM register or 128- bit memory location. The destination

operand is a YMM register.

VEX.128 encoded version: The source operand is an XMM register or 64- bit memory location. The destination

operand is a XMM register. The upper Bits (MAXVL-1:128) of the corresponding ZMM register destination are

zeroed.

128-bit Legacy SSE version: The source operand is an XMM register or 64- bit memory location. The destination

operand is an XMM register. The upper Bits (MAXVL-1:128) of the corresponding ZMM register destination are

unmodified.

VEX.vvvv and EVEX.vvvv are reserved and must be 1111b, otherwise instructions will #UD.

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CVTDQ2PD—Convert Packed Doubleword Integers to Packed Double Precision Floating-Point Values

INSTRUCTION SET REFERENCE, A-L

VCVTDQ2PD (EVEX encoded versions) when src operand is a memory source

(KL, VL) = (2, 128), (4, 256), (8, 512)

FOR j := 0 TO KL-1

i := j * 64

k := j * 32

IF k1[j] OR *no writemask*

THEN

IF (EVEX.b = 1)

THEN

DEST[i+63:i] :=

Convert_Integer_To_Double_Precision_Floating_Point(SRC[31:0])

ELSE

DEST[i+63:i] :=

Convert_Integer_To_Double_Precision_Floating_Point(SRC[k+31:k])

FI;

ELSE

IF *merging-masking*

; merging-masking

THEN *DEST[i+63:i] remains unchanged*

ELSE

; zeroing-masking

DEST[i+63:i] := 0

FI;

ENDFOR

DEST[MAXVL-1:VL] := 0

VCVTDQ2PD (VEX.256 encoded version)

DEST[63:0] := Convert_Integer_To_Double_Precision_Floating_Point(SRC[31:0])

DEST[127:64] := Convert_Integer_To_Double_Precision_Floating_Point(SRC[63:32])

DEST[191:128] := Convert_Integer_To_Double_Precision_Floating_Point(SRC[95:64])

DEST[255:192] := Convert_Integer_To_Double_Precision_Floating_Point(SRC[127:96)

DEST[MAXVL-1:256] := 0

VCVTDQ2PD (VEX.128 encoded version)

DEST[63:0] := Convert_Integer_To_Double_Precision_Floating_Point(SRC[31:0])

DEST[127:64] := Convert_Integer_To_Double_Precision_Floating_Point(SRC[63:32])

DEST[MAXVL-1:128] := 0

CVTDQ2PD (128-bit Legacy SSE version)

DEST[63:0] := Convert_Integer_To_Double_Precision_Floating_Point(SRC[31:0])

DEST[127:64] := Convert_Integer_To_Double_Precision_Floating_Point(SRC[63:32])

DEST[MAXVL-1:128] (unmodified)

Intel C/C++ Compiler Intrinsic Equivalent

VCVTDQ2PD __m512d _mm512_cvtepi32_pd( __m256i a);

VCVTDQ2PD __m512d _mm512_mask_cvtepi32_pd( __m512d s, __mmask8 k, __m256i a);

VCVTDQ2PD __m512d _mm512_maskz_cvtepi32_pd( __mmask8 k, __m256i a);

VCVTDQ2PD __m256d _mm256_cvtepi32_pd (__m128i src);

VCVTDQ2PD __m256d _mm256_mask_cvtepi32_pd( __m256d s, __mmask8 k, __m256i a);

VCVTDQ2PD __m256d _mm256_maskz_cvtepi32_pd( __mmask8 k, __m256i a);

VCVTDQ2PD __m128d _mm_mask_cvtepi32_pd( __m128d s, __mmask8 k, __m128i a);

VCVTDQ2PD __m128d _mm_maskz_cvtepi32_pd( __mmask8 k, __m128i a);

CVTDQ2PD __m128d _mm_cvtepi32_pd (__m128i src)

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CVTDQ2PD—Convert Packed Doubleword Integers to Packed Double Precision Floating-Point Values

INSTRUCTION SET REFERENCE, A-L

CVTDQ2PS—Convert Packed Doubleword Integers to Packed Single Precision Floating-Point

Values

Opcode

Op /

64/32

CPUID

Description

Instruction

bit Mode

Feature

Support

Flag

NP 0F 5B /r

V/V

SSE2

Convert four packed signed doubleword integers from

CVTDQ2PS xmm1, xmm2/m128

xmm2/mem to four packed single precision floating-

point values in xmm1.

VEX.128.0F.WIG 5B /r

V/V

AVX

Convert four packed signed doubleword integers from

VCVTDQ2PS xmm1, xmm2/m128

xmm2/mem to four packed single precision floating-

point values in xmm1.

VEX.256.0F.WIG 5B /r

V/V

AVX

Convert eight packed signed doubleword integers from

VCVTDQ2PS ymm1, ymm2/m256

ymm2/mem to eight packed single precision floating-

point values in ymm1.

EVEX.128.0F.W0 5B /r

V/V

AVX512VL

Convert four packed signed doubleword integers from

VCVTDQ2PS xmm1 {k1}{z},

AVX512F

xmm2/m128/m32bcst to four packed single precision

xmm2/m128/m32bcst

floating-point values in xmm1with writemask k1.

EVEX.256.0F.W0 5B /r

V/V

AVX512VL

Convert eight packed signed doubleword integers from

VCVTDQ2PS ymm1 {k1}{z},

AVX512F

ymm2/m256/m32bcst to eight packed single precision

ymm2/m256/m32bcst

floating-point values in ymm1with writemask k1.

EVEX.512.0F.W0 5B /r

V/V

AVX512F

Convert sixteen packed signed doubleword integers

VCVTDQ2PS zmm1 {k1}{z},

from zmm2/m512/m32bcst to sixteen packed single

zmm2/m512/m32bcst{er}

precision floating-point values in zmm1with writemask

k1.

Instruction Operand Encoding

Op/En

Tuple Type

Operand 1

Operand 2

Operand 3

Operand 4

N/A

ModRM:reg (w)

ModRM:r/m (r)

N/A

Full

ModRM:reg (w)

ModRM:r/m (r)

N/A

Description

Converts four, eight or sixteen packed signed doubleword integers in the source operand to four, eight or sixteen

packed single precision floating-point values in the destination operand.

EVEX encoded versions: The source operand can be a ZMM/YMM/XMM register, a 512/256/128-bit memory location

or a 512/256/128-bit vector broadcasted from a 32-bit memory location. The destination operand is a

ZMM/YMM/XMM register conditionally updated with writemask k1.

VEX.256 encoded version: The source operand is a YMM register or 256- bit memory location. The destination

operand is a YMM register. Bits (MAXVL-1:256) of the corresponding register destination are zeroed.

VEX.128 encoded version: The source operand is an XMM register or 128- bit memory location. The destination

operand is a XMM register. The upper bits (MAXVL-1:128) of the corresponding register destination are zeroed.

128-bit Legacy SSE version: The source operand is an XMM register or 128- bit memory location. The destination

operand is an XMM register. The upper Bits (MAXVL-1:128) of the corresponding register destination are unmodi-

fied.

VEX.vvvv and EVEX.vvvv are reserved and must be 1111b, otherwise instructions will #UD.

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CVTDQ2PS—Convert Packed Doubleword Integers to Packed Single Precision Floating-Point Values

INSTRUCTION SET REFERENCE, A-L

Operation

VCVTDQ2PS (EVEX encoded versions) when SRC operand is a register

(KL, VL) = (4, 128), (8, 256), (16, 512)

IF (VL = 512) AND (EVEX.b = 1)

THEN

SET_ROUNDING_MODE_FOR_THIS_INSTRUCTION(EVEX.RC); ; refer to Table 15-4 in the Intel® 64 and IA-32 Architectures

Software Developer’s Manual, Volume 1

ELSE

SET_ROUNDING_MODE_FOR_THIS_INSTRUCTION(MXCSR.RC); ; refer to Table 15-4 in the Intel® 64 and IA-32 Architectures

Software Developer’s Manual, Volume 1

FI;

FOR j := 0 TO KL-1

i := j * 32

IF k1[j] OR *no writemask*

THEN DEST[i+31:i] :=

Convert_Integer_To_Single_Precision_Floating_Point(SRC[i+31:i])

ELSE

IF *merging-masking*

; merging-masking

THEN *DEST[i+31:i] remains unchanged*

ELSE

; zeroing-masking

DEST[i+31:i] := 0

FI;

ENDFOR

DEST[MAXVL-1:VL] := 0

VCVTDQ2PS (EVEX encoded versions) when SRC operand is a memory source

(KL, VL) = (4, 128), (8, 256), (16, 512)

FOR j := 0 TO KL-1

i := j * 32

IF k1[j] OR *no writemask*

THEN

IF (EVEX.b = 1)

THEN

DEST[i+31:i] :=

Convert_Integer_To_Single_Precision_Floating_Point(SRC[31:0])

ELSE

DEST[i+31:i] :=

Convert_Integer_To_Single_Precision_Floating_Point(SRC[i+31:i])

FI;

ELSE

IF *merging-masking*

; merging-masking

THEN *DEST[i+31:i] remains unchanged*

ELSE

; zeroing-masking

DEST[i+31:i] := 0

FI;

ENDFOR

DEST[MAXVL-1:VL] := 0

CVTDQ2PS—Convert Packed Doubleword Integers to Packed Single Precision Floating-Point Values

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3-269

INSTRUCTION SET REFERENCE, A-L

VCVTDQ2PS (VEX.256 encoded version)

DEST[31:0] := Convert_Integer_To_Single_Precision_Floating_Point(SRC[31:0])

DEST[63:32] := Convert_Integer_To_Single_Precision_Floating_Point(SRC[63:32])

DEST[95:64] := Convert_Integer_To_Single_Precision_Floating_Point(SRC[95:64])

DEST[127:96] := Convert_Integer_To_Single_Precision_Floating_Point(SRC[127:96)

DEST[159:128] := Convert_Integer_To_Single_Precision_Floating_Point(SRC[159:128])

DEST[191:160] := Convert_Integer_To_Single_Precision_Floating_Point(SRC[191:160])

DEST[223:192] := Convert_Integer_To_Single_Precision_Floating_Point(SRC[223:192])

DEST[255:224] := Convert_Integer_To_Single_Precision_Floating_Point(SRC[255:224)

DEST[MAXVL-1:256] := 0

VCVTDQ2PS (VEX.128 encoded version)

DEST[31:0] := Convert_Integer_To_Single_Precision_Floating_Point(SRC[31:0])

DEST[63:32] := Convert_Integer_To_Single_Precision_Floating_Point(SRC[63:32])

DEST[95:64] := Convert_Integer_To_Single_Precision_Floating_Point(SRC[95:64])

DEST[127:96] := Convert_Integer_To_Single_Precision_Floating_Point(SRC[127z:96)

DEST[MAXVL-1:128] := 0

CVTDQ2PS (128-bit Legacy SSE version)

DEST[31:0] := Convert_Integer_To_Single_Precision_Floating_Point(SRC[31:0])

DEST[63:32] := Convert_Integer_To_Single_Precision_Floating_Point(SRC[63:32])

DEST[95:64] := Convert_Integer_To_Single_Precision_Floating_Point(SRC[95:64])

DEST[127:96] := Convert_Integer_To_Single_Precision_Floating_Point(SRC[127z:96)

DEST[MAXVL-1:128] (unmodified)

Intel C/C++ Compiler Intrinsic Equivalent

VCVTDQ2PS __m512 _mm512_cvtepi32_ps( __m512i a);

VCVTDQ2PS __m512 _mm512_mask_cvtepi32_ps( __m512 s, __mmask16 k, __m512i a);

VCVTDQ2PS __m512 _mm512_maskz_cvtepi32_ps( __mmask16 k, __m512i a);

VCVTDQ2PS __m512 _mm512_cvt_roundepi32_ps( __m512i a, int r);

VCVTDQ2PS __m512 _mm512_mask_cvt_roundepi_ps( __m512 s, __mmask16 k, __m512i a, int r);

VCVTDQ2PS __m512 _mm512_maskz_cvt_roundepi32_ps( __mmask16 k, __m512i a, int r);

VCVTDQ2PS __m256 _mm256_mask_cvtepi32_ps( __m256 s, __mmask8 k, __m256i a);

VCVTDQ2PS __m256 _mm256_maskz_cvtepi32_ps( __mmask8 k, __m256i a);

VCVTDQ2PS __m128 _mm_mask_cvtepi32_ps( __m128 s, __mmask8 k, __m128i a);

VCVTDQ2PS __m128 _mm_maskz_cvtepi32_ps( __mmask8 k, __m128i a);

CVTDQ2PS __m256 _mm256_cvtepi32_ps (__m256i src)

CVTDQ2PS __m128 _mm_cvtepi32_ps (__m128i src)

SIMD Floating-Point Exceptions

Precision

Other Exceptions

VEX-encoded instructions, see Table 2-19, “Type 2 Class Exception Conditions”.

EVEX-encoded instructions, see Table 2-46, “Type E2 Class Exception Conditions”.

Additionally:

#UD

If VEX.vvvv != 1111B or EVEX.vvvv != 1111B.

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INSTRUCTION SET REFERENCE, A-L

CVTPD2DQ—Convert Packed Double Precision Floating-Point Values to Packed Doubleword

Integers

Opcode

Op /

64/32

CPUID

Description

Instruction

bit Mode

Feature

Support

Flag

F2 0F E6 /r

V/V

SSE2

Convert two packed double precision floating-point

CVTPD2DQ xmm1, xmm2/m128

values in xmm2/mem to two signed doubleword

integers in xmm1.

VEX.128.F2.0F.WIG E6 /r

V/V

AVX

Convert two packed double precision floating-point

VCVTPD2DQ xmm1, xmm2/m128

values in xmm2/mem to two signed doubleword

integers in xmm1.

VEX.256.F2.0F.WIG E6 /r

V/V

AVX

Convert four packed double precision floating-point

VCVTPD2DQ xmm1, ymm2/m256

values in ymm2/mem to four signed doubleword

integers in xmm1.

EVEX.128.F2.0F.W1 E6 /r

V/V

AVX512VL

Convert two packed double precision floating-point

VCVTPD2DQ xmm1 {k1}{z},

AVX512F

values in xmm2/m128/m64bcst to two signed

xmm2/m128/m64bcst

doubleword integers in xmm1 subject to writemask k1.

EVEX.256.F2.0F.W1 E6 /r

V/V

AVX512VL

Convert four packed double precision floating-point

VCVTPD2DQ xmm1 {k1}{z},

AVX512F

values in ymm2/m256/m64bcst to four signed

ymm2/m256/m64bcst

doubleword integers in xmm1 subject to writemask k1.

EVEX.512.F2.0F.W1 E6 /r

V/V

AVX512F

Convert eight packed double precision floating-point

VCVTPD2DQ ymm1 {k1}{z},

values in zmm2/m512/m64bcst to eight signed

zmm2/m512/m64bcst{er}

doubleword integers in ymm1 subject to writemask k1.

Instruction Operand Encoding

Op/En

Tuple Type

Operand 1

Operand 2

Operand 3

Operand 4

N/A

ModRM:reg (w)

ModRM:r/m (r)

N/A

Full

ModRM:reg (w)

ModRM:r/m (r)

N/A

Description

Converts packed double precision floating-point values in the source operand (second operand) to packed signed

doubleword integers in the destination operand (first operand).

When a conversion is inexact, the value returned is rounded according to the rounding control bits in the MXCSR

format, the floating-point invalid exception is raised, and if this exception is masked, the indefinite integer value

(2^w-1, where w represents the number of bits in the destination format) is returned.

EVEX encoded versions: The source operand is a ZMM/YMM/XMM register, a 512-bit memory location, or a 512-bit

vector broadcasted from a 64-bit memory location. The destination operand is a ZMM/YMM/XMM register condi-

tionally updated with writemask k1. The upper bits (MAXVL-1:256/128/64) of the corresponding destination are

zeroed.

VEX.256 encoded version: The source operand is a YMM register or 256- bit memory location. The destination

operand is an XMM register. The upper bits (MAXVL-1:128) of the corresponding ZMM register destination are

zeroed.

VEX.128 encoded version: The source operand is an XMM register or 128- bit memory location. The destination

operand is a XMM register. The upper bits (MAXVL-1:64) of the corresponding ZMM register destination are zeroed.

128-bit Legacy SSE version: The source operand is an XMM register or 128- bit memory location. The destination

operand is an XMM register. Bits[127:64] of the destination XMM register are zeroed. However, the upper bits

(MAXVL-1:128) of the corresponding ZMM register destination are unmodified.

VEX.vvvv and EVEX.vvvv are reserved and must be 1111b, otherwise instructions will #UD.

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INSTRUCTION SET REFERENCE, A-L

SRC

DEST

Figure 3-12. VCVTPD2DQ (VEX.256 encoded version)

Operation

VCVTPD2DQ (EVEX encoded versions) when src operand is a register

(KL, VL) = (2, 128), (4, 256), (8, 512)

IF (VL = 512) AND (EVEX.b = 1)

THEN

SET_ROUNDING_MODE_FOR_THIS_INSTRUCTION(EVEX.RC);

ELSE

SET_ROUNDING_MODE_FOR_THIS_INSTRUCTION(MXCSR.RC);

FI;

FOR j := 0 TO KL-1

i := j * 32

k := j * 64

IF k1[j] OR *no writemask*

THEN DEST[i+31:i] :=

Convert_Double_Precision_Floating_Point_To_Integer(SRC[k+63:k])

ELSE

IF *merging-masking*

; merging-masking

THEN *DEST[i+31:i] remains unchanged*

ELSE

; zeroing-masking

DEST[i+31:i] := 0

FI;

ENDFOR

DEST[MAXVL-1:VL/2] := 0

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INSTRUCTION SET REFERENCE, A-L

VCVTPD2DQ (EVEX encoded versions) when src operand is a memory source

(KL, VL) = (2, 128), (4, 256), (8, 512)

FOR j := 0 TO KL-1

i := j * 32

k := j * 64

IF k1[j] OR *no writemask*

THEN

IF (EVEX.b = 1)

THEN

DEST[i+31:i] :=

Convert_Double_Precision_Floating_Point_To_Integer(SRC[63:0])

ELSE

DEST[i+31:i] :=

Convert_Double_Precision_Floating_Point_To_Integer(SRC[k+63:k])

FI;

ELSE

IF *merging-masking*

; merging-masking

THEN *DEST[i+31:i] remains unchanged*

ELSE

; zeroing-masking

DEST[i+31:i] := 0

FI;

ENDFOR

DEST[MAXVL-1:VL/2] := 0

VCVTPD2DQ (VEX.256 encoded version)

DEST[31:0] := Convert_Double_Precision_Floating_Point_To_Integer(SRC[63:0])

DEST[63:32] := Convert_Double_Precision_Floating_Point_To_Integer(SRC[127:64])

DEST[95:64] := Convert_Double_Precision_Floating_Point_To_Integer(SRC[191:128])

DEST[127:96] := Convert_Double_Precision_Floating_Point_To_Integer(SRC[255:192)

DEST[MAXVL-1:128] := 0

VCVTPD2DQ (VEX.128 encoded version)

DEST[31:0] := Convert_Double_Precision_Floating_Point_To_Integer(SRC[63:0])

DEST[63:32] := Convert_Double_Precision_Floating_Point_To_Integer(SRC[127:64])

DEST[MAXVL-1:64] := 0

CVTPD2DQ (128-bit Legacy SSE version)

DEST[31:0] := Convert_Double_Precision_Floating_Point_To_Integer(SRC[63:0])

DEST[63:32] := Convert_Double_Precision_Floating_Point_To_Integer(SRC[127:64])

DEST[127:64] := 0

DEST[MAXVL-1:128] (unmodified)

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INSTRUCTION SET REFERENCE, A-L

Intel C/C++ Compiler Intrinsic Equivalent

VCVTPD2DQ __m256i _mm512_cvtpd_epi32( __m512d a);

VCVTPD2DQ __m256i _mm512_mask_cvtpd_epi32( __m256i s, __mmask8 k, __m512d a);

VCVTPD2DQ __m256i _mm512_maskz_cvtpd_epi32( __mmask8 k, __m512d a);

VCVTPD2DQ __m256i _mm512_cvt_roundpd_epi32( __m512d a, int r);

VCVTPD2DQ __m256i _mm512_mask_cvt_roundpd_epi32( __m256i s, __mmask8 k, __m512d a, int r);

VCVTPD2DQ __m256i _mm512_maskz_cvt_roundpd_epi32( __mmask8 k, __m512d a, int r);

VCVTPD2DQ __m128i _mm256_mask_cvtpd_epi32( __m128i s, __mmask8 k, __m256d a);

VCVTPD2DQ __m128i _mm256_maskz_cvtpd_epi32( __mmask8 k, __m256d a);

VCVTPD2DQ __m128i _mm_mask_cvtpd_epi32( __m128i s, __mmask8 k, __m128d a);

VCVTPD2DQ __m128i _mm_maskz_cvtpd_epi32( __mmask8 k, __m128d a);

VCVTPD2DQ __m128i _mm256_cvtpd_epi32 (__m256d src)

CVTPD2DQ __m128i _mm_cvtpd_epi32 (__m128d src)

SIMD Floating-Point Exceptions

Invalid, Precision

Other Exceptions

See Table 2-19, “Type 2 Class Exception Conditions”.

EVEX-encoded instructions, see Table 2-46, “Type E2 Class Exception Conditions”.

Additionally:

#UD

If VEX.vvvv != 1111B or EVEX.vvvv != 1111B.

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INSTRUCTION SET REFERENCE, A-L

CVTPD2PI—Convert Packed Double Precision Floating-Point Values to Packed Dword Integers

Opcode/

Op/

64/32 bit

CPUID

Description

Instruction

Mode

Feature

Support

Flag

66 0F 2D /r

V/V

SSE2

Convert two packed double precision floating-

point values from xmm/m128 to two packed

CVTPD2PI mm, xmm/m128

signed doubleword integers in mm.

Instruction Operand Encoding

Op/En

Operand 1

Operand 2

Operand 3

Operand 4

ModRM:reg (w)

ModRM:r/m (r)

N/A

Description

Converts two packed double precision floating-point values in the source operand (second operand) to two packed

signed doubleword integers in the destination operand (first operand).

The source operand can be an XMM register or a 128-bit memory location. The destination operand is an MMX tech-

nology register.

When a conversion is inexact, the value returned is rounded according to the rounding control bits in the MXCSR

exception is raised, and if this exception is masked, the indefinite integer value (80000000H) is returned.

This instruction causes a transition from x87 FPU to MMX technology operation (that is, the x87 FPU top-of-stack

pointer is set to 0 and the x87 FPU tag word is set to all 0s [valid]). If this instruction is executed while an x87 FPU

floating-point exception is pending, the exception is handled before the CVTPD2PI instruction is executed.

In 64-bit mode, use of the REX.R prefix permits this instruction to access additional registers (XMM8-XMM15).

Operation

DEST[31:0] := Convert_Double_Precision_Floating_Point_To_Integer32(SRC[63:0]);

DEST[63:32] := Convert_Double_Precision_Floating_Point_To_Integer32(SRC[127:64]);

Intel C/C++ Compiler Intrinsic Equivalent

CVTPD1PI:

__m64 _mm_cvtpd_pi32(__m128d a)

SIMD Floating-Point Exceptions

Invalid, Precision.

Other Exceptions

See Table 23-4, “Exception Conditions for Legacy SIMD/MMX Instructions with FP Exception and 16-Byte Align-

ment” in the Intel® 64 and IA-32 Architectures Software Developer’s Manual, Volume 3B.

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INSTRUCTION SET REFERENCE, A-L

CVTPD2PS—Convert Packed Double Precision Floating-Point Values to Packed Single Precision

Floating-Point Values

Opcode/

Op /

64/32

CPUID

Description

Instruction

bit Mode

Feature

Support

Flag

66 0F 5A /r

V/V

SSE2

Convert two packed double precision floating-point

CVTPD2PS xmm1, xmm2/m128

values in xmm2/mem to two single precision

floating-point values in xmm1.

VEX.128.66.0F.WIG 5A /r

V/V

AVX

Convert two packed double precision floating-point

VCVTPD2PS xmm1, xmm2/m128

values in xmm2/mem to two single precision

floating-point values in xmm1.

VEX.256.66.0F.WIG 5A /r

V/V

AVX

Convert four packed double precision floating-point

VCVTPD2PS xmm1, ymm2/m256

values in ymm2/mem to four single precision

floating-point values in xmm1.

EVEX.128.66.0F.W1 5A /r

V/V

AVX512VL

Convert two packed double precision floating-point

VCVTPD2PS xmm1 {k1}{z},

AVX512F

values in xmm2/m128/m64bcst to two single

xmm2/m128/m64bcst

precision floating-point values in xmm1with

writemask k1.

EVEX.256.66.0F.W1 5A /r

V/V

AVX512VL

Convert four packed double precision floating-point

VCVTPD2PS xmm1 {k1}{z},

AVX512F

values in ymm2/m256/m64bcst to four single

ymm2/m256/m64bcst

precision floating-point values in xmm1with

writemask k1.

EVEX.512.66.0F.W1 5A /r

V/V

AVX512F

Convert eight packed double precision floating-point

VCVTPD2PS ymm1 {k1}{z},

values in zmm2/m512/m64bcst to eight single

zmm2/m512/m64bcst{er}

precision floating-point values in ymm1with

writemask k1.

Instruction Operand Encoding

Op/En

Tuple Type

Operand 1

Operand 2

Operand 3

Operand 4

N/A

ModRM:reg (w)

ModRM:r/m (r)

N/A

Full

ModRM:reg (w)

ModRM:r/m (r)

N/A

Description

Converts two, four or eight packed double precision floating-point values in the source operand (second operand)

to two, four or eight packed single precision floating-point values in the destination operand (first operand).

When a conversion is inexact, the value returned is rounded according to the rounding control bits in the MXCSR

EVEX encoded versions: The source operand is a ZMM/YMM/XMM register, a 512/256/128-bit memory location, or

a 512/256/128-bit vector broadcasted from a 64-bit memory location. The destination operand is a

YMM/XMM/XMM (low 64-bits) register conditionally updated with writemask k1. The upper bits (MAXVL-

1:256/128/64) of the corresponding destination are zeroed.

VEX.256 encoded version: The source operand is a YMM register or 256- bit memory location. The destination

operand is an XMM register. The upper bits (MAXVL-1:128) of the corresponding ZMM register destination are

zeroed.

VEX.128 encoded version: The source operand is an XMM register or 128- bit memory location. The destination

operand is a XMM register. The upper bits (MAXVL-1:64) of the corresponding ZMM register destination are zeroed.

128-bit Legacy SSE version: The source operand is an XMM register or 128- bit memory location. The destination

operand is an XMM register. Bits[127:64] of the destination XMM register are zeroed. However, the upper Bits

(MAXVL-1:128) of the corresponding ZMM register destination are unmodified.

VEX.vvvv and EVEX.vvvv are reserved and must be 1111b otherwise instructions will #UD.

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INSTRUCTION SET REFERENCE, A-L

SRC

DEST

Figure 3-13. VCVTPD2PS (VEX.256 encoded version)

Operation

VCVTPD2PS (EVEX encoded version) when src operand is a register

(KL, VL) = (2, 128), (4, 256), (8, 512)

IF (VL = 512) AND (EVEX.b = 1)

THEN

SET_ROUNDING_MODE_FOR_THIS_INSTRUCTION(EVEX.RC);

ELSE

SET_ROUNDING_MODE_FOR_THIS_INSTRUCTION(MXCSR.RC);

FI;

FOR j := 0 TO KL-1

i := j * 32

k := j * 64

IF k1[j] OR *no writemask*

THEN

DEST[i+31:i] := Convert_Double_Precision_Floating_Point_To_Single_Precision_Floating_Point(SRC[k+63:k])

ELSE

IF *merging-masking*

; merging-masking

THEN *DEST[i+31:i] remains unchanged*

ELSE

; zeroing-masking

DEST[i+31:i] := 0

FI;

ENDFOR

DEST[MAXVL-1:VL/2] := 0

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INSTRUCTION SET REFERENCE, A-L

VCVTPD2PS (EVEX encoded version) when src operand is a memory source

(KL, VL) = (2, 128), (4, 256), (8, 512)

FOR j := 0 TO KL-1

i := j * 32

k := j * 64

IF k1[j] OR *no writemask*

THEN

IF (EVEX.b = 1)

THEN

DEST[i+31:i] :=Convert_Double_Precision_Floating_Point_To_Single_Precision_Floating_Point(SRC[63:0])

ELSE

DEST[i+31:i] := Convert_Double_Precision_Floating_Point_To_Single_Precision_Floating_Point(SRC[k+63:k])

FI;

ELSE

IF *merging-masking*

; merging-masking

THEN *DEST[i+31:i] remains unchanged*

ELSE

; zeroing-masking

DEST[i+31:i] := 0

FI;

ENDFOR

DEST[MAXVL-1:VL/2] := 0

VCVTPD2PS (VEX.256 encoded version)

DEST[31:0] := Convert_Double_Precision_To_Single_Precision_Floating_Point(SRC[63:0])

DEST[63:32] := Convert_Double_Precision_To_Single_Precision_Floating_Point(SRC[127:64])

DEST[95:64] := Convert_Double_Precision_To_Single_Precision_Floating_Point(SRC[191:128])

DEST[127:96] := Convert_Double_Precision_To_Single_Precision_Floating_Point(SRC[255:192)

DEST[MAXVL-1:128] := 0

VCVTPD2PS (VEX.128 encoded version)

DEST[31:0] := Convert_Double_Precision_To_Single_Precision_Floating_Point(SRC[63:0])

DEST[63:32] := Convert_Double_Precision_To_Single_Precision_Floating_Point(SRC[127:64])

DEST[MAXVL-1:64] := 0

CVTPD2PS (128-bit Legacy SSE version)

DEST[31:0] := Convert_Double_Precision_To_Single_Precision_Floating_Point(SRC[63:0])

DEST[63:32] := Convert_Double_Precision_To_Single_Precision_Floating_Point(SRC[127:64])

DEST[127:64] := 0

DEST[MAXVL-1:128] (unmodified)

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INSTRUCTION SET REFERENCE, A-L

Intel C/C++ Compiler Intrinsic Equivalent

VCVTPD2PS __m256 _mm512_cvtpd_ps( __m512d a);

VCVTPD2PS __m256 _mm512_mask_cvtpd_ps( __m256 s, __mmask8 k, __m512d a);

VCVTPD2PS __m256 _mm512_maskz_cvtpd_ps( __mmask8 k, __m512d a);

VCVTPD2PS __m256 _mm512_cvt_roundpd_ps( __m512d a, int r);

VCVTPD2PS __m256 _mm512_mask_cvt_roundpd_ps( __m256 s, __mmask8 k, __m512d a, int r);

VCVTPD2PS __m256 _mm512_maskz_cvt_roundpd_ps( __mmask8 k, __m512d a, int r);

VCVTPD2PS __m128 _mm256_mask_cvtpd_ps( __m128 s, __mmask8 k, __m256d a);

VCVTPD2PS __m128 _mm256_maskz_cvtpd_ps( __mmask8 k, __m256d a);

VCVTPD2PS __m128 _mm_mask_cvtpd_ps( __m128 s, __mmask8 k, __m128d a);

VCVTPD2PS __m128 _mm_maskz_cvtpd_ps( __mmask8 k, __m128d a);

VCVTPD2PS __m128 _mm256_cvtpd_ps (__m256d a)

CVTPD2PS __m128 _mm_cvtpd_ps (__m128d a)

SIMD Floating-Point Exceptions

Invalid, Precision, Underflow, Overflow, Denormal

Other Exceptions

VEX-encoded instructions, see Table 2-19, “Type 2 Class Exception Conditions”.

EVEX-encoded instructions, see Table 2-46, “Type E2 Class Exception Conditions”.

Additionally:

#UD

If VEX.vvvv != 1111B or EVEX.vvvv != 1111B.

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INSTRUCTION SET REFERENCE, A-L

CVTPI2PD—Convert Packed Dword Integers to Packed Double Precision Floating-Point Values

Opcode/

Op/

64-Bit

Compat/

Description

Instruction

Mode

Leg Mode

66 0F 2A /r

Valid

Convert two packed signed doubleword

integers from mm/mem64 to two packed

CVTPI2PD xmm, mm/m64¹

double precision floating-point values in xmm.

NOTES:

1. Operation is different for different operand sets; see the Description section.

Instruction Operand Encoding

Op/En

Operand 1

Operand 2

Operand 3

Operand 4

ModRM:reg (w)

ModRM:r/m (r)

N/A

Description

Converts two packed signed doubleword integers in the source operand (second operand) to two packed double

precision floating-point values in the destination operand (first operand).

The source operand can be an MMX technology register or a 64-bit memory location. The destination operand is an

XMM register. In addition, depending on the operand configuration:

• For operands xmm, mm: the instruction causes a transition from x87 FPU to MMX technology operation (that

is, the x87 FPU top-of-stack pointer is set to 0 and the x87 FPU tag word is set to all 0s [valid]). If this

instruction is executed while an x87 FPU floating-point exception is pending, the exception is handled before

the CVTPI2PD instruction is executed.

• For operands xmm, m64: the instruction does not cause a transition to MMX technology and does not take

x87 FPU exceptions.

In 64-bit mode, use of the REX.R prefix permits this instruction to access additional registers (XMM8-XMM15).

Operation

DEST[63:0] := Convert_Integer_To_Double_Precision_Floating_Point(SRC[31:0]);

DEST[127:64] := Convert_Integer_To_Double_Precision_Floating_Point(SRC[63:32]);

Intel C/C++ Compiler Intrinsic Equivalent

CVTPI2PD:

__m128d _mm_cvtpi32_pd(__m64 a)

SIMD Floating-Point Exceptions

None

Other Exceptions

See Table 23-6, “Exception Conditions for Legacy SIMD/MMX Instructions with XMM and without FP Exception” in

the Intel® 64 and IA-32 Architectures Software Developer’s Manual, Volume 3B.

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INSTRUCTION SET REFERENCE, A-L

CVTPI2PS—Convert Packed Dword Integers to Packed Single Precision Floating-Point Values

Opcode/

Op/

64-Bit

Compat/

Description

Instruction

Mode

Leg Mode

NP 0F 2A /r

Valid

Convert two signed doubleword integers

from mm/m64 to two single precision

CVTPI2PS xmm, mm/m64

floating-point values in xmm.

Instruction Operand Encoding

Op/En

Operand 1

Operand 2

Operand 3

Operand 4

ModRM:reg (r, w)

ModRM:r/m (r)

N/A

Description

Converts two packed signed doubleword integers in the source operand (second operand) to two packed single

precision floating-point values in the destination operand (first operand).

The source operand can be an MMX technology register or a 64-bit memory location. The destination operand is an

XMM register. The results are stored in the low quadword of the destination operand, and the high quadword

remains unchanged. When a conversion is inexact, the value returned is rounded according to the rounding control

bits in the MXCSR register.

This instruction causes a transition from x87 FPU to MMX technology operation (that is, the x87 FPU top-of-stack

pointer is set to 0 and the x87 FPU tag word is set to all 0s [valid]). If this instruction is executed while an x87 FPU

floating-point exception is pending, the exception is handled before the CVTPI2PS instruction is executed.

In 64-bit mode, use of the REX.R prefix permits this instruction to access additional registers (XMM8-XMM15).

Operation

DEST[31:0] := Convert_Integer_To_Single_Precision_Floating_Point(SRC[31:0]);

DEST[63:32] := Convert_Integer_To_Single_Precision_Floating_Point(SRC[63:32]);

(* High quadword of destination unchanged *)

Intel C/C++ Compiler Intrinsic Equivalent

CVTPI2PS:

__m128 _mm_cvtpi32_ps(__m128 a, __m64 b)

SIMD Floating-Point Exceptions

Precision

Other Exceptions

See Table 23-5, “Exception Conditions for Legacy SIMD/MMX Instructions with XMM and FP Exception” in the

Intel® 64 and IA-32 Architectures Software Developer’s Manual, Volume 3B.

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INSTRUCTION SET REFERENCE, A-L

CVTPS2DQ—Convert Packed Single Precision Floating-Point Values to Packed Signed

Doubleword Integer Values

Opcode/

Op /

64/32

CPUID

Description

Instruction

bit Mode

Feature

Support

Flag

66 0F 5B /r

V/V

SSE2

Convert four packed single precision floating-point values

CVTPS2DQ xmm1, xmm2/m128

from xmm2/mem to four packed signed doubleword

values in xmm1.

VEX.128.66.0F.WIG 5B /r

V/V

AVX

Convert four packed single precision floating-point values

VCVTPS2DQ xmm1, xmm2/m128

from xmm2/mem to four packed signed doubleword

values in xmm1.

VEX.256.66.0F.WIG 5B /r

V/V

AVX

Convert eight packed single precision floating-point values

VCVTPS2DQ ymm1, ymm2/m256

from ymm2/mem to eight packed signed doubleword

values in ymm1.

EVEX.128.66.0F.W0 5B /r

V/V

AVX512VL

Convert four packed single precision floating-point values

VCVTPS2DQ xmm1 {k1}{z},

AVX512F

from xmm2/m128/m32bcst to four packed signed

xmm2/m128/m32bcst

doubleword values in xmm1 subject to writemask k1.

EVEX.256.66.0F.W0 5B /r

V/V

AVX512VL

Convert eight packed single precision floating-point values

VCVTPS2DQ ymm1 {k1}{z},

AVX512F

from ymm2/m256/m32bcst to eight packed signed

ymm2/m256/m32bcst

doubleword values in ymm1 subject to writemask k1.

EVEX.512.66.0F.W0 5B /r

V/V

AVX512F

Convert sixteen packed single precision floating-point

VCVTPS2DQ zmm1 {k1}{z},

values from zmm2/m512/m32bcst to sixteen packed

zmm2/m512/m32bcst{er}

signed doubleword values in zmm1 subject to writemask

k1.

Instruction Operand Encoding

Op/En

Tuple Type

Operand 1

Operand 2

Operand 3

Operand 4

N/A

ModRM:reg (w)

ModRM:r/m (r)

N/A

Full

ModRM:reg (w)

ModRM:r/m (r)

N/A

Description

Converts four, eight or sixteen packed single precision floating-point values in the source operand to four, eight or

sixteen signed doubleword integers in the destination operand.

When a conversion is inexact, the value returned is rounded according to the rounding control bits in the MXCSR

format, the floating-point invalid exception is raised, and if this exception is masked, the indefinite integer value

(2^w-1, where w represents the number of bits in the destination format) is returned.

EVEX encoded versions: The source operand is a ZMM register, a 512-bit memory location or a 512-bit vector

broadcasted from a 32-bit memory location. The destination operand is a ZMM register conditionally updated with

writemask k1.

VEX.256 encoded version: The source operand is a YMM register or 256- bit memory location. The destination

operand is a YMM register. The upper bits (MAXVL-1:256) of the corresponding ZMM register destination are

zeroed.

VEX.128 encoded version: The source operand is an XMM register or 128- bit memory location. The destination

operand is a XMM register. The upper bits (MAXVL-1:128) of the corresponding ZMM register destination are

zeroed.

128-bit Legacy SSE version: The source operand is an XMM register or 128- bit memory location. The destination

operand is an XMM register. The upper bits (MAXVL-1:128) of the corresponding ZMM register destination are

unmodified.

VEX.vvvv and EVEX.vvvv are reserved and must be 1111b otherwise instructions will #UD.

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INSTRUCTION SET REFERENCE, A-L

Operation

VCVTPS2DQ (encoded versions) when src operand is a register

(KL, VL) = (4, 128), (8, 256), (16, 512)

IF (VL = 512) AND (EVEX.b = 1)

THEN

SET_ROUNDING_MODE_FOR_THIS_INSTRUCTION(EVEX.RC);

ELSE

SET_ROUNDING_MODE_FOR_THIS_INSTRUCTION(MXCSR.RC);

FI;

FOR j := 0 TO KL-1

i := j * 32

IF k1[j] OR *no writemask*

THEN DEST[i+31:i] :=

Convert_Single_Precision_Floating_Point_To_Integer(SRC[i+31:i])

ELSE

IF *merging-masking*

; merging-masking

THEN *DEST[i+31:i] remains unchanged*

ELSE

; zeroing-masking

DEST[i+31:i] := 0

FI;

ENDFOR

DEST[MAXVL-1:VL] := 0

VCVTPS2DQ (EVEX encoded versions) when src operand is a memory source

(KL, VL) = (4, 128), (8, 256), (16, 512)

FOR j := 0 TO 15

i := j * 32

IF k1[j] OR *no writemask*

THEN

IF (EVEX.b = 1)

THEN

DEST[i+31:i] :=

Convert_Single_Precision_Floating_Point_To_Integer(SRC[31:0])

ELSE

DEST[i+31:i] :=

Convert_Single_Precision_Floating_Point_To_Integer(SRC[i+31:i])

FI;

ELSE

IF *merging-masking*

; merging-masking

THEN *DEST[i+31:i] remains unchanged*

ELSE

; zeroing-masking

DEST[i+31:i] := 0

FI;

ENDFOR

DEST[MAXVL-1:VL] := 0

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INSTRUCTION SET REFERENCE, A-L

VCVTPS2DQ (VEX.256 encoded version)

DEST[31:0] := Convert_Single_Precision_Floating_Point_To_Integer(SRC[31:0])

DEST[63:32] := Convert_Single_Precision_Floating_Point_To_Integer(SRC[63:32])

DEST[95:64] := Convert_Single_Precision_Floating_Point_To_Integer(SRC[95:64])

DEST[127:96] := Convert_Single_Precision_Floating_Point_To_Integer(SRC[127:96)

DEST[159:128] := Convert_Single_Precision_Floating_Point_To_Integer(SRC[159:128])

DEST[191:160] := Convert_Single_Precision_Floating_Point_To_Integer(SRC[191:160])

DEST[223:192] := Convert_Single_Precision_Floating_Point_To_Integer(SRC[223:192])

DEST[255:224] := Convert_Single_Precision_Floating_Point_To_Integer(SRC[255:224])

VCVTPS2DQ (VEX.128 encoded version)

DEST[31:0] := Convert_Single_Precision_Floating_Point_To_Integer(SRC[31:0])

DEST[63:32] := Convert_Single_Precision_Floating_Point_To_Integer(SRC[63:32])

DEST[95:64] := Convert_Single_Precision_Floating_Point_To_Integer(SRC[95:64])

DEST[127:96] := Convert_Single_Precision_Floating_Point_To_Integer(SRC[127:96])

DEST[MAXVL-1:128] := 0

CVTPS2DQ (128-bit Legacy SSE version)

DEST[31:0] := Convert_Single_Precision_Floating_Point_To_Integer(SRC[31:0])

DEST[63:32] := Convert_Single_Precision_Floating_Point_To_Integer(SRC[63:32])

DEST[95:64] := Convert_Single_Precision_Floating_Point_To_Integer(SRC[95:64])

DEST[127:96] := Convert_Single_Precision_Floating_Point_To_Integer(SRC[127:96])

DEST[MAXVL-1:128] (unmodified)

Intel C/C++ Compiler Intrinsic Equivalent

VCVTPS2DQ __m512i _mm512_cvtps_epi32( __m512 a);

VCVTPS2DQ __m512i _mm512_mask_cvtps_epi32( __m512i s, __mmask16 k, __m512 a);

VCVTPS2DQ __m512i _mm512_maskz_cvtps_epi32( __mmask16 k, __m512 a);

VCVTPS2DQ __m512i _mm512_cvt_roundps_epi32( __m512 a, int r);

VCVTPS2DQ __m512i _mm512_mask_cvt_roundps_epi32( __m512i s, __mmask16 k, __m512 a, int r);

VCVTPS2DQ __m512i _mm512_maskz_cvt_roundps_epi32( __mmask16 k, __m512 a, int r);

VCVTPS2DQ __m256i _mm256_mask_cvtps_epi32( __m256i s, __mmask8 k, __m256 a);

VCVTPS2DQ __m256i _mm256_maskz_cvtps_epi32( __mmask8 k, __m256 a);

VCVTPS2DQ __m128i _mm_mask_cvtps_epi32( __m128i s, __mmask8 k, __m128 a);

VCVTPS2DQ __m128i _mm_maskz_cvtps_epi32( __mmask8 k, __m128 a);

VCVTPS2DQ __ m256i _mm256_cvtps_epi32 (__m256 a)

CVTPS2DQ __m128i _mm_cvtps_epi32 (__m128 a)

SIMD Floating-Point Exceptions

Invalid, Precision

Other Exceptions

VEX-encoded instructions, see Table 2-19, “Type 2 Class Exception Conditions”.

EVEX-encoded instructions, see Table 2-46, “Type E2 Class Exception Conditions”.

Additionally:

#UD

If VEX.vvvv != 1111B or EVEX.vvvv != 1111B.

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INSTRUCTION SET REFERENCE, A-L

CVTPS2PD—Convert Packed Single Precision Floating-Point Values to Packed Double Precision

Floating-Point Values

Opcode/

Op /

64/32

CPUID

Description

Instruction

bit Mode

Feature

Support

Flag

NP 0F 5A /r

V/V

SSE2

Convert two packed single precision floating-point values in

CVTPS2PD xmm1, xmm2/m64

xmm2/m64 to two packed double precision floating-point

values in xmm1.

VEX.128.0F.WIG 5A /r

V/V

AVX

Convert two packed single precision floating-point values in

VCVTPS2PD xmm1, xmm2/m64

xmm2/m64 to two packed double precision floating-point

values in xmm1.

VEX.256.0F.WIG 5A /r

V/V

AVX

Convert four packed single precision floating-point values

VCVTPS2PD ymm1, xmm2/m128

in xmm2/m128 to four packed double precision floating-

point values in ymm1.

EVEX.128.0F.W0 5A /r

V/V

AVX512VL

Convert two packed single precision floating-point values in

VCVTPS2PD xmm1 {k1}{z},

AVX512F

xmm2/m64/m32bcst to packed double precision floating-

xmm2/m64/m32bcst

point values in xmm1 with writemask k1.

EVEX.256.0F.W0 5A /r

V/V

AVX512VL

Convert four packed single precision floating-point values

VCVTPS2PD ymm1 {k1}{z},

in xmm2/m128/m32bcst to packed double precision

xmm2/m128/m32bcst

floating-point values in ymm1 with writemask k1.

EVEX.512.0F.W0 5A /r

V/V

AVX512F

Convert eight packed single precision floating-point values

VCVTPS2PD zmm1 {k1}{z},

in ymm2/m256/b32bcst to eight packed double precision

ymm2/m256/m32bcst{sae}

floating-point values in zmm1 with writemask k1.

Instruction Operand Encoding

Op/En

Tuple Type

Operand 1

Operand 2

Operand 3

Operand 4

N/A

ModRM:reg (w)

ModRM:r/m (r)

N/A

Half

ModRM:reg (w)

ModRM:r/m (r)

N/A

Description

Converts two, four or eight packed single precision floating-point values in the source operand (second operand) to

two, four or eight packed double precision floating-point values in the destination operand (first operand).

EVEX encoded versions: The source operand is a YMM/XMM/XMM (low 64-bits) register, a 256/128/64-bit memory

location or a 256/128/64-bit vector broadcasted from a 32-bit memory location. The destination operand is a

ZMM/YMM/XMM register conditionally updated with writemask k1.

VEX.256 encoded version: The source operand is an XMM register or 128- bit memory location. The destination

operand is a YMM register. Bits (MAXVL-1:256) of the corresponding destination ZMM register are zeroed.

VEX.128 encoded version: The source operand is an XMM register or 64- bit memory location. The destination

operand is a XMM register. The upper Bits (MAXVL-1:128) of the corresponding ZMM register destination are

zeroed.

128-bit Legacy SSE version: The source operand is an XMM register or 64- bit memory location. The destination

operand is an XMM register. The upper Bits (MAXVL-1:128) of the corresponding ZMM register destination are

unmodified.

Note: VEX.vvvv and EVEX.vvvv are reserved and must be 1111b otherwise instructions will #UD.

CVTPS2PD—Convert Packed Single Precision Floating-Point Values to Packed Double Precision Floating-Point Values

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INSTRUCTION SET REFERENCE, A-L

SRC

DEST

Figure 3-14. CVTPS2PD (VEX.256 encoded version)

Operation

VCVTPS2PD (EVEX encoded versions) when src operand is a register

(KL, VL) = (2, 128), (4, 256), (8, 512)

FOR j := 0 TO KL-1

i := j * 64

k := j * 32

IF k1[j] OR *no writemask*

THEN DEST[i+63:i] :=

Convert_Single_Precision_To_Double_Precision_Floating_Point(SRC[k+31:k])

ELSE

IF *merging-masking*

; merging-masking

THEN *DEST[i+63:i] remains unchanged*

ELSE

; zeroing-masking

DEST[i+63:i] := 0

FI;

ENDFOR

DEST[MAXVL-1:VL] := 0

VCVTPS2PD (EVEX encoded versions) when src operand is a memory source

(KL, VL) = (2, 128), (4, 256), (8, 512)

FOR j := 0 TO KL-1

i := j * 64

k := j * 32

IF k1[j] OR *no writemask*

THEN

IF (EVEX.b = 1)

THEN

DEST[i+63:i] :=

Convert_Single_Precision_To_Double_Precision_Floating_Point(SRC[31:0])

ELSE

DEST[i+63:i] :=

Convert_Single_Precision_To_Double_Precision_Floating_Point(SRC[k+31:k])

FI;

ELSE

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INSTRUCTION SET REFERENCE, A-L

IF *merging-masking*

; merging-masking

THEN *DEST[i+63:i] remains unchanged*

ELSE

; zeroing-masking

DEST[i+63:i] := 0

FI;

ENDFOR

DEST[MAXVL-1:VL] := 0

VCVTPS2PD (VEX.256 encoded version)

DEST[63:0] := Convert_Single_Precision_To_Double_Precision_Floating_Point(SRC[31:0])

DEST[127:64] := Convert_Single_Precision_To_Double_Precision_Floating_Point(SRC[63:32])

DEST[191:128] := Convert_Single_Precision_To_Double_Precision_Floating_Point(SRC[95:64])

DEST[255:192] := Convert_Single_Precision_To_Double_Precision_Floating_Point(SRC[127:96)

DEST[MAXVL-1:256] := 0

VCVTPS2PD (VEX.128 encoded version)

DEST[63:0] := Convert_Single_Precision_To_Double_Precision_Floating_Point(SRC[31:0])

DEST[127:64] := Convert_Single_Precision_To_Double_Precision_Floating_Point(SRC[63:32])

DEST[MAXVL-1:128] := 0

CVTPS2PD (128-bit Legacy SSE version)

DEST[63:0] := Convert_Single_Precision_To_Double_Precision_Floating_Point(SRC[31:0])

DEST[127:64] := Convert_Single_Precision_To_Double_Precision_Floating_Point(SRC[63:32])

DEST[MAXVL-1:128] (unmodified)

Intel C/C++ Compiler Intrinsic Equivalent

VCVTPS2PD __m512d _mm512_cvtps_pd( __m256 a);

VCVTPS2PD __m512d _mm512_mask_cvtps_pd( __m512d s, __mmask8 k, __m256 a);

VCVTPS2PD __m512d _mm512_maskz_cvtps_pd( __mmask8 k, __m256 a);

VCVTPS2PD __m512d _mm512_cvt_roundps_pd( __m256 a, int sae);

VCVTPS2PD __m512d _mm512_mask_cvt_roundps_pd( __m512d s, __mmask8 k, __m256 a, int sae);

VCVTPS2PD __m512d _mm512_maskz_cvt_roundps_pd( __mmask8 k, __m256 a, int sae);

VCVTPS2PD __m256d _mm256_mask_cvtps_pd( __m256d s, __mmask8 k, __m128 a);

VCVTPS2PD __m256d _mm256_maskz_cvtps_pd( __mmask8 k, __m128a);

VCVTPS2PD __m128d _mm_mask_cvtps_pd( __m128d s, __mmask8 k, __m128 a);

VCVTPS2PD __m128d _mm_maskz_cvtps_pd( __mmask8 k, __m128 a);

VCVTPS2PD __m256d _mm256_cvtps_pd (__m128 a)

CVTPS2PD __m128d _mm_cvtps_pd (__m128 a)

SIMD Floating-Point Exceptions

Invalid, Denormal

Other Exceptions

VEX-encoded instructions, see Table 2-20, “Type 3 Class Exception Conditions”.

EVEX-encoded instructions, see Table 2-47, “Type E3 Class Exception Conditions”.

Additionally:

#UD

If VEX.vvvv != 1111B or EVEX.vvvv != 1111B.

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INSTRUCTION SET REFERENCE, A-L

CVTPS2PI—Convert Packed Single Precision Floating-Point Values to Packed Dword Integers

Opcode/

Op/

64-Bit

Compat/

Description

Instruction

Mode

Leg Mode

NP 0F 2D /r

Valid

Convert two packed single precision floating-

point values from xmm/m64 to two packed

CVTPS2PI mm, xmm/m64

signed doubleword integers in mm.

Instruction Operand Encoding

Op/En

Operand 1

Operand 2

Operand 3

Operand 4

ModRM:reg (w)

ModRM:r/m (r)

N/A

Description

Converts two packed single precision floating-point values in the source operand (second operand) to two packed

signed doubleword integers in the destination operand (first operand).

The source operand can be an XMM register or a 128-bit memory location. The destination operand is an MMX tech-

nology register. When the source operand is an XMM register, the two single precision floating-point values are

contained in the low quadword of the register. When a conversion is inexact, the value returned is rounded

according to the rounding control bits in the MXCSR register. If a converted result is larger than the maximum

signed doubleword integer, the floating-point invalid exception is raised, and if this exception is masked, the indef-

inite integer value (80000000H) is returned.

CVTPS2PI causes a transition from x87 FPU to MMX technology operation (that is, the x87 FPU top-of-stack pointer

is set to 0 and the x87 FPU tag word is set to all 0s [valid]). If this instruction is executed while an x87 FPU floating-

point exception is pending, the exception is handled before the CVTPS2PI instruction is executed.

In 64-bit mode, use of the REX.R prefix permits this instruction to access additional registers (XMM8-XMM15).

Operation

DEST[31:0] := Convert_Single_Precision_Floating_Point_To_Integer(SRC[31:0]);

DEST[63:32] := Convert_Single_Precision_Floating_Point_To_Integer(SRC[63:32]);

Intel C/C++ Compiler Intrinsic Equivalent

CVTPS2PI:

__m64 _mm_cvtps_pi32(__m128 a)

SIMD Floating-Point Exceptions

Invalid, Precision

Other Exceptions

See Table 23-5, “Exception Conditions for Legacy SIMD/MMX Instructions with XMM and FP Exception” in the

Intel® 64 and IA-32 Architectures Software Developer’s Manual, Volume 3B.

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INSTRUCTION SET REFERENCE, A-L

CVTSD2SI—Convert Scalar Double Precision Floating-Point Value to Doubleword Integer

Opcode/

Op /

64/32

CPUID

Description

Instruction

bit Mode

Feature

Support

Flag

F2 0F 2D /r

V/V

SSE2

Convert one double precision floating-point value from

CVTSD2SI r32, xmm1/m64

xmm1/m64 to one signed doubleword integer r32.

F2 REX.W 0F 2D /r

V/N.E.

SSE2

Convert one double precision floating-point value from

CVTSD2SI r64, xmm1/m64

xmm1/m64 to one signed quadword integer sign-

extended into r64.

VEX.LIG.F2.0F.W0 2D /r ¹

V/V

AVX

Convert one double precision floating-point value from

VCVTSD2SI r32, xmm1/m64

xmm1/m64 to one signed doubleword integer r32.

VEX.LIG.F2.0F.W1 2D /r ¹

V/N.E.²

AVX

Convert one double precision floating-point value from

VCVTSD2SI r64, xmm1/m64

xmm1/m64 to one signed quadword integer sign-

extended into r64.

EVEX.LLIG.F2.0F.W0 2D /r

V/V

AVX512F

Convert one double precision floating-point value from

VCVTSD2SI r32, xmm1/m64{er}

xmm1/m64 to one signed doubleword integer r32.

EVEX.LLIG.F2.0F.W1 2D /r

V/N.E.²

AVX512F

Convert one double precision floating-point value from

VCVTSD2SI r64, xmm1/m64{er}

xmm1/m64 to one signed quadword integer sign-

extended into r64.

NOTES:

1. Software should ensure VCVTSD2SI is encoded with VEX.L=0. Encoding VCVTSD2SI with VEX.L=1 may encounter unpredictable

behavior across different processor generations.

2. VEX.W1/EVEX.W1 in non-64 bit is ignored; the instructions behaves as if the W0 version is used.

Instruction Operand Encoding

Op/En

Tuple Type

Operand 1

Operand 2

Operand 3

Operand 4

N/A

ModRM:reg (w)

ModRM:r/m (r)

N/A

Tuple1 Fixed

ModRM:reg (w)

ModRM:r/m (r)

N/A

Description

Converts a double precision floating-point value in the source operand (the second operand) to a signed double-

word integer in the destination operand (first operand). The source operand can be an XMM register or a 64-bit

memory location. The destination operand is a general-purpose register. When the source operand is an XMM

When a conversion is inexact, the value returned is rounded according to the rounding control bits in the MXCSR

If a converted result exceeds the range limits of signed doubleword integer (in non-64-bit modes or 64-bit mode

with REX.W/VEX.W/EVEX.W=0), the floating-point invalid exception is raised, and if this exception is masked, the

indefinite integer value (80000000H) is returned.

If a converted result exceeds the range limits of signed quadword integer (in 64-bit mode and

REX.W/VEX.W/EVEX.W = 1), the floating-point invalid exception is raised, and if this exception is masked, the

indefinite integer value (80000000_00000000H) is returned.

Legacy SSE instruction: Use of the REX.W prefix promotes the instruction to produce 64-bit data in 64-bit mode.

See the summary chart at the beginning of this section for encoding data and limits.

Note: VEX.vvvv and EVEX.vvvv are reserved and must be 1111b, otherwise instructions will #UD.

Software should ensure VCVTSD2SI is encoded with VEX.L=0. Encoding VCVTSD2SI with VEX.L=1 may encounter

unpredictable behavior across different processor generations.

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INSTRUCTION SET REFERENCE, A-L

Operation

VCVTSD2SI (EVEX encoded version)

IF SRC *is register* AND (EVEX.b = 1)

THEN

SET_ROUNDING_MODE_FOR_THIS_INSTRUCTION(EVEX.RC);

ELSE

SET_ROUNDING_MODE_FOR_THIS_INSTRUCTION(MXCSR.RC);

FI;

IF 64-Bit Mode and OperandSize = 64

THEN DEST[63:0] := Convert_Double_Precision_Floating_Point_To_Integer(SRC[63:0]);

ELSE

DEST[31:0] := Convert_Double_Precision_Floating_Point_To_Integer(SRC[63:0]);

(V)CVTSD2SI

IF 64-Bit Mode and OperandSize = 64

THEN

DEST[63:0] := Convert_Double_Precision_Floating_Point_To_Integer(SRC[63:0]);

ELSE

DEST[31:0] := Convert_Double_Precision_Floating_Point_To_Integer(SRC[63:0]);

FI;

Intel C/C++ Compiler Intrinsic Equivalent

VCVTSD2SI int _mm_cvtsd_i32(__m128d);

VCVTSD2SI int _mm_cvt_roundsd_i32(__m128d, int r);

VCVTSD2SI __int64 _mm_cvtsd_i64(__m128d);

VCVTSD2SI __int64 _mm_cvt_roundsd_i64(__m128d, int r);

CVTSD2SI __int64 _mm_cvtsd_si64(__m128d);

CVTSD2SI int _mm_cvtsd_si32(__m128d a)

SIMD Floating-Point Exceptions

Invalid, Precision

Other Exceptions

VEX-encoded instructions, see Table 2-20, “Type 3 Class Exception Conditions”.

EVEX-encoded instructions, see Table 2-48, “Type E3NF Class Exception Conditions”.

Additionally:

#UD

If VEX.vvvv != 1111B or EVEX.vvvv != 1111B.

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Intel 64 and IA-32 Architectures. Software Developer’s Manual (Collection, 2023) - page 69