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Intel 64 and IA-32 Architectures. Software Developer’s Manual (Collection, 2023) - page 8

CHAPTER 2

MODEL-SPECIFIC REGISTERS (MSRS)

This chapter lists MSRs across Intel processor families. All MSRs listed can be read with the RDMSR and written with

the WRMSR instructions. The scope of an MSR defines the set of processors that access the same MSR with RDMSR

and WRMSR. Thread-scope MSRs are unique to every logical processor. Core-scope MSRs are shared by the threads

in the same core; similarly for module-scope, die-scope, and package-scope.

When a processor package contains a single die, die-scope and package-scope are synonymous. When a package

contains multiple die, they are distinct.

NOTE

For information on hierarchical level types supported, refer to the CPUID Leaf 1FH definition for the

actual level type numbers: “V2 Extended Topology Enumeration Leaf” in the Intel^® 64 and IA-32

Architectures Software Developer’s Manual, Volume 2A. Also see Section 9.9.1, “Hierarchical

Mapping of Shared Resources,” in the Intel^® 64 and IA-32 Architectures Software Developer’s

Manual, Volume 3A.

Register addresses are given in both hexadecimal and decimal. The register name is the mnemonic register name

and the bit description describes individual bits in registers.

Model specific registers and its bit-fields may be supported for a finite range of processor families/models. To distin-

guish between different processor family and/or models, software must use CPUID.01H leaf function to query the

combination of DisplayFamily and DisplayModel to determine model-specific availability of MSRs (see CPUID

instruction in Chapter 3, “Instruction Set Reference, A-L,” in the Intel^® 64 and IA-32 Architectures Software Devel-

oper’s Manual, Volume 2A). Table 2-1 lists the signature values of DisplayFamily and DisplayModel for various

processor families or processor number series.

Table 2-1. CPUID Signature Values of DisplayFamily_DisplayModel

DisplayFamily_DisplayModel

Processor Families/Processor Number Series

06_85H

Intel® Xeon Phi™ Processor 7215, 7285, 7295 Series based on Knights Mill microarchitecture

06_57H

Intel® Xeon Phi™ Processor 3200, 5200, 7200 Series based on Knights Landing microarchitecture

06_AAH

Intel® Core™ Ultra 7 processors supporting Meteor Lake performance hybrid architecture

06_CFH

5th generation Intel® Xeon® Scalable Processor Family based on Emerald Rapids microarchitecture

06_8FH

4th generation Intel® Xeon® Scalable Processor Family based on Sapphire Rapids microarchitecture

06_BAH, 06_B7H, 06_BFH

13th generation Intel® Core™ processors supporting Raptor Lake performance hybrid architecture

06_97H, 06_9AH

12th generation Intel® Core™ processors supporting Alder Lake performance hybrid architecture

06_8CH, 06_8DH

11th generation Intel® Core™ processors based on Tiger Lake microarchitecture

06_A7H

11th generation Intel® Core™ processors based on Rocket Lake microarchitecture

06_7DH, 06_7EH

10th generation Intel® Core™ processors based on Ice Lake microarchitecture

06_A5H, 06_A6H

10th generation Intel® Core™ processors based on Comet Lake microarchitecture

06_66H

Intel® Core™ processors based on Cannon Lake microarchitecture

06_8EH, 06_9EH

7th generation Intel® Core™ processors based on Kaby Lake microarchitecture, 8th and 9th generation

Intel® Core™ processors based on Coffee Lake microarchitecture, Intel® Xeon® E processors based on

Coffee Lake microarchitecture

06_6AH, 06_6CH

3rd generation Intel® Xeon® Scalable Processor Family based on Ice Lake microarchitecture

06_55H

Intel® Xeon® Scalable Processor Family based on Skylake microarchitecture, 2nd generation Intel®

Xeon® Scalable Processor Family based on Cascade Lake product, and 3rd generation Intel® Xeon®

Scalable Processor Family based on Cooper Lake product

Vol. 4

2-1

MODEL-SPECIFIC REGISTERS (MSRS)

Table 2-1. CPUID Signature Values of DisplayFamily_DisplayModel (Contd.)

DisplayFamily_DisplayModel

Processor Families/Processor Number Series

06_4EH, 06_5EH

6th generation Intel Core processors and Intel Xeon processor E3-1500m v5 product family and E3-

1200 v5 product family based on Skylake microarchitecture

06_56H

Intel Xeon processor D-1500 product family based on Broadwell microarchitecture

06_4FH

Intel Xeon processor E5 v4 Family based on Broadwell microarchitecture, Intel Xeon processor E7 v4

Family, Intel Core i7-69xx Processor Extreme Edition

06_47H

5th generation Intel Core processors, Intel Xeon processor E3-1200 v4 product family based on

Broadwell microarchitecture

06_3DH

Intel Core M-5xxx Processor, 5th generation Intel Core processors based on Broadwell

microarchitecture

06_3FH

Intel Xeon processor E5-4600/2600/1600 v3 product families, Intel Xeon processor E7 v3 product

families based on Haswell-E microarchitecture, Intel Core i7-59xx Processor Extreme Edition

06_3CH, 06_45H, 06_46H

4th Generation Intel Core processor and Intel Xeon processor E3-1200 v3 product family based on

Haswell microarchitecture

06_3EH

Intel Xeon processor E7-8800/4800/2800 v2 product families based on Ivy Bridge-E

microarchitecture

06_3EH

Intel Xeon processor E5-2600/1600 v2 product families and Intel Xeon processor E5-2400 v2

product family based on Ivy Bridge-E microarchitecture, Intel Core i7-49xx Processor Extreme Edition

06_3AH

3rd Generation Intel Core Processor and Intel Xeon processor E3-1200 v2 product family based on Ivy

Bridge microarchitecture

06_2DH

Intel Xeon processor E5 Family based on Sandy Bridge microarchitecture, Intel Core i7-39xx

Processor Extreme Edition

06_2FH

Intel Xeon Processor E7 Family

06_2AH

Intel Xeon processor E3-1200 product family; 2nd Generation Intel Core i7, i5, i3 Processors 2xxx

Series

06_2EH

Intel Xeon processor 7500, 6500 series

06_25H, 06_2CH

Intel Xeon processors 3600, 5600 series, Intel Core i7, i5, and i3 Processors

06_1EH, 06_1FH

Intel Core i7 and i5 Processors

06_1AH

Intel Core i7 Processor, Intel Xeon processor 3400, 3500, 5500 series

06_1DH

Intel Xeon processor MP 7400 series

06_17H

Intel Xeon processor 3100, 3300, 5200, 5400 series, Intel Core 2 Quad processors 8000, 9000

series

06_0FH

Intel Xeon processor 3000, 3200, 5100, 5300, 7300 series, Intel Core 2 Quad processor 6000 series,

Intel Core 2 Extreme 6000 series, Intel Core 2 Duo 4000, 5000, 6000, 7000 series processors, Intel

Pentium dual-core processors

06_0EH

Intel Core Duo, Intel Core Solo processors

06_0DH

Intel Pentium M processor

06_86H, 06_96H, 06_9CH

Intel Atom® processors, Intel® Celeron® processors, Intel® Pentium® processors, and Intel® Pentium®

Silver processors based on Tremont Microarchitecture

06_7AH

Intel Atom processors based on Goldmont Plus microarchitecture

06_5FH

Intel Atom processors based on Goldmont microarchitecture (Denverton)

06_5CH

Intel Atom processors based on Goldmont microarchitecture

06_4CH

Intel Atom processor X7-Z8000 and X5-Z8000 series based on Airmont microarchitecture

06_5DH

Intel Atom processor X3-C3000 based on Silvermont microarchitecture

06_5AH

Intel Atom processor Z3500 series

06_4AH

Intel Atom processor Z3400 series

2-2 Vol. 4

MODEL-SPECIFIC REGISTERS (MSRS)

Table 2-1. CPUID Signature Values of DisplayFamily_DisplayModel (Contd.)

DisplayFamily_DisplayModel

Processor Families/Processor Number Series

06_37H

Intel Atom processor E3000 series, Z3600 series, Z3700 series

06_4DH

Intel Atom processor C2000 series

06_36H

Intel Atom processor S1000 Series

06_1CH, 06_26H, 06_27H,

Intel Atom processor family, Intel Atom processor D2000, N2000, E2000, Z2000, C1000 series

06_35H, 06_36H

0F_06H

Intel Xeon processor 7100, 5000 Series, Intel Xeon Processor MP, Intel Pentium 4, Pentium D

processors

0F_03H, 0F_04H

Intel Xeon processor, Intel Xeon processor MP, Intel Pentium 4, Pentium D processors

06_09H

Intel Pentium M processor

0F_02H

Intel Xeon Processor, Intel Xeon processor MP, Intel Pentium 4 processors

0F_0H, 0F_01H

Intel Xeon Processor, Intel Xeon processor MP, Intel Pentium 4 processors

06_7H, 06_08H, 06_0AH,

Intel Pentium III Xeon processor, Intel Pentium III processor

06_0BH

06_03H, 06_05H

Intel Pentium II Xeon processor, Intel Pentium II processor

06_01H

Intel Pentium Pro processor

05_01H, 05_02H, 05_04H

Intel Pentium processor, Intel Pentium processor with MMX Technology

The Intel® Quark™ SoC X1000 processor can be identified by the signature of DisplayFamily_DisplayModel = 05_09H and

SteppingID = 0

2.1

ARCHITECTURAL MSRS

Many MSRs have carried over from one generation of IA-32 processors to the next and to Intel 64 processors. A

subset of MSRs and associated bit fields, which do not change on future processor generations, are now considered

architectural MSRs. For historical reasons (beginning with the Pentium 4 processor), these “architectural MSRs”

were given the prefix “IA32_”. Table 2-2 lists the architectural MSRs, their addresses, their current names, their

names in previous IA-32 processors, and bit fields that are considered architectural. MSR addresses outside Table

2-2 and certain bit fields in an MSR address that may overlap with architectural MSR addresses are model-specific.

Code that accesses a model-specific MSR and that is executed on a processor that does not support that MSR will

generate an exception.

Architectural MSR or individual bit fields in an architectural MSR may be introduced or transitioned at the granu-

larity of certain processor family/model or the presence of certain CPUID feature flags. The right-most column of

Table 2-2 provides information on the introduction of each architectural MSR or its individual fields. This informa-

tion is expressed either as signature values of “DF_DM” (see Table 2-1) or via CPUID flags.

Certain bit field position may be related to the maximum physical address width, the value of which is expressed

as “MAXPHYADDR” in Table 2-2. “MAXPHYADDR” is reported by CPUID.8000_0008H leaf.

MSR address range between 40000000H - 4000FFFFH is marked as a specially reserved range. All existing and

future processors will not implement any features using any MSR in this range.

Table 2-2. IA-32 Architectural MSRs

Register Address: Hex, Decimal

Architectural MSR Name (Former MSR Name)

Bit Fields

MSR/Bit Description

Comment

Register Address: 0H, 0

IA32_P5_MC_ADDR (P5_MC_ADDR)

See Section 2.23, “MSRs in Pentium Processors.”

Pentium Processor (05_01H)

Register Address: 1H, 1

IA32_P5_MC_TYPE (P5_MC_TYPE)

See Section 2.23, “MSRs in Pentium Processors.”

DF_DM = 05_01H

Vol. 4

2-3

MODEL-SPECIFIC REGISTERS (MSRS)

Table 2-2. IA-32 Architectural MSRs (Contd.)

Register Address: Hex, Decimal

Architectural MSR Name (Former MSR Name)

Bit Fields

MSR/Bit Description

Comment

Register Address: 6H, 6

IA32_MONITOR_FILTER_SIZE

See Section 9.10.5, “Monitor/Mwait Address Range Determination.”

0F_03H

Register Address: 10H, 16

IA32_TIME_STAMP_COUNTER (TSC)

See Section 18.17, “Time-Stamp Counter.”

05_01H

Register Address: 17H, 23

IA32_PLATFORM_ID (MSR_PLATFORM_ID)

Platform ID (R/O)

06_01H

The operating system can use this MSR to determine “slot” information for the processor and the

proper microcode update to load.

49:0

Reserved.

52:50

Platform ID (R/O)

Contains information concerning the intended platform for the

processor.

52 51

50

0

0

0 Processor Flag 0

0

0

1 Processor Flag 1

0

1

0 Processor Flag 2

0

1

1 Processor Flag 3

1

0

0 Processor Flag 4

1

0

1 Processor Flag 5

1

1

0 Processor Flag 6

1

1

1 Processor Flag 7

63:53

Reserved.

Register Address: 1BH, 27

IA32_APIC_BASE (APIC_BASE)

This register holds the APIC base address, permitting the relocation of the APIC memory map. See

06_01H

Section 11.4.4, “Local APIC Status and Location,” and Section 11.4.5, “Relocating the Local APIC

Registers.”

7:0

Reserved.

8

BSP Flag (R/W)

9

Reserved.

10

Enable x2APIC mode.

06_1AH

11

APIC Global Enable (R/W)

(MAXPHYADDR -1):12

APIC Base (R/W)

63: MAXPHYADDR

Reserved.

Register Address: 3AH, 58

IA32_FEATURE_CONTROL

Control Features in Intel 64 Processor (R/W)

If any one enumeration condition

for defined bit field holds.

2-4 Vol. 4

MODEL-SPECIFIC REGISTERS (MSRS)

Table 2-2. IA-32 Architectural MSRs (Contd.)

Register Address: Hex, Decimal

Architectural MSR Name (Former MSR Name)

Bit Fields

MSR/Bit Description

Comment

0

Lock bit (R/WO): (1 = locked).

If any one enumeration condition

for defined bit field position

When set, locks this MSR from being written; writes to this bit will result

greater than bit 0 holds.

in GP(0).

Note: Once the Lock bit is set, the contents of this register cannot be

modified. Therefore the lock bit must be set after configuring support for

Intel Virtualization Technology and prior to transferring control to an

option ROM or the OS. Hence, once the Lock bit is set, the entire

IA32_FEATURE_CONTROL contents are preserved across RESET when

PWRGOOD is not deasserted.

1

Enable VMX inside SMX operation (R/WL) This bit enables a system

If CPUID.01H:ECX[5] = 1 &&

executive to use VMX in conjunction with SMX to support Intel® Trusted

CPUID.01H:ECX[6] = 1

Execution Technology.

BIOS must set this bit only when the CPUID function 1 returns VMX

feature flag and SMX feature flag set (ECX bits 5 and 6 respectively).

2

Enable VMX outside SMX operation (R/WL) This bit enables VMX for a

If CPUID.01H:ECX[5] = 1

system executive that does not require SMX.

BIOS must set this bit only when the CPUID function 1 returns the VMX

feature flag set (ECX bit 5).

7:3

Reserved.

14:8

SENTER Local Function Enables (R/WL) When set, each bit in the field

If CPUID.01H:ECX[6] = 1

represents an enable control for a corresponding SENTER function. This

field is supported only if CPUID.1:ECX.[bit 6] is set.

15

SENTER Global Enable (R/WL)

If CPUID.01H:ECX[6] = 1

This bit must be set to enable SENTER leaf functions. This bit is

supported only if CPUID.1:ECX.[bit 6] is set.

16

Reserved.

17

SGX Launch Control Enable (R/WL)

If CPUID.(EAX=07H, ECX=0H):

This bit must be set to enable runtime re-configuration of SGX Launch

ECX[30] = 1

Control via the IA32_SGXLEPUBKEYHASHn MSR.

18

SGX Global Enable (R/WL)

If CPUID.(EAX=07H, ECX=0H):

EBX[2] = 1

This bit must be set to enable SGX leaf functions.

19

Reserved.

20

LMCE On (R/WL)

If IA32_MCG_CAP[27] = 1

When set, system software can program the MSRs associated with LMCE

to configure delivery of some machine check exceptions to a single

logical processor.

63:21

Reserved.

Register Address: 3BH, 59

IA32_TSC_ADJUST

Per Logical Processor TSC Adjust (R/Write to clear)

If CPUID.(EAX=07H, ECX=0H):

EBX[1] = 1

63:0

THREAD_ADJUST

Local offset value of the IA32_TSC for a logical processor. Reset value is

zero. A write to IA32_TSC will modify the local offset in

IA32_TSC_ADJUST and the content of IA32_TSC, but does not affect the

internal invariant TSC hardware.

Vol. 4

2-5

MODEL-SPECIFIC REGISTERS (MSRS)

Table 2-2. IA-32 Architectural MSRs (Contd.)

Register Address: Hex, Decimal

Architectural MSR Name (Former MSR Name)

Bit Fields

MSR/Bit Description

Comment

Register Address: 48H, 72

IA32_SPEC_CTRL

Speculation Control (R/W)

If any one of the enumeration

conditions for defined bit field

The MSR bits are defined as logical processor scope. On some core implementations, the bits may

impact sibling logical processors on the same core.

positions holds.

This MSR has a value of 0 after reset and is unaffected by INIT# or SIPI#.

0

Indirect Branch Restricted Speculation (IBRS). Restricts speculation of

If CPUID.(EAX=07H,

indirect branch.

ECX=0):EDX[26]=1

1

Single Thread Indirect Branch Predictors (STIBP). Prevents indirect

If CPUID.(EAX=07H,

branch predictions on all logical processors on the core from being

ECX=0):EDX[27]=1

controlled by any sibling logical processor in the same core.

2

Speculative Store Bypass Disable (SSBD) delays speculative execution of

If CPUID.(EAX=07H,

a load until the addresses for all older stores are known.

ECX=0):EDX[31]=1

3

IPRED_DIS_U

If CPUID.(EAX=07H,

ECX=2):EDX[1]=1

If 1, enables IPRED_DIS control for CPL3.

4

IPRED_DIS_S

If CPUID.(EAX=07H,

ECX=2):EDX[1]=1

If 1, enables IPRED_DIS control for CPL0/1/2.

5

RRSBA_DIS_U

If CPUID.(EAX=07H,

ECX=2):EDX[2]=1

If 1, disables RRSBA behavior for CPL3.

6

RRSBA_DIS_S

If CPUID.(EAX=07H,

ECX=2):EDX[2]=1

If 1, disables RRSBA behavior for CPL0/1/2.

7

PSFD

If CPUID.(EAX=07H,

ECX=2):EDX[0]=1

If 1, disables Fast Store Forwarding Predictor. Note that setting bit 2

(SSBD) also disables this.

8

DDPD_U

If CPUID.(EAX=07H,

ECX=2):EDX[3]=1

If 1, disables the Data Dependent Prefetcher that examines data values

in memory while CPL = 3. Note that setting bit 2 (SSBD) also disables

this.

9

Reserved.

10

BHI_DIS_S

If CPUID.(EAX=07H,

ECX=2):EDX[4]=1

When ‘1, enables BHI_DIS_S behavior.

63:11

Reserved.

Register Address: 49H, 73

IA32_PRED_CMD

Prediction Command (WO)

If any one of the enumeration

conditions for defined bit field

Gives software a way to issue commands that affect the state of predictors.

positions holds.

0

Indirect Branch Prediction Barrier (IBPB)

If CPUID.(EAX=07H,

ECX=0):EDX[26]=1

63:1

Reserved.

Register Address: 4EH, 78

IA32_PPIN_CTL

Protected Processor Inventory Number Enable Control (R/W)

If CPUID.(EAX=07H,

ECX=01H):EBX[0]=1¹

2-6 Vol. 4

MODEL-SPECIFIC REGISTERS (MSRS)

Table 2-2. IA-32 Architectural MSRs (Contd.)

Register Address: Hex, Decimal

Architectural MSR Name (Former MSR Name)

Bit Fields

MSR/Bit Description

Comment

0

LockOut (R/WO)

If 0, indicates that further writes to IA32_PPIN_CTL is allowed.

If 1, indicates that further writes to IA32_PPIN_CTL is disallowed.

Writing 1 to this bit is only permitted if the Enable_PPIN bit is clear.

The Privileged System Software Inventory Agent should read

IA32_PPIN_CTL[bit 1] to determine if IA32_PPIN is accessible.

The Privileged System Software Inventory Agent is not expected to

write to this MSR.

1

Enable_PPIN (R/W)

If 1, indicates that IA32_PPIN is accessible using RDMSR.

If 0, indicates that IA32_PPIN is inaccessible using RDMSR. Any attempt

to read IA32_PPIN will cause #GP.

63:2

Reserved.

Register Address: 4FH, 79

IA32_PPIN

Protected Processor Inventory Number (R/O)

If CPUID.(EAX=07H,

ECX=01H):EBX[0]=1¹

63:0

Protected Processor Inventory Number (R/O)

A unique value within a given CPUID family/model/stepping signature

that a privileged inventory initialization agent can access to identify each

physical processor, when access to IA32_PPIN is enabled. Access to

IA32_PPIN is permitted only if IA32_PPIN_CTL[bits 1:0] = ‘10b’.

Register Address: 79H, 121

IA32_BIOS_UPDT_TRIG (BIOS_UPDT_TRIG)

BIOS Update Trigger (W)

06_01H

Executing a WRMSR instruction to this MSR causes a microcode update to be loaded into the

processor. See Section 10.11.6, “Microcode Update Loader.”

A processor may prevent writing to this MSR when loading guest states on VM entries or saving

guest states on VM exits.

Register Address: 7AH, 122

IA32_FEATURE_ACTIVATION

Feature Activation (R/W)

Implements Feature Activation command. WRMSR to this address activates all 'activatable'

features on this thread.

0

Reserved.

1

KL

Keylocker feature activation.

63:2

Reserved.

Register Address: 8BH, 139

IA32_BIOS_SIGN_ID (BIOS_SIGN/BBL_CR_D3)

BIOS Update Signature (R/W)

06_01H

Returns the microcode update signature following the execution of CPUID.01H.

A processor may prevent writing to this MSR when loading guest states on VM entries or saving

guest states on VM exits.

31:0

Reserved.

Register Address: 8CH, 140

IA32_SGXLEPUBKEYHASH0

Vol. 4

2-7

MODEL-SPECIFIC REGISTERS (MSRS)

Table 2-2. IA-32 Architectural MSRs (Contd.)

Register Address: Hex, Decimal

Architectural MSR Name (Former MSR Name)

Bit Fields

MSR/Bit Description

Comment

IA32_SGXLEPUBKEYHASH[63:0] (R/W)

Read permitted If

CPUID.(EAX=12H,ECX=0H):

Bits 63:0 of the SHA256 digest of the SIGSTRUCT.MODULUS for SGX Launch Enclave. On reset,

EAX[0]=1 && CPUID.(EAX=07H,

the default value is the digest of Intel’s signing key.

ECX=0H):ECX[30]=1.

Write permitted if

CPUID.(EAX=12H,ECX=0H):

EAX[0]=1 &&

IA32_FEATURE_CONTROL[17] = 1

&& IA32_FEATURE_CONTROL[0]

= 1.

Register Address: 8DH, 141

IA32_SGXLEPUBKEYHASH1

IA32_SGXLEPUBKEYHASH[127:64] (R/W)

Same comment in MSR listing for

IA32_SGXLEPUBKEYHASH0 (MSR

Bits 127:64 of the SHA256 digest of the SIGSTRUCT.MODULUS for SGX Launch Enclave. On reset,

address 8CH, 140) applies here.

the default value is the digest of Intel’s signing key.

Register Address: 8EH, 142

IA32_SGXLEPUBKEYHASH2

IA32_SGXLEPUBKEYHASH[191:128] (R/W)

Same comment in MSR listing for

IA32_SGXLEPUBKEYHASH0 (MSR

Bits 191:128 of the SHA256 digest of the SIGSTRUCT.MODULUS for SGX Launch Enclave. On

address 8CH, 140) applies here.

reset, the default value is the digest of Intel’s signing key.

Register Address: 8FH, 143

IA32_SGXLEPUBKEYHASH3

IA32_SGXLEPUBKEYHASH[255:192] (R/W)

Same comment in MSR listing for

IA32_SGXLEPUBKEYHASH0 (MSR

Bits 255:192 of the SHA256 digest of the SIGSTRUCT.MODULUS for SGX Launch Enclave. On

address 8CH, 140) applies here.

reset, the default value is the digest of Intel’s signing key.

Register Address: 9BH, 155

IA32_SMM_MONITOR_CTL

SMM Monitor Configuration (R/W)

If CPUID.01H: ECX[5]=1 ||

CPUID.01H: ECX[6] = 1

0

Valid (R/W)

1

Reserved.

2

Controls SMI unblocking by VMXOFF (see Section 32.14.4).

If IA32_VMX_MISC[28]

11:3

Reserved.

31:12

MSEG Base (R/W)

63:32

Reserved.

Register Address: 9EH, 158

IA32_SMBASE

Base address of the logical processor’s SMRAM image (R/O, SMM only).

If IA32_VMX_MISC[15]

Register Address: BCH, 188

IA32_MISC_PACKAGE_CTLS

Power Filtering Control (R/W)

If IA32_ARCH_CAPABILITIES

[10] = 1

This MSR has a value of 0 after reset and is unaffected by INIT# or SIPI#.

0

ENERGY_FILTERING_ENABLE (R/W)

If IA32_ARCH_CAPABILITIES

[11] = 1

If set, RAPL MSRs report filtered processor power consumption data.

This bit can be changed from 0 to 1, but cannot be changed from 1 to 0.

After setting, all attempts to clear it are ignored until the next processor

reset.

63:1

Reserved.

Register Address: BDH, 189

IA32_XAPIC_DISABLE_STATUS

2-8 Vol. 4

MODEL-SPECIFIC REGISTERS (MSRS)

Table 2-2. IA-32 Architectural MSRs (Contd.)

Register Address: Hex, Decimal

Architectural MSR Name (Former MSR Name)

Bit Fields

MSR/Bit Description

Comment

xAPIC Disable Status (R/O)

If CPUID.(EAX-07H,

ECX=0):EDX[29]=1 and

IA32_ARCH_CAPABILITIES [21] =

1

0

LEGACY_XAPIC_DISABLED

When set, indicates that the local APIC is in x2APIC mode

(IA32_APIC_BASE.EXTD = 1) and that attempts to clear

IA32_APIC_BASE.EXTD will fail (e.g., WRMSR will #GP).

63:1

Reserved.

Register Address: C1H, 193

IA32_PMC0 (PERFCTR0)

General Performance Counter 0 (R/W)

If CPUID.0AH: EAX[15:8] > 0

Register Address: C2H, 194

IA32_PMC1 (PERFCTR1)

General Performance Counter 1 (R/W)

If CPUID.0AH: EAX[15:8] > 1

Register Address: C3H, 195

IA32_PMC2

General Performance Counter 2 (R/W)

If CPUID.0AH: EAX[15:8] > 2

Register Address: C4H, 196

IA32_PMC3

General Performance Counter 3 (R/W)

If CPUID.0AH: EAX[15:8] > 3

Register Address: C5H, 197

IA32_PMC4

General Performance Counter 4 (R/W)

If CPUID.0AH: EAX[15:8] > 4

Register Address: C6H, 198

IA32_PMC5

General Performance Counter 5 (R/W)

If CPUID.0AH: EAX[15:8] > 5

Register Address: C7H, 199

IA32_PMC6

General Performance Counter 6 (R/W)

If CPUID.0AH: EAX[15:8] > 6

Register Address: C8H, 200

IA32_PMC7

General Performance Counter 7 (R/W)

If CPUID.0AH: EAX[15:8] > 7

Register Address: CFH, 207

IA32_CORE_CAPABILITIES

IA32 Core Capabilities Register

If CPUID.(EAX=07H,

ECX=0):EDX[30] = 1

63:0

Reserved.

No architecturally defined bits.

Register Address: E1H, 225

IA32_UMWAIT_CONTROL

UMWAIT Control (R/W)

0

C0.2 is not allowed by the OS. Value of “1” means all C0.2 requests revert

to C0.1.

1

Reserved.

31:2

Determines the maximum time in TSC-quanta that the processor can

reside in either C0.1 or C0.2. A zero value indicates no maximum time.

The maximum time value is a 32-bit value where the upper 30 bits come

from this field and the lower two bits are zero.

Register Address: E7H, 231

IA32_MPERF

TSC Frequency Clock Counter (R/Write to clear)

If CPUID.06H: ECX[0] = 1

Vol. 4

2-9

MODEL-SPECIFIC REGISTERS (MSRS)

Table 2-2. IA-32 Architectural MSRs (Contd.)

Register Address: Hex, Decimal

Architectural MSR Name (Former MSR Name)

Bit Fields

MSR/Bit Description

Comment

63:0

C0_MCNT: C0 TSC Frequency Clock Count

Increments at fixed interval (relative to TSC freq.) when the logical

processor is in C0.

Cleared upon overflow / wrap-around of IA32_APERF.

Register Address: E8H, 232

IA32_APERF

Actual Performance Clock Counter (R/Write to clear)

If CPUID.06H: ECX[0] = 1

63:0

C0_ACNT: C0 Actual Frequency Clock Count

Accumulates core clock counts at the coordinated clock frequency, when

the logical processor is in C0.

Cleared upon overflow / wrap-around of IA32_MPERF.

Register Address: FEH, 254

IA32_MTRRCAP (MTRRcap)

MTRR Capability (R/O)

06_01H

See Section 12.11.2.1, “IA32_MTRR_DEF_TYPE MSR.”

7:0

VCNT: The number of variable memory type ranges in the processor.

8

Fixed range MTRRs are supported when set.

9

Reserved.

10

WC Supported when set.

11

SMRR Supported when set.

12

PRMRR supported when set.

63:13

Reserved.

Register Address: 10AH, 266

IA32_ARCH_CAPABILITIES

Enumeration of Architectural Features (R/O)

If CPUID.(EAX=07H,

ECX=0):EDX[29]=1

0

RDCL_NO: The processor is not susceptible to Rogue Data Cache Load

(RDCL).

1

IBRS_ALL: The processor supports enhanced IBRS.

2

RSBA: The processor supports RSB Alternate. Alternative branch

predictors may be used by RET instructions when the RSB is empty. SW

using retpoline may be affected by this behavior.

3

SKIP_L1DFL_VMENTRY: A value of 1 indicates the hypervisor need not

flush the L1D on VM entry.

4

SSB_NO: Processor is not susceptible to Speculative Store Bypass.

5

MDS_NO: Processor is not susceptible to Microarchitectural Data

Sampling (MDS).

6

IF_PSCHANGE_MC_NO: The processor is not susceptible to a machine

check error due to modifying the size of a code page without TLB

invalidation.

7

TSX_CTRL: If 1, indicates presence of IA32_TSX_CTRL MSR.

8

TAA_NO: If 1, processor is not affected by TAA.

9

MCU_CONTROL: If 1, the processor supports the IA32_MCU_CONTROL

MSR.

2-10 Vol. 4

MODEL-SPECIFIC REGISTERS (MSRS)

Table 2-2. IA-32 Architectural MSRs (Contd.)

Register Address: Hex, Decimal

Architectural MSR Name (Former MSR Name)

Bit Fields

MSR/Bit Description

Comment

10

MISC_PACKAGE_CTLS: The processor supports

IA32_MISC_PACKAGE_CTLS MSR.

11

ENERGY_FILTERING_CTL: The processor supports setting and reading

the IA32_MISC_PACKAGE_CTLS[0] (ENERGY_FILTERING_ENABLE) bit.

12

DOITM: If 1, the processor supports Data Operand Independent Timing

Mode.

13

SBDR_SSDP_NO: The processor is not affected by either the Shared

Buffers Data Read (SBDR) vulnerability or the Sideband Stale Data

Propagator (SSDP).

14

FBSDP_NO: The processor is not affected by the Fill Buffer Stale Data

Propagator (FBSDP).

15

PSDP_NO: The processor is not affected by vulnerabilities involving the

Primary Stale Data Propagator (PSDP).

16

Reserved.

17

FB_CLEAR: If 1, the processor supports overwrite of fill buffer values as

part of MD_CLEAR operations with the VERW instruction.

18

FB_CLEAR_CTRL: If 1, the processor supports the IA32_MCU_OPT_CTRL

MSR and allows software to set bit 3 of that MSR (FB_CLEAR_DIS).

19

RRSBA: A value of 1 indicates the processor may have the RRSBA

alternate prediction behavior, if not disabled by RRSBA_DIS_U or

RRSBA_DIS_S.

20

BHI_NO: A value of 1 indicates BHI_NO branch prediction behavior,

regardless of the value of IA32_SPEC_CTRL[BHI_DIS_S] MSR bit.

21

XAPIC_DISABLE_STATUS: Enumerates that the

IA32_XAPIC_DISABLE_STATUS MSR exists, and that bit 0 specifies

whether the legacy xAPIC is disabled and APIC state is locked to x2APIC.

22

Reserved.

23

OVERCLOCKING_STATUS: If set, the IA32_OVERCLOCKING_STATUS MSR

exists.

24

PBRSB_NO: If 1, the processor is not affected by issues related to Post-

Barrier Return Stack Buffer Predictions.

63:25

Reserved.

Register Address: 10BH, 267

IA32_FLUSH_CMD

Flush Command (WO)

If any one of the enumeration

conditions for defined bit field

Gives software a way to invalidate structures with finer granularity than other architectural

methods.

positions holds.

0

L1D_FLUSH: Writeback and invalidate the L1 data cache.

If CPUID.(EAX=07H,

ECX=0):EDX[28]=1

63:1

Reserved.

Register Address: 10FH, 271

IA32_TSX_FORCE_ABORT

TSX Force Abort

If CPUID.(EAX=07H,

ECX=0):EDX[13]=1

Vol. 4

2-11

MODEL-SPECIFIC REGISTERS (MSRS)

Table 2-2. IA-32 Architectural MSRs (Contd.)

Register Address: Hex, Decimal

Architectural MSR Name (Former MSR Name)

Bit Fields

MSR/Bit Description

Comment

0

RTM_FORCE_ABORT

R/W, Default: 0

If 1, all RTM transactions abort with EAX code 0.

If CPUID.(EAX=07H,ECX=0):

EDX[11]=1, bit 0 is always 1 and

writes to change it are ignored.

If SDV_ENABLE_RTM is 1, bit 0 is

always 0 and writes to change it

are ignored.

1

TSX_CPUID_CLEAR

R/W, Default: 0

When set, CPUID.(EAX=07H,ECX=0):EBX[11]=0 and

Can be set only if

CPUID.(EAX=07H,ECX=0):EBX[4]=0.

CPUID.(EAX=07H,ECX=0):

EDX[11]=1 or if

SDV_ENABLE_RTM is 1.

2

SDV_ENABLE_RTM

R/W, Default: 0

When set, CPUID.(EAX=07H,ECX=0):EDX[11]=0 and the processor may

If 0, can be set only if

not force abort RTM. This unsupported mode should only be used for

CPUID.(EAX=07H,ECX=0):

software development and not for production usage.

EDX[11]=1.

63:3

Reserved.

Register Address: 122H, 290

IA32_TSX_CTRL

IA32_TSX_CTRL

Thread scope. Not architecturally

serializing.

Available when

CPUID.ARCH_CAP(EAX=7H, ECX =

0):EDX[29] = 1 and

IA32_ARCH_CAPABILITIES.bit 7 =

1.

0

RTM_DISABLE

When set to 1, XBEGIN will always abort with EAX code 0.

1

TSX_CPUID_CLEAR

When set to 1, CPUID.07H.EBX.RTM [bit 11] and CPUID.07H.EBX.HLE [bit

4] report 0.

When set to 0 and the SKU supports TSX, these bits will return 1.

63:2

Reserved.

Register Address: 123H, 291

IA32_MCU_OPT_CTRL

Microcode Update Option Control (R/W)

If CPUID.(EAX=07H,

ECX=0):EDX[9]=1 or

IA32_ARCH_CAPABILITIES [18] =

1 or IA32_ARCH_CAPABILITIES.

FB_CLEAR_CTRL=1

0

RNGDS_MITG_DIS (R/W)

If CPUID.(EAX=07H,

ECX=0):EDX[9]=1

If 0 (default), SRBDS mitigation is enabled for RDRAND and RDSEED.

If 1, SRBDS mitigation is disabled for RDRAND and RDSEED executed

outside of Intel SGX enclaves.

1

RTM_ALLOW

Read/Write

If 0, XBEGIN will always abort with EAX code 0.

Setting RTM_LOCKED prevents

writes to this bit.

If 1, XBEGIN behavior depends on the value of

IA32_TSX_CTRL[RTM_DISABLE].

2-12 Vol. 4

MODEL-SPECIFIC REGISTERS (MSRS)

Table 2-2. IA-32 Architectural MSRs (Contd.)

Register Address: Hex, Decimal

Architectural MSR Name (Former MSR Name)

Bit Fields

MSR/Bit Description

Comment

2

RTM_LOCKED

Read-Only status bit.

When 1, RTM_ALLOW is locked at zero, writes to RTM_ALLOW will be

ignored.

3

FB_CLEAR_DIS

If IA32_ARCH_CAPABILITIES.

FB_CLEAR_CTRL=1

If 1, prevents the VERW instruction from performing an FB_CLEAR

action.

4

GDS_MITG_DIS

If 0, the Gather Data Sampling mitigation is enabled (patch load time

default).

If 1 on all threads for a given core, the Gather Data Sampling mitigation is

disabled.

5

GDS_MITG_LOCK

If 0, not locked, and GDS_MITG_DIS is under OS control.

If 1, locked and GDS_MITG_DIS is forced to 0 (writes are ignored).

63:6

Reserved.

Register Address: 174H, 372

IA32_SYSENTER_CS

SYSENTER_CS_MSR (R/W)

06_01H

15:0

CS Selector.

31:16

Not used.

Can be read and written.

63:32

Not used.

Writes ignored; reads

return zero.

Register Address: 175H, 373

IA32_SYSENTER_ESP

SYSENTER_ESP_MSR (R/W)

06_01H

Register Address: 176H, 374

IA32_SYSENTER_EIP

SYSENTER_EIP_MSR (R/W)

06_01H

Register Address: 179H, 377

IA32_MCG_CAP (MCG_CAP)

Global Machine Check Capability (R/O)

06_01H

7:0

Count: Number of reporting banks.

8

MCG_CTL_P: IA32_MCG_CTL is present if this bit is set.

9

MCG_EXT_P: Extended machine check state registers are present if this

bit is set.

10

MCP_CMCI_P: Support for corrected MC error event is present.

06_01H

11

MCG_TES_P: Threshold-based error status register are present if this bit

is set.

15:12

Reserved.

23:16

MCG_EXT_CNT: Number of extended machine check state registers

present.

24

MCG_SER_P: The processor supports software error recovery if this bit is

set.

25

Reserved.

Vol. 4

2-13

MODEL-SPECIFIC REGISTERS (MSRS)

Table 2-2. IA-32 Architectural MSRs (Contd.)

Register Address: Hex, Decimal

Architectural MSR Name (Former MSR Name)

Bit Fields

MSR/Bit Description

Comment

26

MCG_ELOG_P: Indicates that the processor allows platform firmware to

06_3EH

be invoked when an error is detected so that it may provide additional

platform specific information in an ACPI format “Generic Error Data

Entry” that augments the data included in machine check bank registers.

27

MCG_LMCE_P: Indicates that the processor supports extended state in

06_3EH

IA32_MCG_STATUS and associated MSR necessary to configure Local

Machine Check Exception (LMCE).

63:28

Reserved.

Register Address: 17AH, 378

IA32_MCG_STATUS (MCG_STATUS)

Global Machine Check Status (R/W)

06_01H

0

RIPV. Restart IP valid.

06_01H

1

EIPV. Error IP valid.

06_01H

2

MCIP. Machine check in progress.

06_01H

3

LMCE_S.

If IA32_MCG_CAP.LMCE_P[27] =1

63:4

Reserved.

Register Address: 17BH, 379

IA32_MCG_CTL (MCG_CTL)

Global Machine Check Control (R/W)

If IA32_MCG_CAP.CTL_P[8] =1

Register Address: 180H-185H, 384-389

N/A

Reserved

06_0EH²

Register Address: 186H, 390

IA32_PERFEVTSEL0 (PERFEVTSEL0)

Performance Event Select Register 0 (R/W)

If CPUID.0AH: EAX[15:8] > 0

7:0

Event Select: Selects a performance event logic unit.

15:8

UMask: Qualifies the microarchitectural condition to detect on the

selected event logic.

16

USR: Counts while in privilege level is not ring 0.

17

OS: Counts while in privilege level is ring 0.

18

Edge: Enables edge detection if set.

19

PC: Enables pin control.

20

INT: Enables interrupt on counter overflow.

21

AnyThread: When set to 1, it enables counting the associated event

conditions occurring across all logical processors sharing a processor

core. When set to 0, the counter only increments the associated event

conditions occurring in the logical processor which programmed the MSR.

22

EN: Enables the corresponding performance counter to commence

counting when this bit is set.

23

INV: Invert the CMASK.

31:24

CMASK: When CMASK is not zero, the corresponding performance

counter increments each cycle if the event count is greater than or equal

to the CMASK.

63:32

Reserved.

Register Address: 187H, 391

IA32_PERFEVTSEL1 (PERFEVTSEL1)

2-14 Vol. 4

MODEL-SPECIFIC REGISTERS (MSRS)

Table 2-2. IA-32 Architectural MSRs (Contd.)

Register Address: Hex, Decimal

Architectural MSR Name (Former MSR Name)

Bit Fields

MSR/Bit Description

Comment

Performance Event Select Register 1 (R/W)

If CPUID.0AH: EAX[15:8] > 1

Register Address: 188H, 392

IA32_PERFEVTSEL2

Performance Event Select Register 2 (R/W)

If CPUID.0AH: EAX[15:8] > 2

Register Address: 189H, 393

IA32_PERFEVTSEL3

Performance Event Select Register 3 (R/W)

If CPUID.0AH: EAX[15:8] > 3

Register Address: 18AH, 394

IA32_PERFEVTSEL4

Performance Event Select Register 4 (R/W)

If CPUID.0AH: EAX[15:8] > 4

Register Address: 18BH, 395

IA32_PERFEVTSEL5

Performance Event Select Register 5 (R/W)

If CPUID.0AH: EAX[15:8] > 5

Register Address: 18CH, 396

IA32_PERFEVTSEL6

Performance Event Select Register 6 (R/W)

If CPUID.0AH: EAX[15:8] > 6

Register Address: 18DH, 397

IA32_PERFEVTSEL7

Performance Event Select Register 7 (R/W)

If CPUID.0AH: EAX[15:8] > 7

Register Address: 18AH-194H, 394-404

N/A

Reserved.

06_0EH³

Register Address: 195H, 405

IA32_OVERCLOCKING_STATUS

Overclocking Status (R/O)

IA32_ARCH_CAPABILITIES[bit 23] enumerates support for this MSR.

0

Overclocking Utilized

Indicates if specific forms of overclocking have been enabled on this boot

or reset cycle: 0 indicates no, 1 indicates yes.

1

Undervolt Protection

Indicates if the “Dynamic OC Undervolt Protection” security feature is

active: 0 indicates disabled, 1indicates enabled.

2

Overclocking Secure Status

Indicates that overclocking capabilities have been unlocked by BIOS, with

or without overclocking: 0 indicates Not Secured, 1 indicates Secure.

63:4

Reserved.

Register Address: 196H-197H, 406-407

N/A

Reserved.

06_0EH³

Register Address: 198H, 408

IA32_PERF_STATUS

Current Performance Status (R/O)

0F_03H

See Section 15.1.1, “Software Interface For Initiating Performance State Transitions.”

15:0

Current Performance State Value.

63:16

Reserved.

Register Address: 199H, 409

IA32_PERF_CTL

Performance Control MSR (R/W)

0F_03H

Software makes a request for a new Performance state (P-State) by writing this MSR. See

Section 15.1.1, “Software Interface For Initiating Performance State Transitions.”

Vol. 4

2-15

MODEL-SPECIFIC REGISTERS (MSRS)

Table 2-2. IA-32 Architectural MSRs (Contd.)

Register Address: Hex, Decimal

Architectural MSR Name (Former MSR Name)

Bit Fields

MSR/Bit Description

Comment

15:0

Target performance State Value.

31:16

Reserved.

32

Intel® Dynamic Acceleration Technology Engage (R/W)

06_0FH (Mobile only)

When set to 1: Disengages Intel Dynamic Acceleration Technology.

63:33

Reserved.

Register Address: 19AH, 410

IA32_CLOCK_MODULATION

Clock Modulation Control (R/W)

If CPUID.01H:EDX[22] = 1

See Section 15.8.3, “Software Controlled Clock Modulation.”

0

Extended On-Demand Clock Modulation Duty Cycle.

If CPUID.06H:EAX[5] = 1

3:1

On-Demand Clock Modulation Duty Cycle: Specific encoded values for

If CPUID.01H:EDX[22] = 1

target duty cycle modulation.

4

On-Demand Clock Modulation Enable: Set 1 to enable modulation.

If CPUID.01H:EDX[22] = 1

63:5

Reserved.

Register Address: 19BH, 411

IA32_THERM_INTERRUPT

Thermal Interrupt Control (R/W)

If CPUID.01H:EDX[22] = 1

Enables and disables the generation of an interrupt on temperature transitions detected with the

processor’s thermal sensors and thermal monitor.

See Section 15.8.2, “Thermal Monitor.”

0

High-Temperature Interrupt Enable

If CPUID.01H:EDX[22] = 1

1

Low-Temperature Interrupt Enable

If CPUID.01H:EDX[22] = 1

2

PROCHOT# Interrupt Enable

If CPUID.01H:EDX[22] = 1

3

FORCEPR# Interrupt Enable

If CPUID.01H:EDX[22] = 1

4

Critical Temperature Interrupt Enable

If CPUID.01H:EDX[22] = 1

7:5

Reserved.

14:8

Threshold #1 Value

If CPUID.01H:EDX[22] = 1

15

Threshold #1 Interrupt Enable

If CPUID.01H:EDX[22] = 1

22:16

Threshold #2 Value

If CPUID.01H:EDX[22] = 1

23

Threshold #2 Interrupt Enable

If CPUID.01H:EDX[22] = 1

24

Power Limit Notification Enable

If CPUID.06H:EAX[4] = 1

25

Hardware Feedback Notification Enable

If CPUID.06H:EAX[24] = 1

63:26

Reserved.

Register Address: 19CH, 412

IA32_THERM_STATUS

Thermal Status Information (R/O)

If CPUID.01H:EDX[22] = 1

Contains status information about the processor’s thermal sensor and automatic thermal

monitoring facilities.

See Section 15.8.2, “Thermal Monitor.”

0

Thermal Status (R/O)

If CPUID.01H:EDX[22] = 1

1

Thermal Status Log (R/W)

If CPUID.01H:EDX[22] = 1

2

PROCHOT # or FORCEPR# event (R/O)

If CPUID.01H:EDX[22] = 1

2-16 Vol. 4

MODEL-SPECIFIC REGISTERS (MSRS)

Table 2-2. IA-32 Architectural MSRs (Contd.)

Register Address: Hex, Decimal

Architectural MSR Name (Former MSR Name)

Bit Fields

MSR/Bit Description

Comment

3

PROCHOT # or FORCEPR# log (R/WC0)

If CPUID.01H:EDX[22] = 1

4

Critical Temperature Status (R/O)

If CPUID.01H:EDX[22] = 1

5

Critical Temperature Status log (R/WC0)

If CPUID.01H:EDX[22] = 1

6

Thermal Threshold #1 Status (R/O)

If CPUID.01H:ECX[8] = 1

7

Thermal Threshold #1 log (R/WC0)

If CPUID.01H:ECX[8] = 1

8

Thermal Threshold #2 Status (R/O)

If CPUID.01H:ECX[8] = 1

9

Thermal Threshold #2 log (R/WC0)

If CPUID.01H:ECX[8] = 1

10

Power Limitation Status (R/O)

If CPUID.06H:EAX[4] = 1

11

Power Limitation log (R/WC0)

If CPUID.06H:EAX[4] = 1

12

Current Limit Status (R/O)

If CPUID.06H:EAX[7] = 1

13

Current Limit log (R/WC0)

If CPUID.06H:EAX[7] = 1

14

Cross Domain Limit Status (R/O)

If CPUID.06H:EAX[7] = 1

15

Cross Domain Limit log (R/WC0)

If CPUID.06H:EAX[7] = 1

22:16

Digital Readout (R/O)

If CPUID.06H:EAX[0] = 1

26:23

Reserved.

30:27

Resolution in Degrees Celsius (R/O)

If CPUID.06H:EAX[0] = 1

31

Reading Valid (R/O)

If CPUID.06H:EAX[0] = 1

63:32

Reserved.

Register Address: 1A0H, 416

IA32_MISC_ENABLE

Enable Misc. Processor Features (R/W)

Allows a variety of processor functions to be enabled and disabled.

0

Fast-Strings Enable

0F_0H

When set, the fast-strings feature (for REP MOVS and REP STORS) is

enabled (default). When clear, fast-strings are disabled.

2:1

Reserved.

3

Automatic Thermal Control Circuit Enable (R/W)

0F_0H

1 = Setting this bit enables the thermal control circuit (TCC) portion of

the Intel Thermal Monitor feature. This allows the processor to

automatically reduce power consumption in response to TCC

activation.

0 = Disabled.

Note: In some products clearing this bit might be ignored in critical

thermal conditions, and TM1, TM2, and adaptive thermal throttling will

still be activated.

The default value of this field varies with product. See respective tables

where default value is listed.

6:4

Reserved.

7

Performance Monitoring Available (R)

0F_0H

1 = Performance monitoring enabled.

0 = Performance monitoring disabled.

10:8

Reserved.

Vol. 4

2-17

MODEL-SPECIFIC REGISTERS (MSRS)

Table 2-2. IA-32 Architectural MSRs (Contd.)

Register Address: Hex, Decimal

Architectural MSR Name (Former MSR Name)

Bit Fields

MSR/Bit Description

Comment

11

Branch Trace Storage Unavailable (R/O)

0F_0H

1 = Processor doesn’t support branch trace storage (BTS).

0 = BTS is supported.

12

Processor Event Based Sampling (PEBS) Unavailable (R/O)

06_0FH

1 = PEBS is not supported.

0 = PEBS is supported.

15:13

Reserved.

16

Enhanced Intel SpeedStep Technology Enable (R/W)

If CPUID.01H: ECX[7] =1

0= Enhanced Intel SpeedStep Technology disabled.

1 = Enhanced Intel SpeedStep Technology enabled.

17

Reserved.

18

ENABLE MONITOR FSM (R/W)

0F_03H

When this bit is set to 0, the MONITOR feature flag is not set

(CPUID.01H:ECX[bit 3] = 0). This indicates that MONITOR/MWAIT are not

supported.

Software attempts to execute MONITOR/MWAIT will cause #UD when

this bit is 0.

When this bit is set to 1 (default), MONITOR/MWAIT are supported

(CPUID.01H:ECX[bit 3] = 1).

If the SSE3 feature flag ECX[0] is not set (CPUID.01H:ECX[bit 0] = 0), the

OS must not attempt to alter this bit. BIOS must leave it in the default

state. Writing this bit when the SSE3 feature flag is set to 0 may

generate a #GP exception.

21:19

Reserved.

22

Limit CPUID Maxval (R/W)

0F_03H

When this bit is set to 1, CPUID.00H returns a maximum value in

EAX[7:0] of 2.

BIOS should contain a setup question that allows users to specify when

the installed OS does not support CPUID functions greater than 2.

Before setting this bit, BIOS must execute the CPUID.0H and examine

the maximum value returned in EAX[7:0]. If the maximum value is

greater than 2, this bit is supported.

Otherwise, this bit is not supported. Setting this bit when the maximum

value is not greater than 2 may generate a #GP exception.

Setting this bit may cause unexpected behavior in software that

depends on the availability of CPUID leaves greater than 2.

23

xTPR Message Disable (R/W)

If CPUID.01H:ECX[14] = 1

When set to 1, xTPR messages are disabled. xTPR messages are optional

messages that allow the processor to inform the chipset of its priority.

63:24

Reserved.

Note: Some older processors defined one of these bits as a disable for

the execute-disable feature of paging. If a processor supports this bit,

this information is provided in the model-specific tables. See Table 2-3

for the definition of this bit.

Register Address: 1B0H, 432

IA32_ENERGY_PERF_BIAS

2-18 Vol. 4

MODEL-SPECIFIC REGISTERS (MSRS)

Table 2-2. IA-32 Architectural MSRs (Contd.)

Register Address: Hex, Decimal

Architectural MSR Name (Former MSR Name)

Bit Fields

MSR/Bit Description

Comment

Performance Energy Bias Hint (R/W)

If CPUID.6H:ECX[3] = 1

3:0

Power Policy Preference:

0 indicates preference to highest performance.

15 indicates preference to maximize energy saving.

63:4

Reserved.

Register Address: 1B1H, 433

IA32_PACKAGE_THERM_STATUS

Package Thermal Status Information (R/O)

If CPUID.06H: EAX[6] = 1

Contains status information about the package’s thermal sensor.

See Section 15.9, “Package Level Thermal Management.”

0

Pkg Thermal Status (R/O)

1

Pkg Thermal Status Log (R/W)

2

Pkg PROCHOT # event. (R/O)

3

Pkg PROCHOT # log. (R/WC0)

4

Pkg Critical Temperature Status. (R/O)

5

Pkg Critical Temperature Status Log. (R/WC0)

6

Pkg Thermal Threshold #1 Status. (R/O)

7

Pkg Thermal Threshold #1 Log. (R/WC0)

8

Pkg Thermal Threshold #2 Status. (R/O)

9

Pkg Thermal Threshold #1 Log. (R/WC0)

10

Pkg Power Limitation Status. (R/O)

11

Pkg Power Limitation Log. (R/WC0)

15:12

Reserved.

22:16

Pkg Digital Readout. (R/O)

25:23

Reserved.

26

Hardware Feedback Interface Structure Change Status.

If CPUID.06H:EAX.[19] = 1

63:27

Reserved.

Register Address: 1B2H, 434

IA32_PACKAGE_THERM_INTERRUPT

Pkg Thermal Interrupt Control (R/W)

If CPUID.06H: EAX[6] = 1

Enables and disables the generation of an interrupt on temperature transitions detected with the

package’s thermal sensor.

See Section 15.9, “Package Level Thermal Management.”

0

Pkg High-Temperature Interrupt Enable.

1

Pkg Low-Temperature Interrupt Enable.

2

Pkg PROCHOT# Interrupt Enable.

3

Reserved.

4

Pkg Overheat Interrupt Enable.

7:5

Reserved.

14:8

Pkg Threshold #1 Value.

15

Pkg Threshold #1 Interrupt Enable.

Vol. 4

2-19

MODEL-SPECIFIC REGISTERS (MSRS)

Table 2-2. IA-32 Architectural MSRs (Contd.)

Register Address: Hex, Decimal

Architectural MSR Name (Former MSR Name)

Bit Fields

MSR/Bit Description

Comment

22:16

Pkg Threshold #2 Value.

23

Pkg Threshold #2 Interrupt Enable.

24

Pkg Power Limit Notification Enable.

25

Hardware Feedback Interrupt Enable.

If CPUID.06H:EAX.[19] = 1

63:26

Reserved.

Register Address: 1C4H, 452

IA32_XFD

Extended Feature Disable Control (R/W)

If CPUID.(EAX=0DH,ECX=1):

Controls which XSAVE-enabled features are temporarily disabled.

EAX[4] = 1

See Section 13.14 of the Intel^® 64 and IA-32 Architectures Software Developer’s Manual,

Volume 1.

Register Address: 1C5H, 453

IA32_XFD_ERR

Extended Feature Disable Error Code (R/W)

If CPUID.(EAX=0DH,ECX=1):

EAX[4] = 1

Reports which XSAVE-enabled features caused a fault due to being disabled.

See Section 13.14 of the Intel^® 64 and IA-32 Architectures Software Developer’s Manual,

Volume 1.

Register Address: 1D9H, 473

IA32_DEBUGCTL (MSR_DEBUGCTLA, MSR_DEBUGCTLB)

Trace/Profile Resource Control (R/W)

06_0EH

0

LBR: Setting this bit to 1 enables the processor to record a running trace

06_01H

of the most recent branches taken by the processor in the LBR stack.

1

BTF: Setting this bit to 1 enables the processor to treat EFLAGS.TF as

06_01H

single-step on branches instead of single-step on instructions.

2

BLD: Enable OS bus-lock detection. See Section 18.3.1.6 of the Intel^® 64

If (CPUID.(EAX=07H,

and IA-32 Architectures Software Developer’s Manual, Volume 3B.

ECX=0):ECX[24] = 1)

5:3

Reserved.

6

TR: Setting this bit to 1 enables branch trace messages to be sent.

06_0EH

7

BTS: Setting this bit enables branch trace messages (BTMs) to be logged

06_0EH

in a BTS buffer.

8

BTINT: When clear, BTMs are logged in a BTS buffer in circular fashion.

06_0EH

When this bit is set, an interrupt is generated by the BTS facility when

the BTS buffer is full.

9

1: BTS_OFF_OS: When set, BTS or BTM is skipped if CPL = 0.

06_0FH

10

BTS_OFF_USR: When set, BTS or BTM is skipped if CPL > 0.

06_0FH

11

FREEZE_LBRS_ON_PMI: When set, the LBR stack is frozen on a PMI

If CPUID.01H: ECX[15] = 1 &&

request.

CPUID.0AH: EAX[7:0] > 1

12

FREEZE_PERFMON_ON_PMI: When set, each ENABLE bit of the global

If CPUID.01H: ECX[15] = 1 &&

counter control MSR are frozen (address 38FH) on a PMI request.

CPUID.0AH: EAX[7:0] > 1

13

ENABLE_UNCORE_PMI: When set, enables the logical processor to

06_1AH

receive and generate PMI on behalf of the uncore.

14

FREEZE_WHILE_SMM: When set, freezes perfmon and trace messages

If IA32_PERF_CAPABILITIES[12]

while in SMM.

= 1

15

RTM_DEBUG: When set, enables DR7 debug bit on XBEGIN.

If (CPUID.(EAX=07H,

ECX=0):EBX[11] = 1)

2-20 Vol. 4

MODEL-SPECIFIC REGISTERS (MSRS)

Table 2-2. IA-32 Architectural MSRs (Contd.)

Register Address: Hex, Decimal

Architectural MSR Name (Former MSR Name)

Bit Fields

MSR/Bit Description

Comment

63:16

Reserved.

Register Address: 1DDH, 477

IA32_LER_FROM_IP

Last Event Record Source IP Register (R/W)

63:0

FROM_IP

Reset Value: 0

The source IP of the recorded branch or event, in canonical form.

Register Address: 1DEH, 478

IA32_LER_TO_IP

Last Event Record Destination IP Register (R/W)

63:0

TO_IP

Reset Value: 0

The destination IP of the recorded branch or event, in canonical form.

Register Address: 1E0H, 480

IA32_LER_INFO

Last Event Record Info Register (R/W)

55:0

Undefined, may be zero or non-zero. Writes of non- zero values do not

Reset Value: 0

fault, but reads may return a different value.

59:56

BR_TYPE

Reset Value: 0

The branch type recorded by this LBR. Encodings match those of

IA32_LBR_x_INFO.

60

Undefined, may be zero or non-zero. Writes of non- zero values do not

Reset Value: 0

fault, but reads may return a different value.

61

TSX_ABORT

Reset Value: 0

This LBR record is a TSX abort. On processors that do not support Intel®

TSX (CPUID.07H.EBX.HLE[bit 4]=0 and CPUID.07H.EBX.RTM[bit 11]=0),

this bit is undefined.

62

IN_TSX

Reset Value: 0

This LBR record records a branch that retired during a TSX transaction.

On processors that do not support Intel® TSX (CPUID.07H.EBX.HLE[bit

4]=0 and CPUID.07H.EBX.RTM[bit 11]=0), this bit is undefined.

63

MISPRED

Reset Value: 0

The recorded branch taken/not-taken resolution (for conditional

branches) or target (for any indirect branch, including RETs) was

mispredicted.

Register Address: 1F2H, 498

IA32_SMRR_PHYSBASE

SMRR Base Address (Writeable only in SMM)

If IA32_MTRRCAP.SMRR[11] = 1

Base address of SMM memory range.

7:0

Type. Specifies memory type of the range.

11:8

Reserved.

31:12

PhysBase

SMRR physical Base Address.

63:32

Reserved.

Register Address: 1F3H, 499

IA32_SMRR_PHYSMASK

SMRR Range Mask (Writeable only in SMM)

If IA32_MTRRCAP[SMRR] = 1

Range Mask of SMM memory range.

Vol. 4

2-21

MODEL-SPECIFIC REGISTERS (MSRS)

Table 2-2. IA-32 Architectural MSRs (Contd.)

Register Address: Hex, Decimal

Architectural MSR Name (Former MSR Name)

Bit Fields

MSR/Bit Description

Comment

10:0

Reserved.

11

Valid

Enable range mask.

31:12

PhysMask

SMRR address range mask.

63:32

Reserved.

Register Address: 1F8H, 504

IA32_PLATFORM_DCA_CAP

DCA Capability (R)

If CPUID.01H: ECX[18] = 1

Register Address: 1F9H, 505

IA32_CPU_DCA_CAP

If set, CPU supports Prefetch-Hint type.

If CPUID.01H: ECX[18] = 1

Register Address: 1FAH, 506

IA32_DCA_0_CAP

DCA type 0 Status and Control register.

If CPUID.01H: ECX[18] = 1

0

DCA_ACTIVE: Set by HW when DCA is fuse-enabled and no defeatures

are set.

2:1

TRANSACTION

6:3

DCA_TYPE

10:7

DCA_QUEUE_SIZE

12:11

Reserved.

16:13

DCA_DELAY: Writes will update the register but have no HW side-effect.

23:17

Reserved.

24

SW_BLOCK: SW can request DCA block by setting this bit.

25

Reserved.

26

HW_BLOCK: Set when DCA is blocked by HW (e.g., CR0.CD = 1).

31:27

Reserved.

Register Address: 200H, 512

IA32_MTRR_PHYSBASE0 (MTRRphysBase0)

See Section 12.11.2.3, “Variable Range MTRRs.”

If IA32_MTRRCAP[7:0] > 0

Register Address: 201H, 513

IA32_MTRR_PHYSMASK0

MTRRphysMask0

If IA32_MTRRCAP[7:0] > 0

Register Address: 202H, 514

IA32_MTRR_PHYSBASE1

MTRRphysBase1

If IA32_MTRRCAP[7:0] > 1

Register Address: 203H, 515

IA32_MTRR_PHYSMASK1

MTRRphysMask1

If IA32_MTRRCAP[7:0] > 1

Register Address: 204H, 516

IA32_MTRR_PHYSBASE2

MTRRphysBase2

If IA32_MTRRCAP[7:0] > 2

Register Address: 205H, 517

IA32_MTRR_PHYSMASK2

MTRRphysMask2

If IA32_MTRRCAP[7:0] > 2

Register Address: 206H, 518

IA32_MTRR_PHYSBASE3

MTRRphysBase3

If IA32_MTRRCAP[7:0] > 3

2-22 Vol. 4

MODEL-SPECIFIC REGISTERS (MSRS)

Table 2-2. IA-32 Architectural MSRs (Contd.)

Register Address: Hex, Decimal

Architectural MSR Name (Former MSR Name)

Bit Fields

MSR/Bit Description

Comment

Register Address: 207H, 519

IA32_MTRR_PHYSMASK3

MTRRphysMask3

If IA32_MTRRCAP[7:0] > 3

Register Address: 208H, 520

IA32_MTRR_PHYSBASE4

MTRRphysBase4

If IA32_MTRRCAP[7:0] > 4

Register Address: 209H, 521

IA32_MTRR_PHYSMASK4

MTRRphysMask4

If IA32_MTRRCAP[7:0] > 4

Register Address: 20AH, 522

IA32_MTRR_PHYSBASE5

MTRRphysBase5

If IA32_MTRRCAP[7:0] > 5

Register Address: 20BH, 523

IA32_MTRR_PHYSMASK5

MTRRphysMask5

If IA32_MTRRCAP[7:0] > 5

Register Address: 20CH, 524

IA32_MTRR_PHYSBASE6

MTRRphysBase6

If IA32_MTRRCAP[7:0] > 6

Register Address: 20DH, 525

IA32_MTRR_PHYSMASK6

MTRRphysMask6

If IA32_MTRRCAP[7:0] > 6

Register Address: 20EH, 526

IA32_MTRR_PHYSBASE7

MTRRphysBase7

If IA32_MTRRCAP[7:0] > 7

Register Address: 20FH, 527

IA32_MTRR_PHYSMASK7

MTRRphysMask7

If IA32_MTRRCAP[7:0] > 7

Register Address: 210H, 528

IA32_MTRR_PHYSBASE8

MTRRphysBase8

If IA32_MTRRCAP[7:0] > 8

Register Address: 211H, 529

IA32_MTRR_PHYSMASK8

MTRRphysMask8

If IA32_MTRRCAP[7:0] > 8

Register Address: 212H, 530

IA32_MTRR_PHYSBASE9

MTRRphysBase9

If IA32_MTRRCAP[7:0] > 9

Register Address: 213H, 531

IA32_MTRR_PHYSMASK9

MTRRphysMask9

If IA32_MTRRCAP[7:0] > 9

Register Address: 250H, 592

IA32_MTRR_FIX64K_00000

MTRRfix64K_00000

If CPUID.01H: EDX.MTRR[12] =1

Register Address: 258H, 600

IA32_MTRR_FIX16K_80000

MTRRfix16K_80000

If CPUID.01H: EDX.MTRR[12] =1

Register Address: 259H, 601

IA32_MTRR_FIX16K_A0000

MTRRfix16K_A0000

If CPUID.01H: EDX.MTRR[12] =1

Register Address: 268H, 616

IA32_MTRR_FIX4K_C0000 (MTRRfix4K_C0000)

See Section 12.11.2.2, “Fixed Range MTRRs.”

If CPUID.01H: EDX.MTRR[12] =1

Register Address: 269H, 617

IA32_MTRR_FIX4K_C8000

MTRRfix4K_C8000

If CPUID.01H: EDX.MTRR[12] =1

Register Address: 26AH, 618

IA32_MTRR_FIX4K_D0000

Vol. 4

2-23

MODEL-SPECIFIC REGISTERS (MSRS)

Table 2-2. IA-32 Architectural MSRs (Contd.)

Register Address: Hex, Decimal

Architectural MSR Name (Former MSR Name)

Bit Fields

MSR/Bit Description

Comment

MTRRfix4K_D0000

If CPUID.01H: EDX.MTRR[12] =1

Register Address: 26BH, 619

IA32_MTRR_FIX4K_D8000

MTRRfix4K_D8000

If CPUID.01H: EDX.MTRR[12] =1

Register Address: 26CH, 620

IA32_MTRR_FIX4K_E0000

MTRRfix4K_E0000

If CPUID.01H: EDX.MTRR[12] =1

Register Address: 26DH, 621

IA32_MTRR_FIX4K_E8000

MTRRfix4K_E8000

If CPUID.01H: EDX.MTRR[12] =1

Register Address: 26EH, 622

IA32_MTRR_FIX4K_F0000

MTRRfix4K_F0000

If CPUID.01H: EDX.MTRR[12] =1

Register Address: 26FH, 623

IA32_MTRR_FIX4K_F8000

MTRRfix4K_F8000.

If CPUID.01H: EDX.MTRR[12] =1

Register Address: 277H, 631

IA32_PAT

IA32_PAT (R/W)

If CPUID.01H: EDX.MTRR[16] =1

2:0

PA0

7:3

Reserved.

10:8

PA1

15:11

Reserved.

18:16

PA2

23:19

Reserved.

26:24

PA3

31:27

Reserved.

34:32

PA4

39:35

Reserved.

42:40

PA5

47:43

Reserved.

50:48

PA6

55:51

Reserved.

58:56

PA7

63:59

Reserved.

Register Address: 280H, 640

IA32_MC0_CTL2

MSR to enable/disable CMCI capability for bank 0. (R/W)

If IA32_MCG_CAP[10] = 1 &&

IA32_MCG_CAP[7:0] > 0

See Section 16.3.2.5, “IA32_MCi_CTL2 MSRs.”

14:0

Corrected error count threshold.

29:15

Reserved.

30

CMCI_EN

63:31

Reserved.

Register Address: 281H, 641

IA32_MC1_CTL2

2-24 Vol. 4

MODEL-SPECIFIC REGISTERS (MSRS)

Table 2-2. IA-32 Architectural MSRs (Contd.)

Register Address: Hex, Decimal

Architectural MSR Name (Former MSR Name)

Bit Fields

MSR/Bit Description

Comment

Same fields as IA32_MC0_CTL2. (R/W)

If IA32_MCG_CAP[10] = 1 &&

IA32_MCG_CAP[7:0] > 1

Register Address: 282H, 642

IA32_MC2_CTL2

Same fields as IA32_MC0_CTL2. (R/W)

If IA32_MCG_CAP[10] = 1 &&

IA32_MCG_CAP[7:0] > 2

Register Address: 283H, 643

IA32_MC3_CTL2

Same fields as IA32_MC0_CTL2. (R/W)

If IA32_MCG_CAP[10] = 1 &&

IA32_MCG_CAP[7:0] > 3

Register Address: 284H, 644

IA32_MC4_CTL2

Same fields as IA32_MC0_CTL2. (R/W)

If IA32_MCG_CAP[10] = 1 &&

IA32_MCG_CAP[7:0] > 4

Register Address: 285H, 645

IA32_MC5_CTL2

Same fields as IA32_MC0_CTL2. (R/W)

If IA32_MCG_CAP[10] = 1 &&

IA32_MCG_CAP[7:0] > 5

Register Address: 286H, 646

IA32_MC6_CTL2

Same fields as IA32_MC0_CTL2. (R/W)

If IA32_MCG_CAP[10] = 1 &&

IA32_MCG_CAP[7:0] > 6

Register Address: 287H, 647

IA32_MC7_CTL2

Same fields as IA32_MC0_CTL2. (R/W)

If IA32_MCG_CAP[10] = 1 &&

IA32_MCG_CAP[7:0] > 7

Register Address: 288H, 648

IA32_MC8_CTL2

Same fields as IA32_MC0_CTL2. (R/W)

If IA32_MCG_CAP[10] = 1 &&

IA32_MCG_CAP[7:0] > 8

Register Address: 289H, 649

IA32_MC9_CTL2

Same fields as IA32_MC0_CTL2. (R/W)

If IA32_MCG_CAP[10] = 1 &&

IA32_MCG_CAP[7:0] > 9

Register Address: 28AH, 650

IA32_MC10_CTL2

Same fields as IA32_MC0_CTL2. (R/W)

If IA32_MCG_CAP[10] = 1 &&

IA32_MCG_CAP[7:0] > 10

Register Address: 28BH, 651

IA32_MC11_CTL2

Same fields as IA32_MC0_CTL2. (R/W)

If IA32_MCG_CAP[10] = 1 &&

IA32_MCG_CAP[7:0] > 11

Register Address: 28CH, 652

IA32_MC12_CTL2

Same fields as IA32_MC0_CTL2. (R/W)

If IA32_MCG_CAP[10] = 1 &&

IA32_MCG_CAP[7:0] > 12

Register Address: 28DH, 653

IA32_MC13_CTL2

Same fields as IA32_MC0_CTL2. (R/W)

If IA32_MCG_CAP[10] = 1 &&

IA32_MCG_CAP[7:0] > 13

Register Address: 28EH, 654

IA32_MC14_CTL2

Same fields as IA32_MC0_CTL2. (R/W)

If IA32_MCG_CAP[10] = 1 &&

IA32_MCG_CAP[7:0] > 14

Register Address: 28FH, 655

IA32_MC15_CTL2

Vol. 4

2-25

MODEL-SPECIFIC REGISTERS (MSRS)

Table 2-2. IA-32 Architectural MSRs (Contd.)

Register Address: Hex, Decimal

Architectural MSR Name (Former MSR Name)

Bit Fields

MSR/Bit Description

Comment

Same fields as IA32_MC0_CTL2. (R/W)

If IA32_MCG_CAP[10] = 1 &&

IA32_MCG_CAP[7:0] > 15

Register Address: 290H, 656

IA32_MC16_CTL2

Same fields as IA32_MC0_CTL2. (R/W)

If IA32_MCG_CAP[10] = 1 &&

IA32_MCG_CAP[7:0] > 16

Register Address: 291H, 657

IA32_MC17_CTL2

Same fields as IA32_MC0_CTL2. (R/W)

If IA32_MCG_CAP[10] = 1 &&

IA32_MCG_CAP[7:0] > 17

Register Address: 292H, 658

IA32_MC18_CTL2

Same fields as IA32_MC0_CTL2. (R/W)

If IA32_MCG_CAP[10] = 1 &&

IA32_MCG_CAP[7:0] > 18

Register Address: 293H, 659

IA32_MC19_CTL2

Same fields as IA32_MC0_CTL2. (R/W)

If IA32_MCG_CAP[10] = 1 &&

IA32_MCG_CAP[7:0] > 19

Register Address: 294H, 660

IA32_MC20_CTL2

Same fields as IA32_MC0_CTL2. (R/W)

If IA32_MCG_CAP[10] = 1 &&

IA32_MCG_CAP[7:0] > 20

Register Address: 295H, 661

IA32_MC21_CTL2

Same fields as IA32_MC0_CTL2. (R/W)

If IA32_MCG_CAP[10] = 1 &&

IA32_MCG_CAP[7:0] > 21

Register Address: 296H, 662

IA32_MC22_CTL2

Same fields as IA32_MC0_CTL2. (R/W)

If IA32_MCG_CAP[10] = 1 &&

IA32_MCG_CAP[7:0] > 22

Register Address: 297H, 663

IA32_MC23_CTL2

Same fields as IA32_MC0_CTL2. (R/W)

If IA32_MCG_CAP[10] = 1 &&

IA32_MCG_CAP[7:0] > 23

Register Address: 298H, 664

IA32_MC24_CTL2

Same fields as IA32_MC0_CTL2. (R/W)

If IA32_MCG_CAP[10] = 1 &&

IA32_MCG_CAP[7:0] > 24

Register Address: 299H, 665

IA32_MC25_CTL2

Same fields as IA32_MC0_CTL2. (R/W)

If IA32_MCG_CAP[10] = 1 &&

IA32_MCG_CAP[7:0] > 25

Register Address: 29AH, 666

IA32_MC26_CTL2

Same fields as IA32_MC0_CTL2. (R/W)

If IA32_MCG_CAP[10] = 1 &&

IA32_MCG_CAP[7:0] > 26

Register Address: 29BH, 667

IA32_MC27_CTL2

Same fields as IA32_MC0_CTL2. (R/W)

If IA32_MCG_CAP[10] = 1 &&

IA32_MCG_CAP[7:0] > 27

Register Address: 29CH, 668

IA32_MC28_CTL2

Same fields as IA32_MC0_CTL2. (R/W)

If IA32_MCG_CAP[10] = 1 &&

IA32_MCG_CAP[7:0] > 28

Register Address: 29DH, 669

IA32_MC29_CTL2

2-26 Vol. 4

MODEL-SPECIFIC REGISTERS (MSRS)

Table 2-2. IA-32 Architectural MSRs (Contd.)

Register Address: Hex, Decimal

Architectural MSR Name (Former MSR Name)

Bit Fields

MSR/Bit Description

Comment

Same fields as IA32_MC0_CTL2. (R/W)

If IA32_MCG_CAP[10] = 1 &&

IA32_MCG_CAP[7:0] > 29

Register Address: 29EH, 670

IA32_MC30_CTL2

Same fields as IA32_MC0_CTL2. (R/W)

If IA32_MCG_CAP[10] = 1 &&

IA32_MCG_CAP[7:0] > 30

Register Address: 29FH, 671

IA32_MC31_CTL2

Same fields as IA32_MC0_CTL2. (R/W)

If IA32_MCG_CAP[10] = 1 &&

IA32_MCG_CAP[7:0] > 31

Register Address: 2FFH, 767

IA32_MTRR_DEF_TYPE

MTRRdefType (R/W)

If CPUID.01H: EDX.MTRR[12] =1

2:0

Default Memory Type

9:3

Reserved.

10

Fixed Range MTRR Enable

11

MTRR Enable

63:12

Reserved.

Register Address: 309H, 777

IA32_FIXED_CTR0

Fixed-Function Performance Counter 0 (R/W): Counts Instr_Retired.Any.

If CPUID.0AH: EDX[4:0] > 0

Register Address: 30AH, 778

IA32_FIXED_CTR1

Fixed-Function Performance Counter 1 (R/W): Counts CPU_CLK_Unhalted.Core.

If CPUID.0AH: EDX[4:0] > 1

Register Address: 30BH, 779

IA32_FIXED_CTR2

Fixed-Function Performance Counter 2 (R/W): Counts CPU_CLK_Unhalted.Ref.

If CPUID.0AH: EDX[4:0] > 2

Register Address: 345H, 837

IA32_PERF_CAPABILITIES

Read Only MSR that enumerates the existence of performance monitoring features. (R/O)

If CPUID.01H: ECX[15] = 1

5:0

LBR format

6

PEBS Trap

7

PEBSSaveArchRegs

11:8

PEBS Record Format

12

1: Freeze while SMM is supported.

13

1: Full width of counter writable via IA32_A_PMCx.

14

PEBS_BASELINE

15

1: Performance metrics available.

16

1: PEBS output will be written into the Intel PT trace stream.

If CPUID.0x7.0.EBX[25]=1

63:17

Reserved.

Register Address: 38DH, 909

IA32_FIXED_CTR_CTRL

Fixed-Function Performance Counter Control (R/W)

If CPUID.0AH: EAX[7:0] > 1

Counter increments while the results of ANDing respective enable bit in

IA32_PERF_GLOBAL_CTRL with the corresponding OS or USR bits in this MSR is true.

0

EN0_OS: Enable Fixed Counter 0 to count while CPL = 0.

1

EN0_Usr: Enable Fixed Counter 0 to count while CPL > 0.

Vol. 4

2-27

MODEL-SPECIFIC REGISTERS (MSRS)

Table 2-2. IA-32 Architectural MSRs (Contd.)

Register Address: Hex, Decimal

Architectural MSR Name (Former MSR Name)

Bit Fields

MSR/Bit Description

Comment

2

AnyThr0: When set to 1, it enables counting the associated event

If CPUID.0AH:EAX[7:0] > 2 &&

conditions occurring across all logical processors sharing a processor

CPUID.0AH:EDX[15]=0

core. When set to 0, the counter only increments the associated event

conditions occurring in the logical processor which programmed the MSR.

3

EN0_PMI: Enable PMI when fixed counter 0 overflows.

4

EN1_OS: Enable Fixed Counter 1to count while CPL = 0.

5

EN1_Usr: Enable Fixed Counter 1to count while CPL > 0.

6

AnyThr1: When set to 1, it enables counting the associated event

If CPUID.0AH:EAX[7:0] > 2 &&

conditions occurring across all logical processors sharing a processor

CPUID.0AH:EDX[15]=0

core. When set to 0, the counter only increments the associated event

conditions occurring in the logical processor which programmed the MSR.

7

EN1_PMI: Enable PMI when fixed counter 1 overflows.

8

EN2_OS: Enable Fixed Counter 2 to count while CPL = 0.

9

EN2_Usr: Enable Fixed Counter 2 to count while CPL > 0.

10

AnyThr2: When set to 1, it enables counting the associated event

If CPUID.0AH:EAX[7:0] > 2 &&

conditions occurring across all logical processors sharing a processor

CPUID.0AH:EDX[15]=0

core. When set to 0, the counter only increments the associated event

conditions occurring in the logical processor which programmed the MSR.

11

EN2_PMI: Enable PMI when fixed counter 2 overflows.

12

EN3_OS: Enable Fixed Counter 3 to count while CPL = 0.

13

EN3_Usr: Enable Fixed Counter 3 to count while CPL > 0.

14

Reserved.

15

EN3_PMI: Enable PMI when fixed counter 3 overflows.

63:16

Reserved.

Register Address: 38EH, 910

IA32_PERF_GLOBAL_STATUS

Global Performance Counter Status (R/O)

If CPUID.0AH: EAX[7:0] > 0 II

(CPUID.(EAX=07H,

ECX=0):EBX[25] = 1 &&

CPUID.(EAX=014H, ECX=0):ECX[0]

= 1)

0

Ovf_PMC0: Overflow status of IA32_PMC0.

If CPUID.0AH: EAX[15:8] > 0

1

Ovf_PMC1: Overflow status of IA32_PMC1.

If CPUID.0AH: EAX[15:8] > 1

2

Ovf_PMC2: Overflow status of IA32_PMC2.

If CPUID.0AH: EAX[15:8] > 2

3

Ovf_PMC3: Overflow status of IA32_PMC3.

If CPUID.0AH: EAX[15:8] > 3

n

Ovf_PMCn: Overflow status of IA32_PMCn.

If CPUID.0AH: EAX[15:8] > n

31:n+1

Reserved.

32

Ovf_FixedCtr0: Overflow status of IA32_FIXED_CTR0.

If CPUID.0AH: EAX[7:0] > 1

33

Ovf_FixedCtr1: Overflow status of IA32_FIXED_CTR1.

If CPUID.0AH: EAX[7:0] > 1

34

Ovf_FixedCtr2: Overflow status of IA32_FIXED_CTR2.

If CPUID.0AH: EAX[7:0] > 1

47:35

Reserved.

2-28 Vol. 4

MODEL-SPECIFIC REGISTERS (MSRS)

Table 2-2. IA-32 Architectural MSRs (Contd.)

Register Address: Hex, Decimal

Architectural MSR Name (Former MSR Name)

Bit Fields

MSR/Bit Description

Comment

48

OVF_PERF_METRICS: If this bit is set, it indicates that PERF_METRIC

counter has overflowed and a PMI is triggered; however, an overflow of

fixed counter 3 should normally happen first. If this bit is clear no

overflow occurred.

54:49

Reserved.

55

Trace_ToPA_PMI: A PMI occurred due to a ToPA entry memory buffer

If CPUID.(EAX=07H,

that was completely filled.

ECX=0):EBX[25] = 1 &&

CPUID.(EAX=014H, ECX=0):ECX[0]

= 1

57:56

Reserved.

58

LBR_Frz. LBRs are frozen due to:

If CPUID.0AH: EAX[7:0] > 3

• IA32_DEBUGCTL.FREEZE_LBR_ON_PMI=1.

• The LBR stack overflowed.

59

CTR_Frz. Performance counters in the core PMU are frozen due to:

If CPUID.0AH: EAX[7:0] > 3

• IA32_DEBUGCTL.FREEZE_PERFMON_ON_PMI=1.

• One or more core PMU counters overflowed.

60

ASCI: Data in the performance counters in the core PMU may include

If CPUID.(EAX=07H,

contributions from the direct or indirect operation Intel SGX to protect an

ECX=0):EBX[2] = 1

enclave.

61

Ovf_Uncore: Uncore counter overflow status.

If CPUID.0AH: EAX[7:0] > 2

62

OvfBuf: DS SAVE area Buffer overflow status.

If CPUID.0AH: EAX[7:0] > 0

63

CondChgd: Status bits of this register have changed.

If CPUID.0AH: EAX[7:0] > 0

Register Address: 38FH, 911

IA32_PERF_GLOBAL_CTRL

Global Performance Counter Control (R/W)

If CPUID.0AH: EAX[7:0] > 0

Counter increments while the result of ANDing the respective enable bit in this MSR with the

corresponding OS or USR bits in the general-purpose or fixed counter control MSR is true.

0

EN_PMC0

If CPUID.0AH: EAX[15:8] > 0

1

EN_PMC1

If CPUID.0AH: EAX[15:8] > 1

2

EN_PMC2

If CPUID.0AH: EAX[15:8] > 2

n

EN_PMCn

If CPUID.0AH: EAX[15:8] > n

31:n+1

Reserved.

32

EN_FIXED_CTR0

If CPUID.0AH: EDX[4:0] > 0

33

EN_FIXED_CTR1

If CPUID.0AH: EDX[4:0] > 1

34

EN_FIXED_CTR2

If CPUID.0AH: EDX[4:0] > 2

47:35

Reserved.

48

EN_PERF_METRICS: If this bit is set and fixed counter 3 is effectively

enabled, built-in performance metrics are enabled.

63:49

Reserved.

Register Address: 390H, 912

IA32_PERF_GLOBAL_OVF_CTRL

Global Performance Counter Overflow Control (R/W)

If CPUID.0AH: EAX[7:0] > 0 &&

CPUID.0AH: EAX[7:0] <= 3

0

Set 1 to Clear Ovf_PMC0 bit.

If CPUID.0AH: EAX[15:8] > 0

Vol. 4

2-29

MODEL-SPECIFIC REGISTERS (MSRS)

Table 2-2. IA-32 Architectural MSRs (Contd.)

Register Address: Hex, Decimal

Architectural MSR Name (Former MSR Name)

Bit Fields

MSR/Bit Description

Comment

1

Set 1 to Clear Ovf_PMC1 bit.

If CPUID.0AH: EAX[15:8] > 1

2

Set 1 to Clear Ovf_PMC2 bit.

If CPUID.0AH: EAX[15:8] > 2

n

Set 1 to Clear Ovf_PMCn bit.

If CPUID.0AH: EAX[15:8] > n

31:n

Reserved.

32

Set 1 to Clear Ovf_FIXED_CTR0 bit.

If CPUID.0AH: EDX[4:0] > 0

33

Set 1 to Clear Ovf_FIXED_CTR1 bit.

If CPUID.0AH: EDX[4:0] > 1

34

Set 1 to Clear Ovf_FIXED_CTR2 bit.

If CPUID.0AH: EDX[4:0] > 2

54:35

Reserved.

55

Set 1 to Clear Trace_ToPA_PMI bit.

If (CPUID.(EAX=07H,

ECX=0):EBX[25] = 1) &&

IA32_RTIT_CTL.ToPA = 1

60:56

Reserved.

61

Set 1 to Clear Ovf_Uncore bit.

06_2EH

62

Set 1 to Clear OvfBuf bit.

If CPUID.0AH: EAX[7:0] > 0

63

Set 1 to clear CondChgd bit.

If CPUID.0AH: EAX[7:0] > 0

Register Address: 390H, 912

IA32_PERF_GLOBAL_STATUS_RESET

Global Performance Counter Overflow Reset Control (R/W)

If CPUID.0AH: EAX[7:0] > 3 II

(CPUID.(EAX=07H,

ECX=0):EBX[25] = 1 &&

CPUID.(EAX=014H, ECX=0):ECX[0]

= 1)

0

Set 1 to Clear Ovf_PMC0 bit.

If CPUID.0AH: EAX[15:8] > 0

1

Set 1 to Clear Ovf_PMC1 bit.

If CPUID.0AH: EAX[15:8] > 1

2

Set 1 to Clear Ovf_PMC2 bit.

If CPUID.0AH: EAX[15:8] > 2

n

Set 1 to Clear Ovf_PMCn bit.

If CPUID.0AH: EAX[15:8] > n

31:n

Reserved.

32

Set 1 to Clear Ovf_FIXED_CTR0 bit.

If CPUID.0AH: EDX[4:0] > 0

33

Set 1 to Clear Ovf_FIXED_CTR1 bit.

If CPUID.0AH: EDX[4:0] > 1

34

Set 1 to Clear Ovf_FIXED_CTR2 bit.

If CPUID.0AH: EDX[4:0] > 2

47:35

Reserved.

48

RESET_OVF_PERF_METRICS: If this bit is set, it will clear the status bit in

the IA32_PERF_GLOBAL_STATUS register for the PERF_METRICS

counters.

54:49

Reserved.

55

Set 1 to Clear Trace_ToPA_PMI bit.

If CPUID.(EAX=07H,

ECX=0):EBX[25] = 1 &&

CPUID.(EAX=014H, ECX=0):ECX[0]

= 1

57:56

Reserved.

58

Set 1 to Clear LBR_Frz bit.

If CPUID.0AH: EAX[7:0] > 3

59

Set 1 to Clear CTR_Frz bit.

If CPUID.0AH: EAX[7:0] > 3

2-30 Vol. 4

MODEL-SPECIFIC REGISTERS (MSRS)

Table 2-2. IA-32 Architectural MSRs (Contd.)

Register Address: Hex, Decimal

Architectural MSR Name (Former MSR Name)

Bit Fields

MSR/Bit Description

Comment

58

Set 1 to Clear ASCI bit.

If CPUID.0AH: EAX[7:0] > 3

61

Set 1 to Clear Ovf_Uncore bit.

06_2EH

62

Set 1 to Clear OvfBuf bit.

If CPUID.0AH: EAX[7:0] > 0

63

Set 1 to clear CondChgd bit.

If CPUID.0AH: EAX[7:0] > 0

Register Address: 391H, 913

IA32_PERF_GLOBAL_STATUS_SET

Global Performance Counter Overflow Set Control (R/W)

If CPUID.0AH: EAX[7:0] > 3 II

(CPUID.(EAX=07H,

ECX=0):EBX[25] = 1 &&

CPUID.(EAX=014H, ECX=0):ECX[0]

= 1)

0

Set 1 to cause Ovf_PMC0 = 1.

If CPUID.0AH: EAX[7:0] > 3

1

Set 1 to cause Ovf_PMC1 = 1.

If CPUID.0AH: EAX[15:8] > 1

2

Set 1 to cause Ovf_PMC2 = 1.

If CPUID.0AH: EAX[15:8] > 2

n

Set 1 to cause Ovf_PMCn = 1.

If CPUID.0AH: EAX[15:8] > n

31:n

Reserved.

32

Set 1 to cause Ovf_FIXED_CTR0 = 1.

If CPUID.0AH: EAX[7:0] > 3

33

Set 1 to cause Ovf_FIXED_CTR1 = 1.

If CPUID.0AH: EAX[7:0] > 3

34

Set 1 to cause Ovf_FIXED_CTR2 = 1.

If CPUID.0AH: EAX[7:0] > 3

47:35

Reserved.

48

SET_OVF_PERF_METRICS: If this bit is set, it will set the status bit in the

IA32_PERF_GLOBAL_STATUS register for the PERF_METRICS counters.

54:49

Reserved.

55

Set 1 to cause Trace_ToPA_PMI = 1.

If CPUID.(EAX=07H,

ECX=0):EBX[25] = 1 &&

CPUID.(EAX=014H, ECX=0):ECX[0]

= 1

57:56

Reserved.

58

Set 1 to cause LBR_Frz = 1.

If CPUID.0AH: EAX[7:0] > 3

59

Set 1 to cause CTR_Frz = 1.

If CPUID.0AH: EAX[7:0] > 3

58

Set 1 to cause ASCI = 1.

If CPUID.0AH: EAX[7:0] > 3

61

Set 1 to cause Ovf_Uncore = 1.

If CPUID.0AH: EAX[7:0] > 3

62

Set 1 to cause OvfBuf = 1.

If CPUID.0AH: EAX[7:0] > 3

63

Reserved.

Register Address: 392H, 914

IA32_PERF_GLOBAL_INUSE

Indicator that core perfmon interface is in use. (R/O)

If CPUID.0AH: EAX[7:0] > 3

0

IA32_PERFEVTSEL0 in use.

1

IA32_PERFEVTSEL1 in use.

If CPUID.0AH: EAX[15:8] > 1

2

IA32_PERFEVTSEL2 in use.

If CPUID.0AH: EAX[15:8] > 2

n

IA32_PERFEVTSELn in use.

If CPUID.0AH: EAX[15:8] > n

31:n+1

Reserved.

Vol. 4

2-31

MODEL-SPECIFIC REGISTERS (MSRS)

Table 2-2. IA-32 Architectural MSRs (Contd.)

Register Address: Hex, Decimal

Architectural MSR Name (Former MSR Name)

Bit Fields

MSR/Bit Description

Comment

32

IA32_FIXED_CTR0 in use.

33

IA32_FIXED_CTR1 in use.

34

IA32_FIXED_CTR2 in use.

62:35

Reserved or model specific.

63

PMI in use.

Register Address: 3F1H, 1009

IA32_PEBS_ENABLE

PEBS Control (R/W)

0

Enable PEBS on IA32_PMC0.

06_0FH

3:1

Reserved or model specific.

31:4

Reserved.

35:32

Reserved or model specific.

63:36

Reserved.

Register Address: 400H, 1024

IA32_MC0_CTL

MC0_CTL

If IA32_MCG_CAP.CNT >0

Register Address: 401H, 1025

IA32_MC0_STATUS

MC0_STATUS

If IA32_MCG_CAP.CNT >0

Register Address: 402H, 1026

IA32_MC0_ADDR¹

MC0_ADDR

If IA32_MCG_CAP.CNT >0

Register Address: 403H, 1027

IA32_MC0_MISC

MC0_MISC

If IA32_MCG_CAP.CNT >0

Register Address: 404H, 1028

IA32_MC1_CTL

MC1_CTL

If IA32_MCG_CAP.CNT >1

Register Address: 405H, 1029

IA32_MC1_STATUS

MC1_STATUS

If IA32_MCG_CAP.CNT >1

Register Address: 406H, 1030

IA32_MC1_ADDR²

MC1_ADDR

If IA32_MCG_CAP.CNT >1

Register Address: 407H, 1031

IA32_MC1_MISC

MC1_MISC

If IA32_MCG_CAP.CNT >1

Register Address: 408H, 1032

IA32_MC2_CTL

MC2_CTL

If IA32_MCG_CAP.CNT >2

Register Address: 409H, 1033

IA32_MC2_STATUS

MC2_STATUS

If IA32_MCG_CAP.CNT >2

Register Address: 40AH, 1034

IA32_MC2_ADDR¹

MC2_ADDR

If IA32_MCG_CAP.CNT >2

Register Address: 40BH, 1035

IA32_MC2_MISC

MC2_MISC

If IA32_MCG_CAP.CNT >2

Register Address: 40CH, 1036

IA32_MC3_CTL

2-32 Vol. 4

MODEL-SPECIFIC REGISTERS (MSRS)

Table 2-2. IA-32 Architectural MSRs (Contd.)

Register Address: Hex, Decimal

Architectural MSR Name (Former MSR Name)

Bit Fields

MSR/Bit Description

Comment

MC3_CTL

If IA32_MCG_CAP.CNT >3

Register Address: 40DH, 1037

IA32_MC3_STATUS

MC3_STATUS

If IA32_MCG_CAP.CNT >3

Register Address: 40EH, 1038

IA32_MC3_ADDR¹

MC3_ADDR

If IA32_MCG_CAP.CNT >3

Register Address: 40FH, 1039

IA32_MC3_MISC

MC3_MISC

If IA32_MCG_CAP.CNT >3

Register Address: 410H, 1040

IA32_MC4_CTL

MC4_CTL

If IA32_MCG_CAP.CNT >4

Register Address: 411H, 1041

IA32_MC4_STATUS

MC4_STATUS

If IA32_MCG_CAP.CNT >4

Register Address: 412H, 1042

IA32_MC4_ADDR¹

MC4_ADDR

If IA32_MCG_CAP.CNT >4

Register Address: 413H, 1043

IA32_MC4_MISC

MC4_MISC

If IA32_MCG_CAP.CNT >4

Register Address: 414H, 1044

IA32_MC5_CTL

MC5_CTL

If IA32_MCG_CAP.CNT >5

Register Address: 415H, 1045

IA32_MC5_STATUS

MC5_STATUS

If IA32_MCG_CAP.CNT >5

Register Address: 416H, 1046

IA32_MC5_ADDR¹

MC5_ADDR

If IA32_MCG_CAP.CNT >5

Register Address: 417H, 1047

IA32_MC5_MISC

MC5_MISC

If IA32_MCG_CAP.CNT >5

Register Address: 418H, 1048

IA32_MC6_CTL

MC6_CTL

If IA32_MCG_CAP.CNT >6

Register Address: 419H, 1049

IA32_MC6_STATUS

MC6_STATUS

If IA32_MCG_CAP.CNT >6

Register Address: 41AH, 1050

IA32_MC6_ADDR¹

MC6_ADDR

If IA32_MCG_CAP.CNT >6

Register Address: 41BH, 1051

IA32_MC6_MISC

MC6_MISC

If IA32_MCG_CAP.CNT >6

Register Address: 41CH, 1052

IA32_MC7_CTL

MC7_CTL

If IA32_MCG_CAP.CNT >7

Register Address: 41DH, 1053

IA32_MC7_STATUS

MC7_STATUS

If IA32_MCG_CAP.CNT >7

Register Address: 41EH, 1054

IA32_MC7_ADDR¹

MC7_ADDR

If IA32_MCG_CAP.CNT >7

Vol. 4

2-33

MODEL-SPECIFIC REGISTERS (MSRS)

Table 2-2. IA-32 Architectural MSRs (Contd.)

Register Address: Hex, Decimal

Architectural MSR Name (Former MSR Name)

Bit Fields

MSR/Bit Description

Comment

Register Address: 41FH, 1055

IA32_MC7_MISC

MC7_MISC

If IA32_MCG_CAP.CNT >7

Register Address: 420H, 1056

IA32_MC8_CTL

MC8_CTL

If IA32_MCG_CAP.CNT >8

Register Address: 421H, 1057

IA32_MC8_STATUS

MC8_STATUS

If IA32_MCG_CAP.CNT >8

Register Address: 422H, 1058

IA32_MC8_ADDR¹

MC8_ADDR

If IA32_MCG_CAP.CNT >8

Register Address: 423H, 1059

IA32_MC8_MISC

MC8_MISC

If IA32_MCG_CAP.CNT >8

Register Address: 424H, 1060

IA32_MC9_CTL

MC9_CTL

If IA32_MCG_CAP.CNT >9

Register Address: 425H, 1061

IA32_MC9_STATUS

MC9_STATUS

If IA32_MCG_CAP.CNT >9

Register Address: 426H, 1062

IA32_MC9_ADDR¹

MC9_ADDR

If IA32_MCG_CAP.CNT >9

Register Address: 427H, 1063

IA32_MC9_MISC

MC9_MISC

If IA32_MCG_CAP.CNT >9

Register Address: 428H, 1064

IA32_MC10_CTL

MC10_CTL

If IA32_MCG_CAP.CNT >10

Register Address: 429H, 1065

IA32_MC10_STATUS

MC10_STATUS

If IA32_MCG_CAP.CNT >10

Register Address: 42AH, 1066

IA32_MC10_ADDR¹

MC10_ADDR

If IA32_MCG_CAP.CNT >10

Register Address: 42BH, 1067

IA32_MC10_MISC

MC10_MISC

If IA32_MCG_CAP.CNT >10

Register Address: 42CH, 1068

IA32_MC11_CTL

MC11_CTL

If IA32_MCG_CAP.CNT >11

Register Address: 42DH, 1069

IA32_MC11_STATUS

MC11_STATUS

If IA32_MCG_CAP.CNT >11

Register Address: 42EH, 1070

IA32_MC11_ADDR¹

MC11_ADDR

If IA32_MCG_CAP.CNT >11

Register Address: 42FH, 1071

IA32_MC11_MISC

MC11_MISC

If IA32_MCG_CAP.CNT >11

Register Address: 430H, 1072

IA32_MC12_CTL

MC12_CTL

If IA32_MCG_CAP.CNT >12

Register Address: 431H, 1073

IA32_MC12_STATUS

2-34 Vol. 4

MODEL-SPECIFIC REGISTERS (MSRS)

Table 2-2. IA-32 Architectural MSRs (Contd.)

Register Address: Hex, Decimal

Architectural MSR Name (Former MSR Name)

Bit Fields

MSR/Bit Description

Comment

MC12_STATUS

If IA32_MCG_CAP.CNT >12

Register Address: 432H, 1074

IA32_MC12_ADDR¹

MC12_ADDR

If IA32_MCG_CAP.CNT >12

Register Address: 433H, 1075

IA32_MC12_MISC

MC12_MISC

If IA32_MCG_CAP.CNT >12

Register Address: 434H, 1076

IA32_MC13_CTL

MC13_CTL

If IA32_MCG_CAP.CNT >13

Register Address: 435H, 1077

IA32_MC13_STATUS

MC13_STATUS

If IA32_MCG_CAP.CNT >13

Register Address: 436H, 1078

IA32_MC13_ADDR¹

MC13_ADDR

If IA32_MCG_CAP.CNT >13

Register Address: 437H, 1079

IA32_MC13_MISC

MC13_MISC

If IA32_MCG_CAP.CNT >13

Register Address: 438H, 1080

IA32_MC14_CTL

MC14_CTL

If IA32_MCG_CAP.CNT >14

Register Address: 439H, 1081

IA32_MC14_STATUS

MC14_STATUS

If IA32_MCG_CAP.CNT >14

Register Address: 43AH, 1082

IA32_MC14_ADDR¹

MC14_ADDR

If IA32_MCG_CAP.CNT >14

Register Address: 43BH, 1083

IA32_MC14_MISC

MC14_MISC

If IA32_MCG_CAP.CNT >14

Register Address: 43CH, 1084

IA32_MC15_CTL

MC15_CTL

If IA32_MCG_CAP.CNT >15

Register Address: 43DH, 1085

IA32_MC15_STATUS

MC15_STATUS

If IA32_MCG_CAP.CNT >15

Register Address: 43EH, 1086

IA32_MC15_ADDR¹

MC15_ADDR

If IA32_MCG_CAP.CNT >15

Register Address: 43FH, 1087

IA32_MC15_MISC

MC15_MISC

If IA32_MCG_CAP.CNT >15

Register Address: 440H, 1088

IA32_MC16_CTL

MC16_CTL

If IA32_MCG_CAP.CNT >16

Register Address: 441H, 1089

IA32_MC16_STATUS

MC16_STATUS

If IA32_MCG_CAP.CNT >16

Register Address: 442H, 1090

IA32_MC16_ADDR¹

MC16_ADDR

If IA32_MCG_CAP.CNT >16

Register Address: 443H, 1091

IA32_MC16_MISC

MC16_MISC

If IA32_MCG_CAP.CNT >16

Vol. 4

2-35

MODEL-SPECIFIC REGISTERS (MSRS)

Table 2-2. IA-32 Architectural MSRs (Contd.)

Register Address: Hex, Decimal

Architectural MSR Name (Former MSR Name)

Bit Fields

MSR/Bit Description

Comment

Register Address: 444H, 1092

IA32_MC17_CTL

MC17_CTL

If IA32_MCG_CAP.CNT >17

Register Address: 445H, 1093

IA32_MC17_STATUS

MC17_STATUS

If IA32_MCG_CAP.CNT >17

Register Address: 446H, 1094

IA32_MC17_ADDR¹

MC17_ADDR

If IA32_MCG_CAP.CNT >17

Register Address: 447H, 1095

IA32_MC17_MISC

MC17_MISC

If IA32_MCG_CAP.CNT >17

Register Address: 448H, 1096

IA32_MC18_CTL

MC18_CTL

If IA32_MCG_CAP.CNT >18

Register Address: 449H, 1097

IA32_MC18_STATUS

MC18_STATUS

If IA32_MCG_CAP.CNT >18

Register Address: 44AH, 1098

IA32_MC18_ADDR¹

MC18_ADDR

If IA32_MCG_CAP.CNT >18

Register Address: 44BH, 1099

IA32_MC18_MISC

MC18_MISC

If IA32_MCG_CAP.CNT >18

Register Address: 44CH, 1100

IA32_MC19_CTL

MC19_CTL

If IA32_MCG_CAP.CNT >19

Register Address: 44DH, 1101

IA32_MC19_STATUS

MC19_STATUS

If IA32_MCG_CAP.CNT >19

Register Address: 44EH, 1102

IA32_MC19_ADDR¹

MC19_ADDR

If IA32_MCG_CAP.CNT >19

Register Address: 44FH, 1103

IA32_MC19_MISC

MC19_MISC

If IA32_MCG_CAP.CNT >19

Register Address: 450H, 1104

IA32_MC20_CTL

MC20_CTL

If IA32_MCG_CAP.CNT >20

Register Address: 451H, 1105

IA32_MC20_STATUS

MC20_STATUS

If IA32_MCG_CAP.CNT >20

Register Address: 452H, 11061106

IA32_MC20_ADDR¹

MC20_ADDR

If IA32_MCG_CAP.CNT >20

Register Address: 453H, 1107

IA32_MC20_MISC

MC20_MISC

If IA32_MCG_CAP.CNT >20

Register Address: 454H, 1108

IA32_MC21_CTL

MC21_CTL

If IA32_MCG_CAP.CNT >21

Register Address: 455H, 1109

IA32_MC21_STATUS

MC21_STATUS

If IA32_MCG_CAP.CNT >21

Register Address: 456H, 1110

IA32_MC21_ADDR¹

2-36 Vol. 4

MODEL-SPECIFIC REGISTERS (MSRS)

Table 2-2. IA-32 Architectural MSRs (Contd.)

Register Address: Hex, Decimal

Architectural MSR Name (Former MSR Name)

Bit Fields

MSR/Bit Description

Comment

MC21_ADDR

If IA32_MCG_CAP.CNT >21

Register Address: 457H, 1111

IA32_MC21_MISC

MC21_MISC

If IA32_MCG_CAP.CNT >21

Register Address: 458H, 1112

IA32_MC22_CTL

MC22_CTL

If IA32_MCG_CAP.CNT >22

Register Address: 459H, 1113

IA32_MC22_STATUS

MC22_STATUS

If IA32_MCG_CAP.CNT >22

Register Address: 45AH, 1114

IA32_MC22_ADDR¹

MC22_ADDR

If IA32_MCG_CAP.CNT >22

Register Address: 45BH, 1115

IA32_MC22_MISC

MC22_MISC

If IA32_MCG_CAP.CNT >22

Register Address: 45CH, 1116

IA32_MC23_CTL

MC23_CTL

If IA32_MCG_CAP.CNT >23

Register Address: 45DH, 1117

IA32_MC23_STATUS

MC23_STATUS

If IA32_MCG_CAP.CNT >23

Register Address: 45EH, 1118

IA32_MC23_ADDR¹

MC23_ADDR

If IA32_MCG_CAP.CNT >23

Register Address: 45FH, 1119

IA32_MC23_MISC

MC23_MISC

If IA32_MCG_CAP.CNT >23

Register Address: 460H, 1120

IA32_MC24_CTL

MC24_CTL

If IA32_MCG_CAP.CNT >24

Register Address: 461H, 1121

IA32_MC24_STATUS

MC24_STATUS

If IA32_MCG_CAP.CNT >24

Register Address: 462H, 1122

IA32_MC24_ADDR¹

MC24_ADDR

If IA32_MCG_CAP.CNT >24

Register Address: 463H, 1123

IA32_MC24_MISC

MC24_MISC

If IA32_MCG_CAP.CNT >24

Register Address: 464H, 1124

IA32_MC25_CTL

MC25_CTL

If IA32_MCG_CAP.CNT >25

Register Address: 465H, 1125

IA32_MC25_STATUS

MC25_STATUS

If IA32_MCG_CAP.CNT >25

Register Address: 466H, 1126

IA32_MC25_ADDR¹

MC25_ADDR

If IA32_MCG_CAP.CNT >25

Register Address: 467H, 1127

IA32_MC25_MISC

MC25_MISC

If IA32_MCG_CAP.CNT >25

Register Address: 468H, 1128

IA32_MC26_CTL

MC26_CTL

If IA32_MCG_CAP.CNT >26

Vol. 4

2-37