Intel 64 and IA-32 Architectures. Software Developer’s Manual (Collection, 2023)

INSTRUCTION SET REFERENCE, A-L

Table 3-8. Information Returned by CPUID Instruction (Contd.)

Initial EAX

Value

Information Provided about the Processor

NOTES:

* L2 associativity field encodings:

00H - Disabled

08H - 16 ways

01H - 1 way (direct mapped)

09H - Reserved

02H - 2 ways

0AH - 32 ways

03H - Reserved

0BH - 48 ways

04H - 4 ways

0CH - 64 ways

05H - Reserved

0DH - 96 ways

06H - 8 ways

0EH - 128 ways

07H - See CPUID leaf 04H, sub-leaf 2**

0FH - Fully associative

** CPUID leaf 04H provides details of deterministic cache parameters, including the L2 cache in sub-leaf 2

80000007H

EAX

Reserved = 0.

EBX

Reserved = 0.

ECX

Reserved = 0.

EDX

Bits 07-00: Reserved = 0.

Bit 08: Invariant TSC available if 1.

Bits 31-09: Reserved = 0.

80000008H

EAX

Linear/Physical Address size.

Bits 07-00: #Physical Address Bits*.

Bits 15-08: #Linear Address Bits.

Bits 31-16: Reserved = 0.

EBX

Bits 08-00: Reserved = 0.

Bit 09: WBNOINVD is available if 1.

Bits 31-10: Reserved = 0.

ECX

Reserved = 0.

EDX

Reserved = 0.

NOTES:

* If CPUID.80000008H:EAX[7:0] is supported, the maximum physical address number supported should

come from this field. If TME-MK is enabled, the number of bits that can be used to address physical

memory is CPUID.80000008H:EAX[7:0] - IA32_TME_ACTIVATE[35:32].

INPUT EAX = 0: Returns CPUID’s Highest Value for Basic Processor Information and the Vendor Identification String

When CPUID executes with EAX set to 0, the processor returns the highest value the CPUID recognizes for

returning basic processor information. The value is returned in the EAX register and is processor specific.

A vendor identification string is also returned in EBX, EDX, and ECX. For Intel processors, the string is “Genu-

ineIntel” and is expressed:

EBX := 756e6547h (* “Genu”, with G in the low eight bits of BL *)

EDX := 49656e69h (* “ineI”, with i in the low eight bits of DL *)

ECX := 6c65746eh (* “ntel”, with n in the low eight bits of CL *)

INPUT EAX = 80000000H: Returns CPUID’s Highest Value for Extended Processor Information

When CPUID executes with EAX set to 80000000H, the processor returns the highest value the processor recog-

nizes for returning extended processor information. The value is returned in the EAX register and is processor

specific.

IA32_BIOS_SIGN_ID Returns Microcode Update Signature

For processors that support the microcode update facility, the IA32_BIOS_SIGN_ID MSR is loaded with the update

signature whenever CPUID executes. The signature is returned in the upper DWORD. For details, see Chapter 10 in

the Intel^®64 and IA-32 Architectures Software Developer’s Manual, Volume 3A.

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INPUT EAX = 01H: Returns Model, Family, Stepping Information

When CPUID executes with EAX set to 01H, version information is returned in EAX (see Figure 3-6). For example:

model, family, and processor type for the Intel Xeon processor 5100 series is as follows:

• Model - 1111B

• Family - 0101B

• Processor Type - 00B

See Table 3-9 for available processor type values. Stepping IDs are provided as needed.

28 27

20 19

16 15 14 13 12 11

Extended

Family

Stepping

EAX

Model

Family ID

Model ID

Extended Family ID (0)

Extended Model ID (0)

Processor Type

Family (0FH for the Pentium 4 Processor Family)

Model

Reserved

OM16525

Figure 3-6. Version Information Returned by CPUID in EAX

Table 3-9. Processor Type Field

Type

Encoding

Original OEM Processor

00B

Intel OverDrive^® Processor

01B

Dual processor (not applicable to Intel486 processors)

10B

Intel reserved

11B

NOTE

See Chapter 20 in the Intel^® 64 and IA-32 Architectures Software Developer’s Manual, Volume 1,

for information on identifying earlier IA-32 processors.

The Extended Family ID needs to be examined only when the Family ID is 0FH. Integrate the fields into a display

using the following rule:

IF Family_ID ≠ 0FH

THEN DisplayFamily = Family_ID;

ELSE DisplayFamily = Extended_Family_ID + Family_ID;

FI;

(* Show DisplayFamily as HEX field. *)

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The Extended Model ID needs to be examined only when the Family ID is 06H or 0FH. Integrate the field into a

display using the following rule:

IF (Family_ID = 06H or Family_ID = 0FH)

THEN DisplayModel = (Extended_Model_ID « 4) + Model_ID;

(* Right justify and zero-extend 4-bit field; display Model_ID as HEX field.*)

ELSE DisplayModel = Model_ID;

FI;

(* Show DisplayModel as HEX field. *)

INPUT EAX = 01H: Returns Additional Information in EBX

When CPUID executes with EAX set to 01H, additional information is returned to the EBX register:

• Brand index (low byte of EBX) - this number provides an entry into a brand string table that contains brand

strings for IA-32 processors. More information about this field is provided later in this section.

• CLFLUSH instruction cache line size (second byte of EBX) - this number indicates the size of the cache line

flushed by the CLFLUSH and CLFLUSHOPT instructions in 8-byte increments. This field was introduced in the

Pentium 4 processor.

• Local APIC ID (high byte of EBX) - this number is the 8-bit ID that is assigned to the local APIC on the

processor during power up. This field was introduced in the Pentium 4 processor.

INPUT EAX = 01H: Returns Feature Information in ECX and EDX

When CPUID executes with EAX set to 01H, feature information is returned in ECX and EDX.

• Figure 3-7 and Table 3-10 show encodings for ECX.

• Figure 3-8 and Table 3-11 show encodings for EDX.

For all feature flags, a 1 indicates that the feature is supported. Use Intel to properly interpret feature flags.

NOTE

Software must confirm that a processor feature is present using feature flags returned by CPUID

prior to using the feature. Software should not depend on future offerings retaining all features.

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31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10

ECX

RDRAND

F16C

AVX

OSXSAVE

XSAVE

AES

TSC-Deadline

POPCNT

MOVBE

x2APIC

SSE4_2 - SSE4.2

SSE4_1 - SSE4.1

DCA - Direct Cache Access

PCID - Process-context Identifiers

PDCM - Perf/Debug Capability MSR

xTPR Update Control

CMPXCHG16B

FMA - Fused Multiply Add

SDBG

CNXT-ID - L1 Context ID

SSSE3 - SSSE3 Extensions

TM2 - Thermal Monitor 2

EIST - Enhanced Intel SpeedStep® Technology

SMX - Safer Mode Extensions

VMX - Virtual Machine Extensions

DS-CPL - CPL Qualified Debug Store

MONITOR - MONITOR/MWAIT

DTES64 - 64-bit DS Area

PCLMULQDQ - Carryless Multiplication

SSE3 - SSE3 Extensions

OM16524b

Reserved

Figure 3-7. Feature Information Returned in the ECX Register

Table 3-10. Feature Information Returned in the ECX Register

Bit #

Mnemonic

Description

SSE3

Streaming SIMD Extensions 3 (SSE3). A value of 1 indicates the processor supports this

technology.

PCLMULQDQ

PCLMULQDQ. A value of 1 indicates the processor supports the PCLMULQDQ instruction.

DTES64

64-bit DS Area. A value of 1 indicates the processor supports DS area using 64-bit layout.

MONITOR

MONITOR/MWAIT. A value of 1 indicates the processor supports this feature.

DS-CPL

CPL Qualified Debug Store. A value of 1 indicates the processor supports the extensions to the

Debug Store feature to allow for branch message storage qualified by CPL.

VMX

Virtual Machine Extensions. A value of 1 indicates that the processor supports this technology.

SMX

Safer Mode Extensions. A value of 1 indicates that the processor supports this technology. See

Chapter 7, “Safer Mode Extensions Reference.”

EIST

Enhanced Intel SpeedStep® technology. A value of 1 indicates that the processor supports this

technology.

TM2

Thermal Monitor 2. A value of 1 indicates whether the processor supports this technology.

SSSE3

A value of 1 indicates the presence of the Supplemental Streaming SIMD Extensions 3 (SSSE3). A

value of 0 indicates the instruction extensions are not present in the processor.

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Table 3-10. Feature Information Returned in the ECX Register (Contd.)

Bit #

Mnemonic

Description

CNXT-ID

L1 Context ID. A value of 1 indicates the L1 data cache mode can be set to either adaptive mode

or shared mode. A value of 0 indicates this feature is not supported. See definition of the

IA32_MISC_ENABLE MSR Bit 24 (L1 Data Cache Context Mode) for details.

SDBG

A value of 1 indicates the processor supports IA32_DEBUG_INTERFACE MSR for silicon debug.

FMA

A value of 1 indicates the processor supports FMA extensions using YMM state.

CMPXCHG16B

CMPXCHG16B Available. A value of 1 indicates that the feature is available. See the

“CMPXCHG8B/CMPXCHG16B-Compare and Exchange Bytes” section in this chapter for a

description.

xTPR Update

xTPR Update Control. A value of 1 indicates that the processor supports changing

Control

IA32_MISC_ENABLE[bit 23].

PDCM

Perfmon and Debug Capability: A value of 1 indicates the processor supports the performance

and debug feature indication MSR IA32_PERF_CAPABILITIES.

Reserved

PCID

Process-context identifiers. A value of 1 indicates that the processor supports PCIDs and that

software may set CR4.PCIDE to 1.

DCA

A value of 1 indicates the processor supports the ability to prefetch data from a memory mapped

device.

SSE4_1

A value of 1 indicates that the processor supports SSE4.1.

SSE4_2

A value of 1 indicates that the processor supports SSE4.2.

x2APIC

A value of 1 indicates that the processor supports x2APIC feature.

MOVBE

A value of 1 indicates that the processor supports MOVBE instruction.

POPCNT

A value of 1 indicates that the processor supports the POPCNT instruction.

TSC-Deadline

A value of 1 indicates that the processor’s local APIC timer supports one-shot operation using a

TSC deadline value.

AESNI

A value of 1 indicates that the processor supports the AESNI instruction extensions.

XSAVE

A value of 1 indicates that the processor supports the XSAVE/XRSTOR processor extended states

feature, the XSETBV/XGETBV instructions, and XCR0.

OSXSAVE

A value of 1 indicates that the OS has set CR4.OSXSAVE[bit 18] to enable XSETBV/XGETBV

instructions to access XCR0 and to support processor extended state management using

XSAVE/XRSTOR.

AVX

A value of 1 indicates the processor supports the AVX instruction extensions.

F16C

A value of 1 indicates that processor supports 16-bit floating-point conversion instructions.

RDRAND

A value of 1 indicates that processor supports RDRAND instruction.

Not Used

Always returns 0.

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3130292827262524 23 22 21 20 19 18 17 16 15 14 13 12 1110 9

5 4

EDX

PBE-Pend. Brk. EN.

TM-Therm. Monitor

HTT-Multi-threading

SS-Self Snoop

SSE2-SSE2 Extensions

SSE-SSE Extensions

FXSR-FXSAVE/FXRSTOR

MMX-MMX Technology

ACPI-Thermal Monitor and Clock Ctrl

DS-Debug Store

CLFSH-CLFLUSH instruction

PSN-Processor Serial Number

PSE-36 - Page Size Extension

PAT-Page Attribute Table

CMOV-Conditional Move/Compare Instruction

MCA-Machine Check Architecture

PGE-PTE Global Bit

MTRR-Memory Type Range Registers

SEP-SYSENTER and SYSEXIT

APIC-APIC on Chip

CX8-CMPXCHG8B Inst.

MCE-Machine Check Exception

PAE-Physical Address Extensions

MSR-RDMSR and WRMSR Support

TSC-Time Stamp Counter

PSE-Page Size Extensions

DE-Debugging Extensions

VME-Virtual-8086 Mode Enhancement

FPU-x87 FPU on Chip

Reserved

OM16523

Figure 3-8. Feature Information Returned in the EDX Register

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Table 3-11. More on Feature Information Returned in the EDX Register

Bit #

Mnemonic

Description

FPU

Floating-Point Unit On-Chip. The processor contains an x87 FPU.

VME

Virtual 8086 Mode Enhancements. Virtual 8086 mode enhancements, including CR4.VME for controlling the

feature, CR4.PVI for protected mode virtual interrupts, software interrupt indirection, expansion of the TSS

with the software indirection bitmap, and EFLAGS.VIF and EFLAGS.VIP flags.

Debugging Extensions. Support for I/O breakpoints, including CR4.DE for controlling the feature, and optional

trapping of accesses to DR4 and DR5.

PSE

Page Size Extension. Large pages of size 4 MByte are supported, including CR4.PSE for controlling the

feature, the defined dirty bit in PDE (Page Directory Entries), optional reserved bit trapping in CR3, PDEs, and

PTEs.

TSC

Time Stamp Counter. The RDTSC instruction is supported, including CR4.TSD for controlling privilege.

MSR

Model Specific Registers RDMSR and WRMSR Instructions. The RDMSR and WRMSR instructions are

supported. Some of the MSRs are implementation dependent.

PAE

Physical Address Extension. Physical addresses greater than 32 bits are supported: extended page table

entry formats, an extra level in the page translation tables is defined, 2-MByte pages are supported instead of

4 Mbyte pages if PAE bit is 1.

MCE

Machine Check Exception. Exception 18 is defined for Machine Checks, including CR4.MCE for controlling the

feature. This feature does not define the model-specific implementations of machine-check error logging,

reporting, and processor shutdowns. Machine Check exception handlers may have to depend on processor

version to do model specific processing of the exception, or test for the presence of the Machine Check feature.

CX8

CMPXCHG8B Instruction. The compare-and-exchange 8 bytes (64 bits) instruction is supported (implicitly

locked and atomic).

APIC

APIC On-Chip. The processor contains an Advanced Programmable Interrupt Controller (APIC), responding to

memory mapped commands in the physical address range FFFE0000H to FFFE0FFFH (by default - some

processors permit the APIC to be relocated).

Reserved

SEP

SYSENTER and SYSEXIT Instructions. The SYSENTER and SYSEXIT and associated MSRs are supported.

MTRR

Memory Type Range Registers. MTRRs are supported. The MTRRcap MSR contains feature bits that describe

what memory types are supported, how many variable MTRRs are supported, and whether fixed MTRRs are

supported.

PGE

Page Global Bit. The global bit is supported in paging-structure entries that map a page, indicating TLB entries

that are common to different processes and need not be flushed. The CR4.PGE bit controls this feature.

MCA

Machine Check Architecture. A value of 1 indicates the Machine Check Architecture of reporting machine

errors is supported. The MCG_CAP MSR contains feature bits describing how many banks of error reporting

MSRs are supported.

CMOV

Conditional Move Instructions. The conditional move instruction CMOV is supported. In addition, if x87 FPU is

present as indicated by the CPUID.FPU feature bit, then the FCOMI and FCMOV instructions are supported

PAT

Page Attribute Table. Page Attribute Table is supported. This feature augments the Memory Type Range

Registers (MTRRs), allowing an operating system to specify attributes of memory accessed through a linear

address on a 4KB granularity.

PSE-36

36-Bit Page Size Extension. 4-MByte pages addressing physical memory beyond 4 GBytes are supported with

32-bit paging. This feature indicates that upper bits of the physical address of a 4-MByte page are encoded in

bits 20:13 of the page-directory entry. Such physical addresses are limited by MAXPHYADDR and may be up to

40 bits in size.

PSN

Processor Serial Number. The processor supports the 96-bit processor identification number feature and the

feature is enabled.

CLFSH

CLFLUSH Instruction. CLFLUSH Instruction is supported.

Reserved

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Table 3-11. More on Feature Information Returned in the EDX Register (Contd.)

Bit #

Mnemonic

Description

Debug Store. The processor supports the ability to write debug information into a memory resident buffer.

This feature is used by the branch trace store (BTS) and processor event-based sampling (PEBS) facilities (see

Chapter 24, “Introduction to Virtual Machine Extensions,” in the Intel^® 64 and IA-32 Architectures Software

Developer’s Manual, Volume 3C).

ACPI

Thermal Monitor and Software Controlled Clock Facilities. The processor implements internal MSRs that

allow processor temperature to be monitored and processor performance to be modulated in predefined duty

cycles under software control.

MMX

Intel MMX Technology. The processor supports the Intel MMX technology.

FXSR

FXSAVE and FXRSTOR Instructions. The FXSAVE and FXRSTOR instructions are supported for fast save and

restore of the floating-point context. Presence of this bit also indicates that CR4.OSFXSR is available for an

operating system to indicate that it supports the FXSAVE and FXRSTOR instructions.

SSE

SSE. The processor supports the SSE extensions.

SSE2

SSE2. The processor supports the SSE2 extensions.

Self Snoop. The processor supports the management of conflicting memory types by performing a snoop of its

own cache structure for transactions issued to the bus.

HTT

Max APIC IDs reserved field is Valid. A value of 0 for HTT indicates there is only a single logical processor in

the package and software should assume only a single APIC ID is reserved. A value of 1 for HTT indicates the

value in CPUID.1.EBX[23:16] (the Maximum number of addressable IDs for logical processors in this package) is

valid for the package.

Thermal Monitor. The processor implements the thermal monitor automatic thermal control circuitry (TCC).

Reserved

PBE

Pending Break Enable. The processor supports the use of the FERR#/PBE# pin when the processor is in the

stop-clock state (STPCLK# is asserted) to signal the processor that an interrupt is pending and that the

processor should return to normal operation to handle the interrupt.

INPUT EAX = 02H: TLB/Cache/Prefetch Information Returned in EAX, EBX, ECX, EDX

When CPUID executes with EAX set to 02H, the processor returns information about the processor’s internal TLBs,

cache, and prefetch hardware in the EAX, EBX, ECX, and EDX registers. The information is reported in encoded

form and fall into the following categories:

• The least-significant byte in register EAX (register AL) will always return 01H. Software should ignore this value

and not interpret it as an informational descriptor.

• The most significant bit (bit 31) of each register indicates whether the register contains valid information (set

to 0) or is reserved (set to 1).

• If a register contains valid information, the information is contained in 1 byte descriptors. There are four types

of encoding values for the byte descriptor, the encoding type is noted in the second column of Table 3-12. Table

3-12 lists the encoding of these descriptors. Note that the order of descriptors in the EAX, EBX, ECX, and EDX

registers is not defined; that is, specific bytes are not designated to contain descriptors for specific cache,

prefetch, or TLB types. The descriptors may appear in any order. Note also a processor may report a general

descriptor type (FFH) and not report any byte descriptor of “cache type” via CPUID leaf 2.

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Table 3-12. Encoding of CPUID Leaf 2 Descriptors

Descriptor

Type

Cache or TLB Description

Value

00H

General

Null descriptor, this byte contains no information.

01H

TLB

Instruction TLB: 4 KByte pages, 4-way set associative, 32 entries.

02H

TLB

Instruction TLB: 4 MByte pages, fully associative, 2 entries.

03H

TLB

Data TLB: 4 KByte pages, 4-way set associative, 64 entries.

04H

TLB

Data TLB: 4 MByte pages, 4-way set associative, 8 entries.

05H

TLB

Data TLB1: 4 MByte pages, 4-way set associative, 32 entries.

06H

Cache

1st-level instruction cache: 8 KBytes, 4-way set associative, 32 byte line size.

08H

Cache

1st-level instruction cache: 16 KBytes, 4-way set associative, 32 byte line size.

09H

Cache

1st-level instruction cache: 32KBytes, 4-way set associative, 64 byte line size.

0AH

Cache

1st-level data cache: 8 KBytes, 2-way set associative, 32 byte line size.

0BH

TLB

Instruction TLB: 4 MByte pages, 4-way set associative, 4 entries.

0CH

Cache

1st-level data cache: 16 KBytes, 4-way set associative, 32 byte line size.

0DH

Cache

1st-level data cache: 16 KBytes, 4-way set associative, 64 byte line size.

0EH

Cache

1st-level data cache: 24 KBytes, 6-way set associative, 64 byte line size.

1DH

Cache

2nd-level cache: 128 KBytes, 2-way set associative, 64 byte line size.

21H

Cache

2nd-level cache: 256 KBytes, 8-way set associative, 64 byte line size.

22H

Cache

3rd-level cache: 512 KBytes, 4-way set associative, 64 byte line size, 2 lines per sector.

23H

Cache

3rd-level cache: 1 MBytes, 8-way set associative, 64 byte line size, 2 lines per sector.

24H

Cache

2nd-level cache: 1 MBytes, 16-way set associative, 64 byte line size.

25H

Cache

3rd-level cache: 2 MBytes, 8-way set associative, 64 byte line size, 2 lines per sector.

29H

Cache

3rd-level cache: 4 MBytes, 8-way set associative, 64 byte line size, 2 lines per sector.

2CH

Cache

1st-level data cache: 32 KBytes, 8-way set associative, 64 byte line size.

30H

Cache

1st-level instruction cache: 32 KBytes, 8-way set associative, 64 byte line size.

40H

Cache

No 2nd-level cache or, if processor contains a valid 2nd-level cache, no 3rd-level cache.

41H

Cache

2nd-level cache: 128 KBytes, 4-way set associative, 32 byte line size.

42H

Cache

2nd-level cache: 256 KBytes, 4-way set associative, 32 byte line size.

43H

Cache

2nd-level cache: 512 KBytes, 4-way set associative, 32 byte line size.

44H

Cache

2nd-level cache: 1 MByte, 4-way set associative, 32 byte line size.

45H

Cache

2nd-level cache: 2 MByte, 4-way set associative, 32 byte line size.

46H

Cache

3rd-level cache: 4 MByte, 4-way set associative, 64 byte line size.

47H

Cache

3rd-level cache: 8 MByte, 8-way set associative, 64 byte line size.

48H

Cache

2nd-level cache: 3MByte, 12-way set associative, 64 byte line size.

49H

Cache

3rd-level cache: 4MB, 16-way set associative, 64-byte line size (Intel Xeon processor MP, Family 0FH,

Model 06H);

2nd-level cache: 4 MByte, 16-way set associative, 64 byte line size.

4AH

Cache

3rd-level cache: 6MByte, 12-way set associative, 64 byte line size.

4BH

Cache

3rd-level cache: 8MByte, 16-way set associative, 64 byte line size.

4CH

Cache

3rd-level cache: 12MByte, 12-way set associative, 64 byte line size.

4DH

Cache

3rd-level cache: 16MByte, 16-way set associative, 64 byte line size.

4EH

Cache

2nd-level cache: 6MByte, 24-way set associative, 64 byte line size.

4FH

TLB

Instruction TLB: 4 KByte pages, 32 entries.

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Table 3-12. Encoding of CPUID Leaf 2 Descriptors (Contd.)

Descriptor

Type

Cache or TLB Description

Value

50H

TLB

Instruction TLB: 4 KByte and 2-MByte or 4-MByte pages, 64 entries.

51H

TLB

Instruction TLB: 4 KByte and 2-MByte or 4-MByte pages, 128 entries.

52H

TLB

Instruction TLB: 4 KByte and 2-MByte or 4-MByte pages, 256 entries.

55H

TLB

Instruction TLB: 2-MByte or 4-MByte pages, fully associative, 7 entries.

56H

TLB

Data TLB0: 4 MByte pages, 4-way set associative, 16 entries.

57H

TLB

Data TLB0: 4 KByte pages, 4-way associative, 16 entries.

59H

TLB

Data TLB0: 4 KByte pages, fully associative, 16 entries.

5AH

TLB

Data TLB0: 2 MByte or 4 MByte pages, 4-way set associative, 32 entries.

5BH

TLB

Data TLB: 4 KByte and 4 MByte pages, 64 entries.

5CH

TLB

Data TLB: 4 KByte and 4 MByte pages,128 entries.

5DH

TLB

Data TLB: 4 KByte and 4 MByte pages,256 entries.

60H

Cache

1st-level data cache: 16 KByte, 8-way set associative, 64 byte line size.

61H

TLB

Instruction TLB: 4 KByte pages, fully associative, 48 entries.

63H

TLB

Data TLB: 2 MByte or 4 MByte pages, 4-way set associative, 32 entries and a separate array with 1 GByte

pages, 4-way set associative, 4 entries.

64H

TLB

Data TLB: 4 KByte pages, 4-way set associative, 512 entries.

66H

Cache

1st-level data cache: 8 KByte, 4-way set associative, 64 byte line size.

67H

Cache

1st-level data cache: 16 KByte, 4-way set associative, 64 byte line size.

68H

Cache

1st-level data cache: 32 KByte, 4-way set associative, 64 byte line size.

6AH

Cache

uTLB: 4 KByte pages, 8-way set associative, 64 entries.

6BH

Cache

DTLB: 4 KByte pages, 8-way set associative, 256 entries.

6CH

Cache

DTLB: 2M/4M pages, 8-way set associative, 128 entries.

6DH

Cache

DTLB: 1 GByte pages, fully associative, 16 entries.

70H

Cache

Trace cache: 12 K-μop, 8-way set associative.

71H

Cache

Trace cache: 16 K-μop, 8-way set associative.

72H

Cache

Trace cache: 32 K-μop, 8-way set associative.

76H

TLB

Instruction TLB: 2M/4M pages, fully associative, 8 entries.

78H

Cache

2nd-level cache: 1 MByte, 4-way set associative, 64byte line size.

79H

Cache

2nd-level cache: 128 KByte, 8-way set associative, 64 byte line size, 2 lines per sector.

7AH

Cache

2nd-level cache: 256 KByte, 8-way set associative, 64 byte line size, 2 lines per sector.

7BH

Cache

2nd-level cache: 512 KByte, 8-way set associative, 64 byte line size, 2 lines per sector.

7CH

Cache

2nd-level cache: 1 MByte, 8-way set associative, 64 byte line size, 2 lines per sector.

7DH

Cache

2nd-level cache: 2 MByte, 8-way set associative, 64byte line size.

7FH

Cache

2nd-level cache: 512 KByte, 2-way set associative, 64-byte line size.

80H

Cache

2nd-level cache: 512 KByte, 8-way set associative, 64-byte line size.

82H

Cache

2nd-level cache: 256 KByte, 8-way set associative, 32 byte line size.

83H

Cache

2nd-level cache: 512 KByte, 8-way set associative, 32 byte line size.

84H

Cache

2nd-level cache: 1 MByte, 8-way set associative, 32 byte line size.

85H

Cache

2nd-level cache: 2 MByte, 8-way set associative, 32 byte line size.

86H

Cache

2nd-level cache: 512 KByte, 4-way set associative, 64 byte line size.

87H

Cache

2nd-level cache: 1 MByte, 8-way set associative, 64 byte line size.

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Table 3-12. Encoding of CPUID Leaf 2 Descriptors (Contd.)

Descriptor

Type

Cache or TLB Description

Value

A0H

DTLB

DTLB: 4k pages, fully associative, 32 entries.

B0H

TLB

Instruction TLB: 4 KByte pages, 4-way set associative, 128 entries.

B1H

TLB

Instruction TLB: 2M pages, 4-way, 8 entries or 4M pages, 4-way, 4 entries.

B2H

TLB

Instruction TLB: 4KByte pages, 4-way set associative, 64 entries.

B3H

TLB

Data TLB: 4 KByte pages, 4-way set associative, 128 entries.

B4H

TLB

Data TLB1: 4 KByte pages, 4-way associative, 256 entries.

B5H

TLB

Instruction TLB: 4KByte pages, 8-way set associative, 64 entries.

B6H

TLB

Instruction TLB: 4KByte pages, 8-way set associative, 128 entries.

BAH

TLB

Data TLB1: 4 KByte pages, 4-way associative, 64 entries.

C0H

TLB

Data TLB: 4 KByte and 4 MByte pages, 4-way associative, 8 entries.

C1H

STLB

Shared 2nd-Level TLB: 4 KByte/2MByte pages, 8-way associative, 1024 entries.

C2H

DTLB

DTLB: 4 KByte/2 MByte pages, 4-way associative, 16 entries.

C3H

STLB

Shared 2nd-Level TLB: 4 KByte /2 MByte pages, 6-way associative, 1536 entries. Also 1GBbyte pages, 4-

way, 16 entries.

C4H

DTLB

DTLB: 2M/4M Byte pages, 4-way associative, 32 entries.

CAH

STLB

Shared 2nd-Level TLB: 4 KByte pages, 4-way associative, 512 entries.

D0H

Cache

3rd-level cache: 512 KByte, 4-way set associative, 64 byte line size.

D1H

Cache

3rd-level cache: 1 MByte, 4-way set associative, 64 byte line size.

D2H

Cache

3rd-level cache: 2 MByte, 4-way set associative, 64 byte line size.

D6H

Cache

3rd-level cache: 1 MByte, 8-way set associative, 64 byte line size.

D7H

Cache

3rd-level cache: 2 MByte, 8-way set associative, 64 byte line size.

D8H

Cache

3rd-level cache: 4 MByte, 8-way set associative, 64 byte line size.

DCH

Cache

3rd-level cache: 1.5 MByte, 12-way set associative, 64 byte line size.

DDH

Cache

3rd-level cache: 3 MByte, 12-way set associative, 64 byte line size.

DEH

Cache

3rd-level cache: 6 MByte, 12-way set associative, 64 byte line size.

E2H

Cache

3rd-level cache: 2 MByte, 16-way set associative, 64 byte line size.

E3H

Cache

3rd-level cache: 4 MByte, 16-way set associative, 64 byte line size.

E4H

Cache

3rd-level cache: 8 MByte, 16-way set associative, 64 byte line size.

EAH

Cache

3rd-level cache: 12MByte, 24-way set associative, 64 byte line size.

EBH

Cache

3rd-level cache: 18MByte, 24-way set associative, 64 byte line size.

ECH

Cache

3rd-level cache: 24MByte, 24-way set associative, 64 byte line size.

F0H

Prefetch

64-Byte prefetching.

F1H

Prefetch

128-Byte prefetching.

FEH

General

CPUID leaf 2 does not report TLB descriptor information; use CPUID leaf 18H to query TLB and other

address translation parameters.

FFH

General

CPUID leaf 2 does not report cache descriptor information, use CPUID leaf 4 to query cache parameters.

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Example 3-1. Example of Cache and TLB Interpretation

The first member of the family of Pentium 4 processors returns the following information about caches and TLBs

when the CPUID executes with an input value of 2:

EAX

66 5B 50 01H

EBX

ECX

EDX

00 7A 70 00H

Which means:

• The least-significant byte (byte 0) of register EAX is set to 01H. This value should be ignored.

• The most-significant bit of all four registers (EAX, EBX, ECX, and EDX) is set to 0, indicating that each register

contains valid 1-byte descriptors.

• Bytes 1, 2, and 3 of register EAX indicate that the processor has:

- 50H - a 64-entry instruction TLB, for mapping 4-KByte and 2-MByte or 4-MByte pages.

- 5BH - a 64-entry data TLB, for mapping 4-KByte and 4-MByte pages.

- 66H - an 8-KByte 1st level data cache, 4-way set associative, with a 64-Byte cache line size.

• The descriptors in registers EBX and ECX are valid, but contain NULL descriptors.

• Bytes 0, 1, 2, and 3 of register EDX indicate that the processor has:

- 00H - NULL descriptor.

- 70H - Trace cache: 12 K-μop, 8-way set associative.

- 7AH - a 256-KByte 2nd level cache, 8-way set associative, with a sectored, 64-byte cache line size.

- 00H - NULL descriptor.

INPUT EAX = 04H: Returns Deterministic Cache Parameters for Each Level

When CPUID executes with EAX set to 04H and ECX contains an index value, the processor returns encoded data

that describe a set of deterministic cache parameters (for the cache level associated with the input in ECX). Valid

index values start from 0.

Software can enumerate the deterministic cache parameters for each level of the cache hierarchy starting with an

index value of 0, until the parameters report the value associated with the cache type field is 0. The architecturally

defined fields reported by deterministic cache parameters are documented in Table 3-8.

This Cache Size in Bytes

= (Ways + 1) * (Partitions + 1) * (Line_Size + 1) * (Sets + 1)

= (EBX[31:22] + 1) * (EBX[21:12] + 1) * (EBX[11:0] + 1) * (ECX + 1)

The CPUID leaf 04H also reports data that can be used to derive the topology of processor cores in a physical

package. This information is constant for all valid index values. Software can query the raw data reported by

executing CPUID with EAX=04H and ECX=0 and use it as part of the topology enumeration algorithm described in

Chapter 9, “Multiple-Processor Management,” in the Intel^®64 and IA-32 Architectures Software Developer’s

Manual, Volume 3A.

INPUT EAX = 05H: Returns MONITOR and MWAIT Features

When CPUID executes with EAX set to 05H, the processor returns information about features available to

MONITOR/MWAIT instructions. The MONITOR instruction is used for address-range monitoring in conjunction with

MWAIT instruction. The MWAIT instruction optionally provides additional extensions for advanced power manage-

ment. See Table 3-8.

INPUT EAX = 06H: Returns Thermal and Power Management Features

When CPUID executes with EAX set to 06H, the processor returns information about thermal and power manage-

ment features. See Table 3-8.

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INPUT EAX = 07H: Returns Structured Extended Feature Enumeration Information

When CPUID executes with EAX set to 07H and ECX = 0, the processor returns information about the maximum

input value for sub-leaves that contain extended feature flags. See Table 3-8.

When CPUID executes with EAX set to 07H and the input value of ECX is invalid (see leaf 07H entry in Table 3-8),

the processor returns 0 in EAX/EBX/ECX/EDX. In subleaf 0, EAX returns the maximum input value of the highest

leaf 7 sub-leaf, and EBX, ECX & EDX contain information of extended feature flags.

INPUT EAX = 09H: Returns Direct Cache Access Information

When CPUID executes with EAX set to 09H, the processor returns information about Direct Cache Access capabili-

ties. See Table 3-8.

INPUT EAX = 0AH: Returns Architectural Performance Monitoring Features

When CPUID executes with EAX set to 0AH, the processor returns information about support for architectural

performance monitoring capabilities. Architectural performance monitoring is supported if the version ID (see Table

3-8) is greater than Pn 0. See Table 3-8.

For each version of architectural performance monitoring capability, software must enumerate this leaf to discover

the programming facilities and the architectural performance events available in the processor. The details are

described in Chapter 24, “Introduction to Virtual Machine Extensions,” in the Intel^® 64 and IA-32 Architectures

Software Developer’s Manual, Volume 3C.

INPUT EAX = 0BH: Returns Extended Topology Information

CPUID leaf 1FH is a preferred superset to leaf 0BH. Intel recommends first checking for the existence of Leaf 1FH

before using leaf 0BH.

When CPUID executes with EAX set to 0BH, the processor returns information about extended topology enumera-

tion data. Software must detect the presence of CPUID leaf 0BH by verifying (a) the highest leaf index supported

by CPUID is >= 0BH, and (b) CPUID.0BH:EBX[15:0] reports a non-zero value. See Table 3-8.

INPUT EAX = 0DH: Returns Processor Extended States Enumeration Information

When CPUID executes with EAX set to 0DH and ECX = 0, the processor returns information about the bit-vector

representation of all processor state extensions that are supported in the processor and storage size requirements

of the XSAVE/XRSTOR area. See Table 3-8.

When CPUID executes with EAX set to 0DH and ECX = n (n > 1, and is a valid sub-leaf index), the processor returns

information about the size and offset of each processor extended state save area within the XSAVE/XRSTOR area.

See Table 3-8. Software can use the forward-extendable technique depicted below to query the valid sub-leaves

and obtain size and offset information for each processor extended state save area:

For i = 2 to 62 // sub-leaf 1 is reserved

IF (CPUID.(EAX=0DH, ECX=0H):VECTOR[i] = 1 ) // VECTOR is the 64-bit value of EDX:EAX

Execute CPUID.(EAX=0DH, ECX = i) to examine size and offset for sub-leaf i;

FI;

INPUT EAX = 0FH: Returns Intel Resource Director Technology (Intel RDT) Monitoring Enumeration Information

When CPUID executes with EAX set to 0FH and ECX = 0, the processor returns information about the bit-vector

representation of QoS monitoring resource types that are supported in the processor and maximum range of RMID

values the processor can use to monitor of any supported resource types. Each bit, starting from bit 1, corresponds

to a specific resource type if the bit is set. The bit position corresponds to the sub-leaf index (or ResID) that soft-

ware must use to query QoS monitoring capability available for that type. See Table 3-8.

When CPUID executes with EAX set to 0FH and ECX = n (n >= 1, and is a valid ResID), the processor returns infor-

mation software can use to program IA32_PQR_ASSOC, IA32_QM_EVTSEL MSRs before reading QoS data from the

IA32_QM_CTR MSR.

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INSTRUCTION SET REFERENCE, A-L

INPUT EAX = 10H: Returns Intel Resource Director Technology (Intel RDT) Allocation Enumeration Information

When CPUID executes with EAX set to 10H and ECX = 0, the processor returns information about the bit-vector

representation of QoS Enforcement resource types that are supported in the processor. Each bit, starting from bit

1, corresponds to a specific resource type if the bit is set. The bit position corresponds to the sub-leaf index (or

ResID) that software must use to query QoS enforcement capability available for that type. See Table 3-8.

When CPUID executes with EAX set to 10H and ECX = n (n >= 1, and is a valid ResID), the processor returns infor-

mation about available classes of service and range of QoS mask MSRs that software can use to configure each

class of services using capability bit masks in the QoS Mask registers, IA32_resourceType_Mask_n.

INPUT EAX = 12H: Returns Intel SGX Enumeration Information

When CPUID executes with EAX set to 12H and ECX = 0H, the processor returns information about Intel SGX capa-

bilities. See Table 3-8.

When CPUID executes with EAX set to 12H and ECX = 1H, the processor returns information about Intel SGX attri-

butes. See Table 3-8.

When CPUID executes with EAX set to 12H and ECX = n (n > 1), the processor returns information about Intel SGX

Enclave Page Cache. See Table 3-8.

INPUT EAX = 14H: Returns Intel Processor Trace Enumeration Information

When CPUID executes with EAX set to 14H and ECX = 0H, the processor returns information about Intel Processor

Trace extensions. See Table 3-8.

When CPUID executes with EAX set to 14H and ECX = n (n > 0 and less than the number of non-zero bits in

CPUID.(EAX=14H, ECX= 0H).EAX), the processor returns information about packet generation in Intel Processor

Trace. See Table 3-8.

INPUT EAX = 15H: Returns Time Stamp Counter and Nominal Core Crystal Clock Information

When CPUID executes with EAX set to 15H and ECX = 0H, the processor returns information about Time Stamp

Counter and Core Crystal Clock. See Table 3-8.

INPUT EAX = 16H: Returns Processor Frequency Information

When CPUID executes with EAX set to 16H, the processor returns information about Processor Frequency Informa-

tion. See Table 3-8.

INPUT EAX = 17H: Returns System-On-Chip Information

When CPUID executes with EAX set to 17H, the processor returns information about the System-On-Chip Vendor

Attribute Enumeration. See Table 3-8.

INPUT EAX = 18H: Returns Deterministic Address Translation Parameters Information

When CPUID executes with EAX set to 18H, the processor returns information about the Deterministic Address

Translation Parameters. See Table 3-8.

INPUT EAX = 19H: Returns Key Locker Information

When CPUID executes with EAX set to 19H, the processor returns information about Key Locker. See Table 3-8.

INPUT EAX = 1AH: Returns Native Model ID Information

When CPUID executes with EAX set to 1AH, the processor returns information about Native Model Identification.

See Table 3-8.

INPUT EAX = 1BH: Returns PCONFIG Information

When CPUID executes with EAX set to 1BH, the processor returns information about PCONFIG capabilities. This

information is enumerated in sub-leaves selected by the value of ECX (starting with 0).

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INSTRUCTION SET REFERENCE, A-L

Each sub-leaf of CPUID function 1BH enumerates its sub-leaf type in EAX. If a sub-leaf type is 0, the sub-leaf is

invalid and zero is returned in EBX, ECX, and EDX. In this case, all subsequent sub-leaves (selected by larger input

values of ECX) are also invalid.

The only valid sub-leaf type currently defined is 1, indicating that the sub-leaf enumerates target identifiers for the

PCONFIG instruction. Any non-zero value returned in EBX, ECX, or EDX indicates a valid target identifier of the

PCONFIG instruction (any value of zero should be ignored). The only target identifier currently defined is 1, indi-

cating TME-MK. See the “PCONFIG-Platform Configuration” instruction in Chapter 4 of the Intel^® 64 and IA-32

Architectures Software Developer’s Manual, Volume 2B, for more information.

INPUT EAX = 1CH: Returns Last Branch Record Information

When CPUID executes with EAX set to 1CH, the processor returns information about LBRs (the architectural

feature). See Table 3-8.

INPUT EAX = 1DH: Returns Tile Information

When CPUID executes with EAX set to 1DH and ECX = 0H, the processor returns information about tile

architecture. See Table 3-8.

When CPUID executes with EAX set to 1DH and ECX = 1H, the processor returns information about tile palette 1.

See Table 3-8.

INPUT EAX = 1EH: Returns TMUL Information

When CPUID executes with EAX set to 1EH and ECX = 0H, the processor returns information about TMUL

capabilities. See Table 3-8.

INPUT EAX = 1FH: Returns V2 Extended Topology Information

When CPUID executes with EAX set to 1FH, the processor returns information about extended topology enumera-

tion data. Software must detect the presence of CPUID leaf 1FH by verifying (a) the highest leaf index supported

by CPUID is >= 1FH, and (b) CPUID.1FH:EBX[15:0] reports a non-zero value. See Table 3-8.

INPUT EAX = 20H: Returns History Reset Information

When CPUID executes with EAX set to 20H, the processor returns information about History Reset. See Table 3-8.

METHODS FOR RETURNING BRANDING INFORMATION

Use the following techniques to access branding information:

1. Processor brand string method.

2. Processor brand index; this method uses a software supplied brand string table.

These two methods are discussed in the following sections. For methods that are available in early processors, see

Section: “Identification of Earlier IA-32 Processors” in Chapter 20 of the Intel^® 64 and IA-32 Architectures Soft-

ware Developer’s Manual, Volume 1.

The Processor Brand String Method

Figure 3-9 describes the algorithm used for detection of the brand string. Processor brand identification software

should execute this algorithm on all Intel 64 and IA-32 processors.

This method (introduced with Pentium 4 processors) returns an ASCII brand identification string and the Processor

Base frequency of the processor to the EAX, EBX, ECX, and EDX registers.

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INSTRUCTION SET REFERENCE, A-L

Input: EAX=

0x80000000

CPUID

False

Processor Brand

IF (EAX & 0x80000000)

String Not

Supported

CPUID

True ≥

Function

Extended

Supported

EAX Return Value =

Max. Extended CPUID

Function Index

True

IF (EAX Return Value

Processor Brand

String Supported

≥ 0x80000004)

OM15194

Figure 3-9. Determination of Support for the Processor Brand String

How Brand Strings Work

To use the brand string method, execute CPUID with EAX input of 8000002H through 80000004H. For each input

value, CPUID returns 16 ASCII characters using EAX, EBX, ECX, and EDX. The returned string will be NULL-termi-

nated.

Table 3-13 shows the brand string that is returned by the first processor in the Pentium 4 processor family.

Table 3-13. Processor Brand String Returned with Pentium 4 Processor

EAX Input Value

Return Values

ASCII Equivalent

80000002H

EAX = 20202020H

“

”

EBX = 20202020H

“

”

ECX = 20202020H

“

”

EDX = 6E492020H

“nI ”

80000003H

EAX = 286C6574H

“(let”

EBX = 50202952H

“P )R”

ECX = 69746E65H

“itne”

EDX = 52286D75H

“R(mu”

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INSTRUCTION SET REFERENCE, A-L

Table 3-13. Processor Brand String Returned with Pentium 4 Processor (Contd.)

EAX Input Value

Return Values

ASCII Equivalent

80000004H

EAX = 20342029H

“ 4 )”

EBX = 20555043H

“ UPC”

ECX = 30303531H

“0051”

EDX = 007A484DH

“\0zHM”

Extracting the Processor Frequency from Brand Strings

Figure 3-10 provides an algorithm which software can use to extract the Processor Base frequency from the

processor brand string.

Scan "Brand String" in

Reverse Byte Order

"zHM", or

Match

"zHG", or

Substring

"zHT"

False

IF Substring Matched

Report Error

Determine "Freq"

If "zHM"

True

and "Multiplier"

Multiplier = 1 x 10⁶

If "zHG"

Multiplier = 1 x 10⁹

Determine "Multiplier"

If "zHT"

Multiplier = 1 x 10¹²

Scan Digits

Until Blank

Reverse Digits

Determine "Freq"

In Reverse Order

To Decimal Value

Processor Base

Frequency =

"Freq" = X.YZ if

"Freq" x "Multiplier"

Digits = "ZY.X"

Figure 3-10. Algorithm for Extracting Processor Frequency

The Processor Brand Index Method

The brand index method (introduced with Pentium^® III Xeon^® processors) provides an entry point into a brand

identification table that is maintained in memory by system software and is accessible from system- and user-level

code. In this table, each brand index is associate with an ASCII brand identification string that identifies the official

Intel family and model number of a processor.

When CPUID executes with EAX set to 1, the processor returns a brand index to the low byte in EBX. Software can

then use this index to locate the brand identification string for the processor in the brand identification table. The

first entry (brand index 0) in this table is reserved, allowing for backward compatibility with processors that do not

support the brand identification feature. Starting with processor signature family ID = 0FH, model = 03H, brand

index method is no longer supported. Use brand string method instead.

Table 3-14 shows brand indices that have identification strings associated with them.

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INSTRUCTION SET REFERENCE, A-L

Table 3-14. Mapping of Brand Indices; and Intel 64 and IA-32 Processor Brand Strings

Brand Index

Brand String

00H

This processor does not support the brand identification feature

01H

Intel(R) Celeron(R) processor¹

02H

Intel(R) Pentium(R) III processor¹

03H

Intel(R) Pentium(R) III Xeon(R) processor; If processor signature = 000006B1h, then Intel(R) Celeron(R)

processor

04H

Intel(R) Pentium(R) III processor

06H

Mobile Intel(R) Pentium(R) III processor-M

07H

Mobile Intel(R) Celeron(R) processor¹

08H

Intel(R) Pentium(R) 4 processor

09H

Intel(R) Pentium(R) 4 processor

0AH

Intel(R) Celeron(R) processor¹

0BH

Intel(R) Xeon(R) processor; If processor signature = 00000F13h, then Intel(R) Xeon(R) processor MP

0CH

Intel(R) Xeon(R) processor MP

0EH

Mobile Intel(R) Pentium(R) 4 processor-M; If processor signature = 00000F13h, then Intel(R) Xeon(R) processor

0FH

Mobile Intel(R) Celeron(R) processor¹

11H

Mobile Genuine Intel(R) processor

12H

Intel(R) Celeron(R) M processor

13H

Mobile Intel(R) Celeron(R) processor¹

14H

Intel(R) Celeron(R) processor

15H

Mobile Genuine Intel(R) processor

16H

Intel(R) Pentium(R) M processor

17H

Mobile Intel(R) Celeron(R) processor¹

18H - 0FFH

RESERVED

NOTES:

1. Indicates versions of these processors that were introduced after the Pentium III

IA-32 Architecture Compatibility

CPUID is not supported in early models of the Intel486 processor or in any IA-32 processor earlier than the

Intel486 processor.

Operation

IA32_BIOS_SIGN_ID MSR := Update with installed microcode revision number;

CASE (EAX) OF

EAX = 0:

EAX := Highest basic function input value understood by CPUID;

EBX := Vendor identification string;

EDX := Vendor identification string;

ECX := Vendor identification string;

BREAK;

EAX = 1H:

EAX[3:0] := Stepping ID;

EAX[7:4] := Model;

EAX[11:8] := Family;

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EAX[13:12] := Processor type;

EAX[15:14] := Reserved;

EAX[19:16] := Extended Model;

EAX[27:20] := Extended Family;

EAX[31:28] := Reserved;

EBX[7:0] := Brand Index; (* Reserved if the value is zero. *)

EBX[15:8] := CLFLUSH Line Size;

EBX[16:23] := Reserved; (* Number of threads enabled = 2 if MT enable fuse set. *)

EBX[24:31] := Initial APIC ID;

ECX := Feature flags; (* See Figure 3-7. *)

EDX := Feature flags; (* See Figure 3-8. *)

BREAK;

EAX = 2H:

EAX := Cache and TLB information;

EBX := Cache and TLB information;

ECX := Cache and TLB information;

EDX := Cache and TLB information;

BREAK;

EAX = 3H:

EAX := Reserved;

EBX := Reserved;

ECX := ProcessorSerialNumber[31:0];

(* Pentium III processors only, otherwise reserved. *)

EDX := ProcessorSerialNumber[63:32];

(* Pentium III processors only, otherwise reserved. *

BREAK

EAX = 4H:

EAX := Deterministic Cache Parameters Leaf; (* See Table 3-8. *)

EBX := Deterministic Cache Parameters Leaf;

ECX := Deterministic Cache Parameters Leaf;

EDX := Deterministic Cache Parameters Leaf;

BREAK;

EAX = 5H:

EAX := MONITOR/MWAIT Leaf; (* See Table 3-8. *)

EBX := MONITOR/MWAIT Leaf;

ECX := MONITOR/MWAIT Leaf;

EDX := MONITOR/MWAIT Leaf;

BREAK;

EAX = 6H:

EAX := Thermal and Power Management Leaf; (* See Table 3-8. *)

EBX := Thermal and Power Management Leaf;

ECX := Thermal and Power Management Leaf;

EDX := Thermal and Power Management Leaf;

BREAK;

EAX = 7H:

EAX := Structured Extended Feature Flags Enumeration Leaf; (* See Table 3-8. *)

EBX := Structured Extended Feature Flags Enumeration Leaf;

ECX := Structured Extended Feature Flags Enumeration Leaf;

EDX := Structured Extended Feature Flags Enumeration Leaf;

BREAK;

EAX = 8H:

EAX := Reserved = 0;

EBX := Reserved = 0;

ECX := Reserved = 0;

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EDX := Reserved = 0;

BREAK;

EAX = 9H:

EAX := Direct Cache Access Information Leaf; (* See Table 3-8. *)

EBX := Direct Cache Access Information Leaf;

ECX := Direct Cache Access Information Leaf;

EDX := Direct Cache Access Information Leaf;

BREAK;

EAX = AH:

EAX := Architectural Performance Monitoring Leaf; (* See Table 3-8. *)

EBX := Architectural Performance Monitoring Leaf;

ECX := Architectural Performance Monitoring Leaf;

EDX := Architectural Performance Monitoring Leaf;

BREAK

EAX = BH:

EAX := Extended Topology Enumeration Leaf; (* See Table 3-8. *)

EBX := Extended Topology Enumeration Leaf;

ECX := Extended Topology Enumeration Leaf;

EDX := Extended Topology Enumeration Leaf;

BREAK;

EAX = CH:

EAX := Reserved = 0;

EBX := Reserved = 0;

ECX := Reserved = 0;

EDX := Reserved = 0;

BREAK;

EAX = DH:

EAX := Processor Extended State Enumeration Leaf; (* See Table 3-8. *)

EBX := Processor Extended State Enumeration Leaf;

ECX := Processor Extended State Enumeration Leaf;

EDX := Processor Extended State Enumeration Leaf;

BREAK;

EAX = EH:

EAX := Reserved = 0;

EBX := Reserved = 0;

ECX := Reserved = 0;

EDX := Reserved = 0;

BREAK;

EAX = FH:

EAX := Intel Resource Director Technology Monitoring Enumeration Leaf; (* See Table 3-8. *)

EBX := Intel Resource Director Technology Monitoring Enumeration Leaf;

ECX := Intel Resource Director Technology Monitoring Enumeration Leaf;

EDX := Intel Resource Director Technology Monitoring Enumeration Leaf;

BREAK;

EAX = 10H:

EAX := Intel Resource Director Technology Allocation Enumeration Leaf; (* See Table 3-8. *)

EBX := Intel Resource Director Technology Allocation Enumeration Leaf;

ECX := Intel Resource Director Technology Allocation Enumeration Leaf;

EDX := Intel Resource Director Technology Allocation Enumeration Leaf;

BREAK;

EAX = 12H:

EAX := Intel SGX Enumeration Leaf; (* See Table 3-8. *)

EBX := Intel SGX Enumeration Leaf;

ECX := Intel SGX Enumeration Leaf;

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INSTRUCTION SET REFERENCE, A-L

EDX := Intel SGX Enumeration Leaf;

BREAK;

EAX = 14H:

EAX := Intel Processor Trace Enumeration Leaf; (* See Table 3-8. *)

EBX := Intel Processor Trace Enumeration Leaf;

ECX := Intel Processor Trace Enumeration Leaf;

EDX := Intel Processor Trace Enumeration Leaf;

BREAK;

EAX = 15H:

EAX := Time Stamp Counter and Nominal Core Crystal Clock Information Leaf; (* See Table 3-8. *)

EBX := Time Stamp Counter and Nominal Core Crystal Clock Information Leaf;

ECX := Time Stamp Counter and Nominal Core Crystal Clock Information Leaf;

EDX := Time Stamp Counter and Nominal Core Crystal Clock Information Leaf;

BREAK;

EAX = 16H:

EAX := Processor Frequency Information Enumeration Leaf; (* See Table 3-8. *)

EBX := Processor Frequency Information Enumeration Leaf;

ECX := Processor Frequency Information Enumeration Leaf;

EDX := Processor Frequency Information Enumeration Leaf;

BREAK;

EAX = 17H:

EAX := System-On-Chip Vendor Attribute Enumeration Leaf; (* See Table 3-8. *)

EBX := System-On-Chip Vendor Attribute Enumeration Leaf;

ECX := System-On-Chip Vendor Attribute Enumeration Leaf;

EDX := System-On-Chip Vendor Attribute Enumeration Leaf;

BREAK;

EAX = 18H:

EAX := Deterministic Address Translation Parameters Enumeration Leaf; (* See Table 3-8. *)

EBX := Deterministic Address Translation Parameters Enumeration Leaf;

ECX := Deterministic Address Translation Parameters Enumeration Leaf;

EDX := Deterministic Address Translation Parameters Enumeration Leaf;

BREAK;

EAX = 19H:

EAX := Key Locker Enumeration Leaf; (* See Table 3-8. *)

EBX := Key Locker Enumeration Leaf;

ECX := Key Locker Enumeration Leaf;

EDX := Key Locker Enumeration Leaf;

BREAK;

EAX = 1AH:

EAX := Native Model ID Enumeration Leaf; (* See Table 3-8. *)

EBX := Native Model ID Enumeration Leaf;

ECX := Native Model ID Enumeration Leaf;

EDX := Native Model ID Enumeration Leaf;

BREAK;

EAX = 1BH:

EAX := PCONFIG Information Enumeration Leaf; (* See “INPUT EAX = 1BH: Returns PCONFIG Information” on page 3-253. *)

EBX := PCONFIG Information Enumeration Leaf;

ECX := PCONFIG Information Enumeration Leaf;

EDX := PCONFIG Information Enumeration Leaf;

BREAK;

EAX = 1CH:

EAX := Last Branch Record Information Enumeration Leaf; (* See Table 3-8. *)

EBX := Last Branch Record Information Enumeration Leaf;

ECX := Last Branch Record Information Enumeration Leaf;

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INSTRUCTION SET REFERENCE, A-L

EDX := Last Branch Record Information Enumeration Leaf;

BREAK;

EAX = 1DH:

EAX := Tile Information Enumeration Leaf; (* See Table 3-8. *)

EBX := Tile Information Enumeration Leaf;

ECX := Tile Information Enumeration Leaf;

EDX := Tile Information Enumeration Leaf;

BREAK;

EAX = 1EH:

EAX := TMUL Information Enumeration Leaf; (* See Table 3-8. *)

EBX := TMUL Information Enumeration Leaf;

ECX := TMUL Information Enumeration Leaf;

EDX := TMUL Information Enumeration Leaf;

BREAK;

EAX = 1FH:

EAX := V2 Extended Topology Enumeration Leaf; (* See Table 3-8. *)

EBX := V2 Extended Topology Enumeration Leaf;

ECX := V2 Extended Topology Enumeration Leaf;

EDX := V2 Extended Topology Enumeration Leaf;

BREAK;

EAX = 20H:

EAX := Processor History Reset Sub-leaf; (* See Table 3-8. *)

EBX := Processor History Reset Sub-leaf;

ECX := Processor History Reset Sub-leaf;

EDX := Processor History Reset Sub-leaf;

BREAK;

EAX = 80000000H:

EAX := Highest extended function input value understood by CPUID;

EBX := Reserved;

ECX := Reserved;

EDX := Reserved;

BREAK;

EAX = 80000001H:

EAX := Reserved;

EBX := Reserved;

ECX := Extended Feature Bits (* See Table 3-8.*);

EDX := Extended Feature Bits (* See Table 3-8. *);

BREAK;

EAX = 80000002H:

EAX := Processor Brand String;

EBX := Processor Brand String, continued;

ECX := Processor Brand String, continued;

EDX := Processor Brand String, continued;

BREAK;

EAX = 80000003H:

EAX := Processor Brand String, continued;

EBX := Processor Brand String, continued;

ECX := Processor Brand String, continued;

EDX := Processor Brand String, continued;

BREAK;

EAX = 80000004H:

EAX := Processor Brand String, continued;

EBX := Processor Brand String, continued;

ECX := Processor Brand String, continued;

CPUID-CPU Identification

Vol. 2A

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INSTRUCTION SET REFERENCE, A-L

EDX := Processor Brand String, continued;

BREAK;

EAX = 80000005H:

EAX := Reserved = 0;

EBX := Reserved = 0;

ECX := Reserved = 0;

EDX := Reserved = 0;

BREAK;

EAX = 80000006H:

EAX := Reserved = 0;

EBX := Reserved = 0;

ECX := Cache information;

EDX := Reserved = 0;

BREAK;

EAX = 80000007H:

EAX := Reserved = 0;

EBX := Reserved = 0;

ECX := Reserved = 0;

EDX := Reserved = Misc Feature Flags;

BREAK;

EAX = 80000008H:

EAX := Address Size Information;

EBX := Misc Feature Flags;

ECX := Reserved = 0;

EDX := Reserved = 0;

BREAK;

EAX >= 40000000H and EAX <= 4FFFFFFFH:

DEFAULT: (* EAX = Value outside of recognized range for CPUID. *)

(* If the highest basic information leaf data depend on ECX input value, ECX is honored.*)

EAX := Reserved; (* Information returned for highest basic information leaf. *)

EBX := Reserved; (* Information returned for highest basic information leaf. *)

ECX := Reserved; (* Information returned for highest basic information leaf. *)

EDX := Reserved; (* Information returned for highest basic information leaf. *)

BREAK;

ESAC;

Flags Affected

None.

Exceptions (All Operating Modes)

#UD

If the LOCK prefix is used.

In earlier IA-32 processors that do not support the CPUID instruction, execution of the instruc-

tion results in an invalid opcode (#UD) exception being generated.

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INSTRUCTION SET REFERENCE, A-L

INVD-Invalidate Internal Caches

Opcode¹

Instruction

Op/

64-Bit

Compat/

Description

Mode

Leg Mode

0F 08

INVD

Valid

Flush internal caches; initiate flushing of

external caches.

NOTES:

1. See the IA-32 Architecture Compatibility section below.

Instruction Operand Encoding

Op/En

Operand 1

Operand 2

Operand 3

Operand 4

N/A

Description

Invalidates (flushes) the processor’s internal caches and issues a special-function bus cycle that directs external

caches to also flush themselves. Data held in internal caches is not written back to main memory.

After executing this instruction, the processor does not wait for the external caches to complete their flushing oper-

ation before proceeding with instruction execution. It is the responsibility of hardware to respond to the cache flush

signal.

The INVD instruction is a privileged instruction. When the processor is running in protected mode, the CPL of a

program or procedure must be 0 to execute this instruction.

The INVD instruction may be used when the cache is used as temporary memory and the cache contents need to

be invalidated rather than written back to memory. When the cache is used as temporary memory, no external

device should be actively writing data to main memory.

Use this instruction with care. Data cached internally and not written back to main memory will be lost. Note that

any data from an external device to main memory (for example, via a PCIWrite) can be temporarily stored in the

caches; these data can be lost when an INVD instruction is executed. Unless there is a specific requirement or

benefit to flushing caches without writing back modified cache lines (for example, temporary memory, testing, or

fault recovery where cache coherency with main memory is not a concern), software should instead use the

WBINVD instruction.

On processors that support processor reserved memory, the INVD instruction cannot be executed when processor

reserved memory protections are activated. See Section 36.5, “EPC and Management of EPC Pages,” in the Intel^®

64 and IA-32 Architectures Software Developer’s Manual, Volume 3D.

Some processors prevent execution of INVD after BIOS execution is complete. They report this by enumerating

CPUID.(EAX=07H,ECX=1H):EAX[bit 30] as 1. On such processors, INVD cannot be executed if bit 0 of

SR_BIOS_DONE (MSR address 151H) is 1.

This instruction’s operation is the same in non-64-bit modes and 64-bit mode.

IA-32 Architecture Compatibility

The INVD instruction is implementation dependent; it may be implemented differently on different families of Intel

64 or IA-32 processors. This instruction is not supported on IA-32 processors earlier than the Intel486 processor.

Operation

Flush(InternalCaches);

SignalFlush(ExternalCaches);

Continue (* Continue execution *)

Flags Affected

None.

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INSTRUCTION SET REFERENCE, M-U

PREFETCHW-Prefetch Data Into Caches in Anticipation of a Write

Opcode/

Op/

64/32 bit

CPUID

Description

Instruction

Mode

Feature Flag

Support

0F 0D /1

V/V

PREFETCHW

Move data from m8 closer to the processor in anticipation of a

PREFETCHW m8

write.

Instruction Operand Encoding

Op/En

Operand 1

Operand 2

Operand 3

Operand 4

ModRM:r/m (r)

N/A

Description

Fetches the cache line of data from memory that contains the byte specified with the source operand to a location

in the 1st or 2nd level cache and invalidates other cached instances of the line.

The source operand is a byte memory location. If the line selected is already present in the lowest level cache and

is already in an exclusively owned state, no data movement occurs. Prefetches from non-writeback memory are

ignored.

The PREFETCHW instruction is merely a hint and does not affect program behavior. If executed, this instruction

moves data closer to the processor and invalidates other cached copies in anticipation of the line being written to

in the future.

The characteristic of prefetch locality hints is implementation-dependent, and can be overloaded or ignored by a

processor implementation. The amount of data prefetched is also processor implementation-dependent. It will,

however, be a minimum of 32 bytes. Additional details of the implementation-dependent locality hints are

described in Section 7.4 of Intel® 64 and IA-32 Architectures Optimization Reference Manual.

It should be noted that processors are free to speculatively fetch and cache data with exclusive ownership from

system memory regions that permit such accesses (that is, the WB memory type). A PREFETCHW instruction is

considered a hint to this speculative behavior. Because this speculative fetching can occur at any time and is not

tied to instruction execution, a PREFETCHW instruction is not ordered with respect to the fence instructions

(MFENCE, SFENCE, and LFENCE) or locked memory references. A PREFETCHW instruction is also unordered with

respect to CLFLUSH and CLFLUSHOPT instructions, other PREFETCHW instructions, or any other general instruction

It is ordered with respect to serializing instructions such as CPUID, WRMSR, OUT, and MOV CR.

This instruction's operation is the same in non-64-bit modes and 64-bit mode.

Operation

FETCH_WITH_EXCLUSIVE_OWNERSHIP (m8);

Flags Affected

None.

C/C++ Compiler Intrinsic Equivalent

void _m_prefetchw( void * );

Protected Mode Exceptions

#UD

If the LOCK prefix is used.

Real-Address Mode Exceptions

#UD

If the LOCK prefix is used.

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7. Updates to Chapter 5, Volume 2C

Change bars and violet text show changes to Chapter 5 of the Intel^® 64 and IA-32 Architectures Software

Developer’s Manual, Volume 2C: Instruction Set Reference, V.

------------------------------------------------------------------------------------------

Changes to this chapter:

• Updated the VPBLENDD instruction to use “dword” instead of “word” since the instruction operates on dwords.

• Updated the VGETMANTSS instruction to change “Vector” to “Scalar” in the instruction title.

• Updated the VFCMADDCPH/VFMADDCPH instructions to correct the description box for both the normal and

complex conjugate forms. They erroneously reported the opposite descriptions and needed a wording change.

• Updated the VFCMADDCSH/VFMADDCSH instructions to correct the description box for both the normal and

complex conjugate forms. They erroneously reported the opposite descriptions and needed a wording change.

Removed two duplicate intrinsics for the VFCMADDCSH instruction and added two missing intrinsics for the

VFMADDCSH instruction.

• Updated the VFCMULCPH/VFMULCPH instructions to correct the description box for both the normal and

complex conjugate forms. They erroneously reported the opposite descriptions and needed a wording change.

• Updated the VFCMULCSH/VFMULCSH instructions to correct the description box for both the normal and

complex conjugate forms. They erroneously reported the opposite descriptions and needed a wording change.

Intel® 64 and IA-32 Architectures Software Developer’s Manual Documentation Changes

INSTRUCTION SET REFERENCE, V

VFCMADDCPH/VFMADDCPH-Complex Multiply and Accumulate FP16 Values

Opcode/

Op/

64/32

CPUID Feature

Description

Instruction

Bit Mode

Flag

Support

EVEX.128.F2.MAP6.W0 56 /r

V/V

AVX512-FP16

Complex multiply a pair of FP16 values from

VFCMADDCPH xmm1{k1}{z}, xmm2,

AVX512VL

xmm2 and complex conjugate of

xmm3/m128/m32bcst

xmm3/m128/m32bcst, add to xmm1 and store

the result in xmm1 subject to writemask k1.

EVEX.256.F2.MAP6.W0 56 /r

V/V

AVX512-FP16

Complex multiply a pair of FP16 values from

VFCMADDCPH ymm1{k1}{z}, ymm2,

AVX512VL

ymm2 and complex conjugate of

ymm3/m256/m32bcst

ymm3/m256/m32bcst, add to ymm1 and store

the result in ymm1 subject to writemask k1.

EVEX.512.F2.MAP6.W0 56 /r

V/V

AVX512-FP16

Complex multiply a pair of FP16 values from

VFCMADDCPH zmm1{k1}{z}, zmm2,

zmm2 and complex conjugate of

zmm3/m512/m32bcst {er}

zmm3/m512/m32bcst, add to zmm1 and store

the result in zmm1 subject to writemask k1.

EVEX.128.F3.MAP6.W0 56 /r

V/V

AVX512-FP16

Complex multiply a pair of FP16 values from

VFMADDCPH xmm1{k1}{z}, xmm2,

AVX512VL

xmm2 and xmm3/m128/m32bcst, add to xmm1

xmm3/m128/m32bcst

and store the result in xmm1 subject to

writemask k1.

EVEX.256.F3.MAP6.W0 56 /r

V/V

AVX512-FP16

Complex multiply a pair of FP16 values from

VFMADDCPH ymm1{k1}{z}, ymm2,

AVX512VL

ymm2 and ymm3/m256/m32bcst, add to ymm1

ymm3/m256/m32bcst

and store the result in ymm1 subject to

writemask k1.

EVEX.512.F3.MAP6.W0 56 /r

V/V

AVX512-FP16

Complex multiply a pair of FP16 values from

VFMADDCPH zmm1{k1}{z}, zmm2,

zmm2 and zmm3/m512/m32bcst, add to zmm1

zmm3/m512/m32bcst {er}

and store the result in zmm1 subject to

writemask k1.

Instruction Operand Encoding

Op/En

Tuple

Operand 1

Operand 2

Operand 3

Operand 4

Full

ModRM:reg (r, w)

VEX.vvvv (r)

ModRM:r/m (r)

N/A

Description

This instruction performs a complex multiply and accumulate operation. There are normal and complex conjugate

forms of the operation.

The broadcasting and masking for this operation is done on 32-bit quantities representing a pair of FP16 values.

Rounding is performed at every FMA (fused multiply and add) boundary. Execution occurs as if all MXCSR excep-

tions are masked. MXCSR status bits are updated to reflect exceptional conditions.

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INSTRUCTION SET REFERENCE, V

Operation

VFCMADDCPH dest{k1}, src1, src2 (AVX512)

VL = 128, 256, 512

KL := VL / 32

FOR i := 0 to KL-1:

IF k1[i] or *no writemask*:

IF broadcasting and src2 is memory:

tsrc2.fp16[2*i+0] := src2.fp16[0]

tsrc2.fp16[2*i+1] := src2.fp16[1]

ELSE:

tsrc2.fp16[2*i+0] := src2.fp16[2*i+0]

tsrc2.fp16[2*i+1] := src2.fp16[2*i+1]

FOR i := 0 to KL-1:

IF k1[i] or *no writemask*:

tmp[2*i+0] := dest.fp16[2*i+0] + src1.fp16[2*i+0] * tsrc2.fp16[2*i+0]

tmp[2*i+1] := dest.fp16[2*i+1] + src1.fp16[2*i+1] * tsrc2.fp16[2*i+0]

FOR i := 0 to KL-1:

IF k1[i] or *no writemask*:

// conjugate version subtracts odd final term

dest.fp16[2*i+0] := tmp[2*i+0] + src1.fp16[2*i+1] * tsrc2.fp16[2*i+1]

dest.fp16[2*i+1] := tmp[2*i+1] - src1.fp16[2*i+0] * tsrc2.fp16[2*i+1]

ELSE IF *zeroing*:

dest.fp16[2*i+0] := 0

dest.fp16[2*i+1] := 0

DEST[MAXVL-1:VL] := 0

VFMADDCPH dest{k1}, src1, src2 (AVX512)

VL = 128, 256, 512

KL := VL / 32

FOR i := 0 to KL-1:

IF k1[i] or *no writemask*:

IF broadcasting and src2 is memory:

tsrc2.fp16[2*i+0] := src2.fp16[0]

tsrc2.fp16[2*i+1] := src2.fp16[1]

ELSE:

tsrc2.fp16[2*i+0] := src2.fp16[2*i+0]

tsrc2.fp16[2*i+1] := src2.fp16[2*i+1]

FOR i := 0 to KL-1:

IF k1[i] or *no writemask*:

tmp[2*i+0] := dest.fp16[2*i+0] + src1.fp16[2*i+0] * tsrc2.fp16[2*i+0]

tmp[2*i+1] := dest.fp16[2*i+1] + src1.fp16[2*i+1] * tsrc2.fp16[2*i+0]

FOR i := 0 to KL-1:

IF k1[i] or *no writemask*:

// non-conjugate version subtracts even term

dest.fp16[2*i+0] := tmp[2*i+0] - src1.fp16[2*i+1] * tsrc2.fp16[2*i+1]

dest.fp16[2*i+1] := tmp[2*i+1] + src1.fp16[2*i+0] * tsrc2.fp16[2*i+1]

ELSE IF *zeroing*:

VFCMADDCPH/VFMADDCPH-Complex Multiply and Accumulate FP16 Values

Vol. 2C

5-171

INSTRUCTION SET REFERENCE, V

dest.fp16[2*i+0] := 0

dest.fp16[2*i+1] := 0

DEST[MAXVL-1:VL] := 0

Intel C/C++ Compiler Intrinsic Equivalent

VFCMADDCPH __m128h _mm_fcmadd_pch (__m128h a, __m128h b, __m128h c);

VFCMADDCPH __m128h _mm_mask_fcmadd_pch (__m128h a, __mmask8 k, __m128h b, __m128h c);

VFCMADDCPH __m128h _mm_mask3_fcmadd_pch (__m128h a, __m128h b, __m128h c, __mmask8 k);

VFCMADDCPH __m128h _mm_maskz_fcmadd_pch (__mmask8 k, __m128h a, __m128h b, __m128h c);

VFCMADDCPH __m256h _mm256_fcmadd_pch (__m256h a, __m256h b, __m256h c);

VFCMADDCPH __m256h _mm256_mask_fcmadd_pch (__m256h a, __mmask8 k, __m256h b, __m256h c);

VFCMADDCPH __m256h _mm256_mask3_fcmadd_pch (__m256h a, __m256h b, __m256h c, __mmask8 k);

VFCMADDCPH __m256h _mm256_maskz_fcmadd_pch (__mmask8 k, __m256h a, __m256h b, __m256h c);

VFCMADDCPH __m512h _mm512_fcmadd_pch (__m512h a, __m512h b, __m512h c);

VFCMADDCPH __m512h _mm512_mask_fcmadd_pch (__m512h a, __mmask16 k, __m512h b, __m512h c);

VFCMADDCPH __m512h _mm512_mask3_fcmadd_pch (__m512h a, __m512h b, __m512h c, __mmask16 k);

VFCMADDCPH __m512h _mm512_maskz_fcmadd_pch (__mmask16 k, __m512h a, __m512h b, __m512h c);

VFCMADDCPH __m512h _mm512_fcmadd_round_pch (__m512h a, __m512h b, __m512h c, const int rounding);

VFCMADDCPH __m512h _mm512_mask_fcmadd_round_pch (__m512h a, __mmask16 k, __m512h b, __m512h c, const int rounding);

VFCMADDCPH __m512h _mm512_mask3_fcmadd_round_pch (__m512h a, __m512h b, __m512h c, __mmask16 k, const int rounding);

VFCMADDCPH __m512h _mm512_maskz_fcmadd_round_pch (__mmask16 k, __m512h a, __m512h b, __m512h c, const int rounding);

VFMADDCPH __m128h _mm_fmadd_pch (__m128h a, __m128h b, __m128h c);

VFMADDCPH __m128h _mm_mask_fmadd_pch (__m128h a, __mmask8 k, __m128h b, __m128h c);

VFMADDCPH __m128h _mm_mask3_fmadd_pch (__m128h a, __m128h b, __m128h c, __mmask8 k);

VFMADDCPH __m128h _mm_maskz_fmadd_pch (__mmask8 k, __m128h a, __m128h b, __m128h c);

VFMADDCPH __m256h _mm256_fmadd_pch (__m256h a, __m256h b, __m256h c);

VFMADDCPH __m256h _mm256_mask_fmadd_pch (__m256h a, __mmask8 k, __m256h b, __m256h c);

VFMADDCPH __m256h _mm256_mask3_fmadd_pch (__m256h a, __m256h b, __m256h c, __mmask8 k);

VFMADDCPH __m256h _mm256_maskz_fmadd_pch (__mmask8 k, __m256h a, __m256h b, __m256h c);

VFMADDCPH __m512h _mm512_fmadd_pch (__m512h a, __m512h b, __m512h c);

VFMADDCPH __m512h _mm512_mask_fmadd_pch (__m512h a, __mmask16 k, __m512h b, __m512h c);

VFMADDCPH __m512h _mm512_mask3_fmadd_pch (__m512h a, __m512h b, __m512h c, __mmask16 k);

VFMADDCPH __m512h _mm512_maskz_fmadd_pch (__mmask16 k, __m512h a, __m512h b, __m512h c);

VFMADDCPH __m512h _mm512_fmadd_round_pch (__m512h a, __m512h b, __m512h c, const int rounding);

VFMADDCPH __m512h _mm512_mask_fmadd_round_pch (__m512h a, __mmask16 k, __m512h b, __m512h c, const int rounding);

VFMADDCPH __m512h _mm512_mask3_fmadd_round_pch (__m512h a, __m512h b, __m512h c, __mmask16 k, const int rounding);

VFMADDCPH __m512h _mm512_maskz_fmadd_round_pch (__mmask16 k, __m512h a, __m512h b, __m512h c, const int rounding);

SIMD Floating-Point Exceptions

Invalid, Underflow, Overflow, Precision, Denormal.

Other Exceptions

EVEX-encoded instructions, see Table 2-49, “Type E4 Class Exception Conditions.”

Additionally:

#UD

If (dest_reg == src1_reg) or (dest_reg == src2_reg).

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INSTRUCTION SET REFERENCE, V

VFCMADDCSH/VFMADDCSH-Complex Multiply and Accumulate Scalar FP16 Values

Opcode/

Op/

64/32

CPUID Feature

Description

Instruction

Bit Mode

Flag

Support

EVEX.LLIG.F2.MAP6.W0 57 /r

V/V

AVX512-FP16

Complex multiply a pair of FP16 values from

VFCMADDCSH xmm1{k1}{z}, xmm2,

xmm2 and complex conjugate of xmm3/m32, add

xmm3/m32 {er}

to xmm1 and store the result in xmm1 subject to

writemask k1. Bits 127:32 of xmm2 are copied

to xmm1[127:32].

EVEX.LLIG.F3.MAP6.W0 57 /r

V/V

AVX512-FP16

Complex multiply a pair of FP16 values from

VFMADDCSH xmm1{k1}{z}, xmm2,

xmm2 and xmm3/m32, add to xmm1 and store

xmm3/m32 {er}

the result in xmm1 subject to writemask k1. Bits

127:32 of xmm2 are copied to xmm1[127:32].

Instruction Operand Encoding

Op/En

Tuple

Operand 1

Operand 2

Operand 3

Operand 4

Scalar

ModRM:reg (r, w)

VEX.vvvv (r)

ModRM:r/m (r)

N/A

Description

This instruction performs a complex multiply and accumulate operation. There are normal and complex conjugate

forms of the operation.

The masking for this operation is done on 32-bit quantities representing a pair of FP16 values.

Bits 127:32 of the destination operand are copied from the corresponding bits of the first source operand. Bits

MAXVL-1:128 of the destination operand are zeroed. The low FP16 element of the destination is updated according

to the writemask.

Rounding is performed at every FMA (fused multiply and add) boundary. Execution occurs as if all MXCSR excep-

tions are masked. MXCSR status bits are updated to reflect exceptional conditions.

Operation

VFCMADDCSH dest{k1}, src1, src2 (AVX512)

IF k1[0] or *no writemask*:

tmp[0] := dest.fp16[0] + src1.fp16[0] * src2.fp16[0]

tmp[1] := dest.fp16[1] + src1.fp16[1] * src2.fp16[0]

// conjugate version subtracts odd final term

dest.fp16[0] := tmp[0] + src1.fp16[1] * src2.fp16[1]

dest.fp16[1] := tmp[1] - src1.fp16[0] * src2.fp16[1]

ELSE IF *zeroing*:

dest.fp16[0] := 0

dest.fp16[1] := 0

DEST[127:32] := src1[127:32] // copy upper part of src1

DEST[MAXVL-1:128] := 0

VFCMADDCSH/VFMADDCSH-Complex Multiply and Accumulate Scalar FP16 Values

Vol. 2C

5-173

INSTRUCTION SET REFERENCE, V

VFMADDCSH dest{k1}, src1, src2 (AVX512)

IF k1[0] or *no writemask*:

tmp[0] := dest.fp16[0] + src1.fp16[0] * src2.fp16[0]

tmp[1] := dest.fp16[1] + src1.fp16[1] * src2.fp16[0]

// non-conjugate version subtracts last even term

dest.fp16[0] := tmp[0] - src1.fp16[1] * src2.fp16[1]

dest.fp16[1] := tmp[1] + src1.fp16[0] * src2.fp16[1]

ELSE IF *zeroing*:

dest.fp16[0] := 0

dest.fp16[1] := 0

DEST[127:32] := src1[127:32] // copy upper part of src1

DEST[MAXVL-1:128] := 0

Intel C/C++ Compiler Intrinsic Equivalent

VFCMADDCSH __m128h _mm_fcmadd_round_sch (__m128h a, __m128h b, __m128h c, const int rounding);

VFCMADDCSH __m128h _mm_mask_fcmadd_round_sch (__m128h a, __mmask8 k, __m128h b, __m128h c, const int rounding);

VFCMADDCSH __m128h _mm_mask3_fcmadd_round_sch (__m128h a, __m128h b, __m128h c, __mmask8 k, const int rounding);

VFCMADDCSH __m128h _mm_maskz_fcmadd_round_sch (__mmask8 k, __m128h a, __m128h b, __m128h c, const int rounding);

VFCMADDCSH __m128h _mm_fcmadd_sch (__m128h a, __m128h b, __m128h c);

VFCMADDCSH __m128h _mm_mask_fcmadd_sch (__m128h a, __mmask8 k, __m128h b, __m128h c);

VFCMADDCSH __m128h _mm_mask3_fcmadd_sch (__m128h a, __m128h b, __m128h c, __mmask8 k);

VFCMADDCSH __m128h _mm_maskz_fcmadd_sch (__mmask8 k, __m128h a, __m128h b, __m128h c);

VFMADDCSH __m128h _mm_fmadd_round_sch (__m128h a, __m128h b, __m128h c, const int rounding);

VFMADDCSH __m128h _mm_mask_fmadd_round_sch (__m128h a, __mmask8 k, __m128h b, __m128h c, const int rounding);

VFMADDCSH __m128h _mm_mask3_fmadd_round_sch (__m128h a, __m128h b, __m128h c, __mmask8 k, const int rounding);

VFMADDCSH __m128h _mm_maskz_fmadd_round_sch (__mmask8 k, __m128h a, __m128h b, __m128h c, const int rounding);

VFMADDCSH __m128h _mm_fmadd_sch (__m128h a, __m128h b, __m128h c);

VFMADDCSH __m128h _mm_mask_fmadd_sch (__m128h a, __mmask8 k, __m128h b, __m128h c);

VFMADDCSH __m128h _mm_mask3_fmadd_sch (__m128h a, __m128h b, __m128h c, __mmask8 k);

VFMADDCSH __m128h _mm_maskz_fmadd_sch (__mmask8 k, __m128h a, __m128h b, __m128h c);

SIMD Floating-Point Exceptions

Invalid, Underflow, Overflow, Precision, Denormal.

Other Exceptions

EVEX-encoded instructions, see Table 2-58, “Type E10 Class Exception Conditions.”

Additionally:

#UD

If (dest_reg == src1_reg) or (dest_reg == src2_reg).

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INSTRUCTION SET REFERENCE, V

VFCMULCPH/VFMULCPH-Complex Multiply FP16 Values

Opcode/

Op/

64/32

CPUID Feature

Description

Instruction

Bit Mode

Flag

Support

EVEX.128.F2.MAP6.W0 D6 /r

V/V

AVX512-FP16

Complex multiply a pair of FP16 values from

VFCMULCPH xmm1{k1}{z}, xmm2,

AVX512VL

xmm2 and complex conjugate of

xmm3/m128/m32bcst

xmm3/m128/m32bcst, and store the result in

xmm1 subject to writemask k1.

EVEX.256.F2.MAP6.W0 D6 /r

V/V

AVX512-FP16

Complex multiply a pair of FP16 values from

VFCMULCPH ymm1{k1}{z}, ymm2,

AVX512VL

ymm2 and complex conjugate of

ymm3/m256/m32bcst

ymm3/m256/m32bcst, and store the result in

ymm1 subject to writemask k1.

EVEX.512.F2.MAP6.W0 D6 /r

V/V

AVX512-FP16

Complex multiply a pair of FP16 values from

VFCMULCPH zmm1{k1}{z}, zmm2,

zmm2 and complex conjugate of

zmm3/m512/m32bcst {er}

zmm3/m512/m32bcst, and store the result in

zmm1 subject to writemask k1.

EVEX.128.F3.MAP6.W0 D6 /r

V/V

AVX512-FP16

Complex multiply a pair of FP16 values from

VFMULCPH xmm1{k1}{z}, xmm2,

AVX512VL

xmm2 and xmm3/m128/m32bcst, and store the

xmm3/m128/m32bcst

result in xmm1 subject to writemask k1.

EVEX.256.F3.MAP6.W0 D6 /r

V/V

AVX512-FP16

Complex multiply a pair of FP16 values from

VFMULCPH ymm1{k1}{z}, ymm2,

AVX512VL

ymm2 and ymm3/m256/m32bcst, and store the

ymm3/m256/m32bcst

result in ymm1 subject to writemask k1.

EVEX.512.F3.MAP6.W0 D6 /r

V/V

AVX512-FP16

Complex multiply a pair of FP16 values from

VFMULCPH zmm1{k1}{z}, zmm2,

zmm2 and zmm3/m512/m32bcst, and store the

zmm3/m512/m32bcst {er}

result in zmm1 subject to writemask k1.

Instruction Operand Encoding

Op/En

Tuple

Operand 1

Operand 2

Operand 3

Operand 4

Full

ModRM:reg (w)

VEX.vvvv (r)

ModRM:r/m (r)

N/A

Description

This instruction performs a complex multiply operation. There are normal and complex conjugate forms of the oper-

ation. The broadcasting and masking for this operation is done on 32-bit quantities representing a pair of FP16

values.

Rounding is performed at every FMA (fused multiply and add) boundary. Execution occurs as if all MXCSR excep-

tions are masked. MXCSR status bits are updated to reflect exceptional conditions.

Operation

VFCMULCPH dest{k1}, src1, src2 (AVX512)

VL = 128, 256 or 512

KL := VL/32

FOR i := 0 to KL-1:

IF k1[i] or *no writemask*:

IF broadcasting and src2 is memory:

tsrc2.fp16[2*i+0] := src2.fp16[0]

tsrc2.fp16[2*i+1] := src2.fp16[1]

ELSE:

tsrc2.fp16[2*i+0] := src2.fp16[2*i+0]

tsrc2.fp16[2*i+1] := src2.fp16[2*i+1]

FOR i := 0 to KL-1:

VFCMULCPH/VFMULCPH-Complex Multiply FP16 Values

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5-175

INSTRUCTION SET REFERENCE, V

IF k1[i] or *no writemask*:

tmp.fp16[2*i+0] := src1.fp16[2*i+0] * tsrc2.fp16[2*i+0]

tmp.fp16[2*i+1] := src1.fp16[2*i+1] * tsrc2.fp16[2*i+0]

FOR i := 0 to KL-1:

IF k1[i] or *no writemask*:

// conjugate version subtracts odd final term

dest.fp16[2*i] := tmp.fp16[2*i+0] +src1.fp16[2*i+1] * tsrc2.fp16[2*i+1]

dest.fp16[2*i+1] := tmp.fp16[2*i+1] - src1.fp16[2*i+0] * tsrc2.fp16[2*i+1]

ELSE IF *zeroing*:

dest.fp16[2*i+0] := 0

dest.fp16[2*i+1] := 0

DEST[MAXVL-1:VL] := 0

VFMULCPH dest{k1}, src1, src2 (AVX512)

VL = 128, 256 or 512

KL := VL/32

FOR i := 0 to KL-1:

IF k1[i] or *no writemask*:

IF broadcasting and src2 is memory:

tsrc2.fp16[2*i+0] := src2.fp16[0]

tsrc2.fp16[2*i+1] := src2.fp16[1]

ELSE:

tsrc2.fp16[2*i+0] := src2.fp16[2*i+0]

tsrc2.fp16[2*i+1] := src2.fp16[2*i+1]

FOR i := 0 to kl-1:

IF k1[i] or *no writemask*:

tmp.fp16[2*i+0] := src1.fp16[2*i+0] * tsrc2.fp16[2*i+0]

tmp.fp16[2*i+1] := src1.fp16[2*i+1] * tsrc2.fp16[2*i+0]

FOR i := 0 to KL-1:

IF k1[i] or *no writemask*:

// non-conjugate version subtracts last even term

dest.fp16[2*i+0] := tmp.fp16[2*i+0] - src1.fp16[2*i+1] * tsrc2.fp16[2*i+1]

dest.fp16[2*i+1] := tmp.fp16[2*i+1] + src1.fp16[2*i+0] * tsrc2.fp16[2*i+1]

ELSE IF *zeroing*:

dest.fp16[2*i+0] := 0

dest.fp16[2*i+1] := 0

DEST[MAXVL-1:VL] := 0

Intel C/C++ Compiler Intrinsic Equivalent

VFCMULCPH __m128h _mm_cmul_pch (__m128h a, __m128h b);

VFCMULCPH __m128h _mm_mask_cmul_pch (__m128h src, __mmask8 k, __m128h a, __m128h b);

VFCMULCPH __m128h _mm_maskz_cmul_pch (__mmask8 k, __m128h a, __m128h b);

VFCMULCPH __m256h _mm256_cmul_pch (__m256h a, __m256h b);

VFCMULCPH __m256h _mm256_mask_cmul_pch (__m256h src, __mmask8 k, __m256h a, __m256h b);

VFCMULCPH __m256h _mm256_maskz_cmul_pch (__mmask8 k, __m256h a, __m256h b);

VFCMULCPH __m512h _mm512_cmul_pch (__m512h a, __m512h b);

VFCMULCPH __m512h _mm512_mask_cmul_pch (__m512h src, __mmask16 k, __m512h a, __m512h b);

VFCMULCPH __m512h _mm512_maskz_cmul_pch (__mmask16 k, __m512h a, __m512h b);

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INSTRUCTION SET REFERENCE, V

VFCMULCPH __m512h _mm512_cmul_round_pch (__m512h a, __m512h b, const int rounding);

VFCMULCPH __m512h _mm512_mask_cmul_round_pch (__m512h src, __mmask16 k, __m512h a, __m512h b, const int rounding);

VFCMULCPH __m512h _mm512_maskz_cmul_round_pch (__mmask16 k, __m512h a, __m512h b, const int rounding);

VFCMULCPH __m128h _mm_fcmul_pch (__m128h a, __m128h b);

VFCMULCPH __m128h _mm_mask_fcmul_pch (__m128h src, __mmask8 k, __m128h a, __m128h b);

VFCMULCPH __m128h _mm_maskz_fcmul_pch (__mmask8 k, __m128h a, __m128h b);

VFCMULCPH __m256h _mm256_fcmul_pch (__m256h a, __m256h b);

VFCMULCPH __m256h _mm256_mask_fcmul_pch (__m256h src, __mmask8 k, __m256h a, __m256h b);

VFCMULCPH __m256h _mm256_maskz_fcmul_pch (__mmask8 k, __m256h a, __m256h b);

VFCMULCPH __m512h _mm512_fcmul_pch (__m512h a, __m512h b);

VFCMULCPH __m512h _mm512_mask_fcmul_pch (__m512h src, __mmask16 k, __m512h a, __m512h b);

VFCMULCPH __m512h _mm512_maskz_fcmul_pch (__mmask16 k, __m512h a, __m512h b);

VFCMULCPH __m512h _mm512_fcmul_round_pch (__m512h a, __m512h b, const int rounding);

VFCMULCPH __m512h _mm512_mask_fcmul_round_pch (__m512h src, __mmask16 k, __m512h a, __m512h b, const int rounding);

VFCMULCPH __m512h _mm512_maskz_fcmul_round_pch (__mmask16 k, __m512h a, __m512h b, const int rounding);

VFMULCPH __m128h _mm_fmul_pch (__m128h a, __m128h b);

VFMULCPH __m128h _mm_mask_fmul_pch (__m128h src, __mmask8 k, __m128h a, __m128h b);

VFMULCPH __m128h _mm_maskz_fmul_pch (__mmask8 k, __m128h a, __m128h b);

VFMULCPH __m256h _mm256_fmul_pch (__m256h a, __m256h b);

VFMULCPH __m256h _mm256_mask_fmul_pch (__m256h src, __mmask8 k, __m256h a, __m256h b);

VFMULCPH __m256h _mm256_maskz_fmul_pch (__mmask8 k, __m256h a, __m256h b);

VFMULCPH __m512h _mm512_fmul_pch (__m512h a, __m512h b);

VFMULCPH __m512h _mm512_mask_fmul_pch (__m512h src, __mmask16 k, __m512h a, __m512h b);

VFMULCPH __m512h _mm512_maskz_fmul_pch (__mmask16 k, __m512h a, __m512h b);

VFMULCPH __m512h _mm512_fmul_round_pch (__m512h a, __m512h b, const int rounding);

VFMULCPH __m512h _mm512_mask_fmul_round_pch (__m512h src, __mmask16 k, __m512h a, __m512h b, const int rounding);

VFMULCPH __m512h _mm512_maskz_fmul_round_pch (__mmask16 k, __m512h a, __m512h b, const int rounding);

VFMULCPH __m128h _mm_mask_mul_pch (__m128h src, __mmask8 k, __m128h a, __m128h b);

VFMULCPH __m128h _mm_maskz_mul_pch (__mmask8 k, __m128h a, __m128h b);

VFMULCPH __m128h _mm_mul_pch (__m128h a, __m128h b);

VFMULCPH __m256h _mm256_mask_mul_pch (__m256h src, __mmask8 k, __m256h a, __m256h b);

VFMULCPH __m256h _mm256_maskz_mul_pch (__mmask8 k, __m256h a, __m256h b);

VFMULCPH __m256h _mm256_mul_pch (__m256h a, __m256h b);

VFMULCPH __m512h _mm512_mask_mul_pch (__m512h src, __mmask16 k, __m512h a, __m512h b);

VFMULCPH __m512h _mm512_maskz_mul_pch (__mmask16 k, __m512h a, __m512h b);

VFMULCPH __m512h _mm512_mul_pch (__m512h a, __m512h b);

VFMULCPH __m512h _mm512_mask_mul_round_pch (__m512h src, __mmask16 k, __m512h a, __m512h b, const int rounding);

VFMULCPH __m512h _mm512_maskz_mul_round_pch (__mmask16 k, __m512h a, __m512h b, const int rounding);

VFMULCPH __m512h _mm512_mul_round_pch (__m512h a, __m512h b, const int rounding);

SIMD Floating-Point Exceptions

Invalid, Underflow, Overflow, Precision, Denormal.

Other Exceptions

EVEX-encoded instructions, see Table 2-49, “Type E4 Class Exception Conditions.”

Additionally:

#UD

If (dest_reg == src1_reg) or (dest_reg == src2_reg).

VFCMULCPH/VFMULCPH-Complex Multiply FP16 Values

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5-177

INSTRUCTION SET REFERENCE, V

VFCMULCSH/VFMULCSH-Complex Multiply Scalar FP16 Values

Opcode/

Op/

64/32

CPUID Feature

Description

Instruction

Bit Mode

Flag

Support

EVEX.LLIG.F2.MAP6.W0 D7 /r

V/V

AVX512-FP16

Complex multiply a pair of FP16 values from

VFCMULCSH xmm1{k1}{z}, xmm2,

xmm2 and complex conjugate of xmm3/m32, and

xmm3/m32 {er}

store the result in xmm1 subject to writemask k1.

Bits 127:32 of xmm2 are copied to

xmm1[127:32].

EVEX.LLIG.F3.MAP6.W0 D7 /r

V/V

AVX512-FP16

Complex multiply a pair of FP16 values from

VFMULCSH xmm1{k1}{z}, xmm2,

xmm2 and xmm3/m32, and store the result in

xmm3/m32 {er}

xmm1 subject to writemask k1. Bits 127:32 of

xmm2 are copied to xmm1[127:32].

Instruction Operand Encoding

Op/En

Tuple

Operand 1

Operand 2

Operand 3

Operand 4

Scalar

ModRM:reg (w)

VEX.vvvv (r)

ModRM:r/m (r)

N/A

Description

This instruction performs a complex multiply operation. There are normal and complex conjugate forms of the oper-

ation. The masking for this operation is done on 32-bit quantities representing a pair of FP16 values.

Bits 127:32 of the destination operand are copied from the corresponding bits of the first source operand. Bits

MAXVL-1:128 of the destination operand are zeroed. The low FP16 element of the destination is updated according

to the writemask.

Rounding is performed at every FMA (fused multiply and add) boundary. Execution occurs as if all MXCSR excep-

tions are masked. MXCSR status bits are updated to reflect exceptional conditions.

Operation

VFCMULCSH dest{k1}, src1, src2 (AVX512)

KL := VL / 32

IF k1[0] or *no writemask*:

tmp.fp16[0] := src1.fp16[0] * src2.fp16[0]

tmp.fp16[1] := src1.fp16[1] * src2.fp16[0]

// conjugate version subtracts odd final term

dest.fp16[0] := tmp.fp16[0] + src1.fp16[1] * src2.fp16[1]

dest.fp16[1] := tmp.fp16[1] - src1.fp16[0] * src2.fp16[1]

ELSE IF *zeroing*:

dest.fp16[0] := 0

dest.fp16[1] := 0

DEST[127:32] := src1[127:32] // copy upper part of src1

DEST[MAXVL-1:128] := 0

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INSTRUCTION SET REFERENCE, V

VFMULCSH dest{k1}, src1, src2 (AVX512)

KL := VL / 32

IF k1[0] or *no writemask*:

// non-conjugate version subtracts last even term

tmp.fp16[0] := src1.fp16[0] * src2.fp16[0]

tmp.fp16[1] := src1.fp16[1] * src2.fp16[0]

dest.fp16[0] := tmp.fp16[0] - src1.fp16[1] * src2.fp16[1]

dest.fp16[1] := tmp.fp16[1] + src1.fp16[0] * src2.fp16[1]

ELSE IF *zeroing*:

dest.fp16[0] := 0

dest.fp16[1] := 0

DEST[127:32] := src1[127:32] // copy upper part of src1

DEST[MAXVL-1:128] := 0

Intel C/C++ Compiler Intrinsic Equivalent

VFCMULCSH __m128h _mm_cmul_round_sch (__m128h a, __m128h b, const int rounding);

VFCMULCSH __m128h _mm_mask_cmul_round_sch (__m128h src, __mmask8 k, __m128h a, __m128h b, const int rounding);

VFCMULCSH __m128h _mm_maskz_cmul_round_sch (__mmask8 k, __m128h a, __m128h b, const int rounding);

VFCMULCSH __m128h _mm_cmul_sch (__m128h a, __m128h b);

VFCMULCSH __m128h _mm_mask_cmul_sch (__m128h src, __mmask8 k, __m128h a, __m128h b);

VFCMULCSH __m128h _mm_maskz_cmul_sch (__mmask8 k, __m128h a, __m128h b);

VFCMULCSH __m128h _mm_fcmul_round_sch (__m128h a, __m128h b, const int rounding);

VFCMULCSH __m128h _mm_mask_fcmul_round_sch (__m128h src, __mmask8 k, __m128h a, __m128h b, const int rounding);

VFCMULCSH __m128h _mm_maskz_fcmul_round_sch (__mmask8 k, __m128h a, __m128h b, const int rounding);

VFCMULCSH __m128h _mm_fcmul_sch (__m128h a, __m128h b);

VFCMULCSH __m128h _mm_mask_fcmul_sch (__m128h src, __mmask8 k, __m128h a, __m128h b);

VFCMULCSH __m128h _mm_maskz_fcmul_sch (__mmask8 k, __m128h a, __m128h b);

VFMULCSH __m128h _mm_fmul_round_sch (__m128h a, __m128h b, const int rounding);

VFMULCSH __m128h _mm_mask_fmul_round_sch (__m128h src, __mmask8 k, __m128h a, __m128h b, const int rounding);

VFMULCSH __m128h _mm_maskz_fmul_round_sch (__mmask8 k, __m128h a, __m128h b, const int rounding);

VFMULCSH __m128h _mm_fmul_sch (__m128h a, __m128h b);

VFMULCSH __m128h _mm_mask_fmul_sch (__m128h src, __mmask8 k, __m128h a, __m128h b);

VFMULCSH __m128h _mm_maskz_fmul_sch (__mmask8 k, __m128h a, __m128h b);

VFMULCSH __m128h _mm_mask_mul_round_sch (__m128h src, __mmask8 k, __m128h a, __m128h b, const int rounding);

VFMULCSH __m128h _mm_maskz_mul_round_sch (__mmask8 k, __m128h a, __m128h b, const int rounding);

VFMULCSH __m128h _mm_mul_round_sch (__m128h a, __m128h b, const int rounding);

VFMULCSH __m128h _mm_mask_mul_sch (__m128h src, __mmask8 k, __m128h a, __m128h b);

VFMULCSH __m128h _mm_maskz_mul_sch (__mmask8 k, __m128h a, __m128h b);

VFMULCSH __m128h _mm_mul_sch (__m128h a, __m128h b);

SIMD Floating-Point Exceptions

Invalid, Underflow, Overflow, Precision, Denormal.

Other Exceptions

EVEX-encoded instructions, see Table 2-58, “Type E10 Class Exception Conditions.”

Additionally:

#UD

If (dest_reg == src1_reg) or (dest_reg == src2_reg).

VFCMULCSH/VFMULCSH-Complex Multiply Scalar FP16 Values

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5-179

INSTRUCTION SET REFERENCE, V

VGETMANTSS-Extract Float32 Vector of Normalized Mantissa From Float32 Scalar

Opcode/

Op/

64/32

CPUID

Description

Instruction

Bit Mode

Feature

Support

Flag

EVEX.LLIG.66.0F3A.W0 27 /r ib

V/V

AVX512F

Extract the normalized mantissa from the low float32

VGETMANTSS xmm1 {k1}{z}, xmm2,

element of xmm3/m32 using imm8 for sign control and

xmm3/m32{sae}, imm8

mantissa interval normalization, store the mantissa to

xmm1 under the writemask k1 and merge with the

other elements of xmm2.

Instruction Operand Encoding

Op/En

Tuple Type

Operand 1

Operand 2

Operand 3

Operand 4

Tuple1 Scalar

ModRM:reg (w)

EVEX.vvvv (r)

ModRM:r/m (r)

N/A

Description

Convert the single-precision floating values in the low doubleword element of the second source operand (the third

operand) to single-precision floating-point value with the mantissa normalization and sign control specified by the

imm8 byte, see Figure 5-15. The converted result is written to the low doubleword element of the destination

operand (the first operand) using writemask k1. Bits (127:32) of the XMM register destination are copied from

corresponding bits in the first source operand. The normalized mantissa is specified by interv (imm8[1:0]) and the

sign control (sc) is specified by bits 3:2 of the immediate byte.

The conversion operation is:

GetMant(x) = ±2^k|x.significand|

where:

1 <= |x.significand| < 2

Unbiased exponent k can be either 0 or -1, depending on the interval range defined by interv, the range of the

significand and whether the exponent of the source is even or odd. The sign of the final result is determined by sc

and the source sign. The encoded value of imm8[1:0] and sign control are shown in Figure 5-15.

The converted single-precision floating-point result is encoded according to the sign control, the unbiased expo-

nent k (adding bias) and a mantissa normalized to the range specified by interv.

The GetMant() function follows Table 5-8 when dealing with floating-point special numbers.

If writemasking is used, the low doubleword element of the destination operand is conditionally updated depending

on the value of writemask register k1. If writemasking is not used, the low doubleword element of the destination

operand is unconditionally updated.

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VGETMANTSS-Extract Float32 Vector of Normalized Mantissa From Float32 Scalar

INSTRUCTION SET REFERENCE, V

Operation

// getmant_fp32(src, sign_control, normalization_interval) is defined in the operation section of VGETMANTPS

VGETMANTSS (EVEX encoded version)

SignCtrl[1:0] := IMM8[3:2];

Interv[1:0] := IMM8[1:0];

IF k1[0] OR *no writemask*

THEN DEST[31:0] :=

getmant_fp32(src, sign_control, normalization_interval)

ELSE

IF *merging-masking*

; merging-masking

THEN *DEST[31:0] remains unchanged*

ELSE

; zeroing-masking

DEST[31:0] := 0

FI;

DEST[127:32] := SRC1[127:32]

DEST[MAXVL-1:128] := 0

Intel C/C++ Compiler Intrinsic Equivalent

VGETMANTSS __m128 _mm_getmant_ss( __m128 a, __m128 b, enum intv, enum sgn);

VGETMANTSS __m128 _mm_mask_getmant_ss(__m128 s, __mmask8 k, __m128 a, __m128 b, enum intv, enum sgn);

VGETMANTSS __m128 _mm_maskz_getmant_ss( __mmask8 k, __m128 a, __m128 b, enum intv, enum sgn);

VGETMANTSS __m128 _mm_getmant_round_ss( __m128 a, __m128 b, enum intv, enum sgn, int r);

VGETMANTSS __m128 _mm_mask_getmant_round_ss(__m128 s, __mmask8 k, __m128 a, __m128 b, enum intv, enum sgn, int r);

VGETMANTSS __m128 _mm_maskz_getmant_round_ss( __mmask8 k, __m128 a, __m128 b, enum intv, enum sgn, int r);

SIMD Floating-Point Exceptions

Denormal, Invalid

Other Exceptions

See Table 2-47, “Type E3 Class Exception Conditions.”

VGETMANTSS-Extract Float32 Vector of Normalized Mantissa From Float32 Scalar

Vol. 2C

5-385

INSTRUCTION SET REFERENCE, V

VPBLENDD-Blend Packed Dwords

Opcode/

Op/

64/32

CPUID

Description

Instruction

-bit

Feature

Mode

Flag

VEX.128.66.0F3A.W0 02 /r ib

RVMI

V/V

AVX2

Select dwords from xmm2 and xmm3/m128 from

VPBLENDD xmm1, xmm2, xmm3/m128, imm8

mask specified in imm8 and store the values into

xmm1.

VEX.256.66.0F3A.W0 02 /r ib

RVMI

V/V

AVX2

Select dwords from ymm2 and ymm3/m256 from

VPBLENDD ymm1, ymm2, ymm3/m256, imm8

mask specified in imm8 and store the values into

ymm1.

Instruction Operand Encoding

Op/En

Operand 1

Operand 2

Operand 3

Operand 4

RVMI

ModRM:reg (w)

VEX.vvvv (r)

ModRM:r/m (r)

imm8

Description

Dword elements from the source operand (second operand) are conditionally written to the destination operand

(first operand) depending on bits in the immediate operand (third operand). The immediate bits (bits 7:0) form a

mask that determines whether the corresponding dword in the destination is copied from the source. If a bit in the

mask, corresponding to a dword, is “1", then the dword is copied, else the dword is unchanged.

VEX.128 encoded version: The second source operand can be an XMM register or a 128-bit memory location. The

first source and destination operands are XMM registers. Bits (MAXVL-1:128) of the corresponding YMM register

are zeroed.

VEX.256 encoded version: The first source operand is a YMM register. The second source operand is a YMM register

or a 256-bit memory location. The destination operand is a YMM register.

Operation

VPBLENDD (VEX.256 encoded version)

IF (imm8[0] == 1) THEN DEST[31:0] := SRC2[31:0]

ELSE DEST[31:0] := SRC1[31:0]

IF (imm8[1] == 1) THEN DEST[63:32] := SRC2[63:32]

ELSE DEST[63:32] := SRC1[63:32]

IF (imm8[2] == 1) THEN DEST[95:64] := SRC2[95:64]

ELSE DEST[95:64] := SRC1[95:64]

IF (imm8[3] == 1) THEN DEST[127:96] := SRC2[127:96]

ELSE DEST[127:96] := SRC1[127:96]

IF (imm8[4] == 1) THEN DEST[159:128] := SRC2[159:128]

ELSE DEST[159:128] := SRC1[159:128]

IF (imm8[5] == 1) THEN DEST[191:160] := SRC2[191:160]

ELSE DEST[191:160] := SRC1[191:160]

IF (imm8[6] == 1) THEN DEST[223:192] := SRC2[223:192]

ELSE DEST[223:192] := SRC1[223:192]

IF (imm8[7] == 1) THEN DEST[255:224] := SRC2[255:224]

ELSE DEST[255:224] := SRC1[255:224]

5-412

Vol. 2C

VPBLENDD-Blend Packed Dwords

CHAPTER 1

ABOUT THIS MANUAL

The Intel^®64 and IA-32 Architectures Software Developer’s Manual, Volume 3A: System Programming Guide, Part

1 (order number 253668), the Intel^® 64 and IA-32 Architectures Software Developer’s Manual, Volume 3B: System

Programming Guide, Part 2 (order number 253669), the Intel^® 64 and IA-32 Architectures Software Developer’s

Manual, Volume 3C: System Programming Guide, Part 3 (order number 326019), and the Intel^® 64 and IA-32

Architectures Software Developer’s Manual, Volume 3D:System Programming Guide, Part 4 (order number

332831) are part of a set that describes the architecture and programming environment of Intel 64 and IA-32

Architecture processors. The other volumes in this set are:

• Intel^® 64 and IA-32 Architectures Software Developer’s Manual, Volume 1: Basic Architecture (order number

253665).

• Intel^® 64 and IA-32 Architectures Software Developer’s Manual, Volumes 2A, 2B, 2C, & 2D: Instruction Set

Reference (order numbers 253666, 253667, 326018, and 334569).

• The Intel® 64 and IA-32 Architectures Software Developer’s Manual, Volume 4: Model-Specific Registers

(order number 335592).

The Intel^® 64 and IA-32 Architectures Software Developer’s Manual, Volume 1, describes the basic architecture

and programming environment of Intel 64 and IA-32 processors. The Intel^® 64 and IA-32 Architectures Software

Developer’s Manual, Volumes 2A, 2B, 2C, & 2D, describe the instruction set of the processor and the opcode struc-

ture. These volumes apply to application programmers and to programmers who write operating systems or exec-

utives. The Intel^® 64 and IA-32 Architectures Software Developer’s Manual, Volumes 3A, 3B, 3C, & 3D, describe

the operating-system support environment of Intel 64 and IA-32 processors. These volumes target operating-

system and BIOS designers. In addition, Intel^® 64 and IA-32 Architectures Software Developer’s Manual, Volume

3B, and Intel^® 64 and IA-32 Architectures Software Developer’s Manual, Volume 3C, address the programming

environment for classes of software that host operating systems. The Intel^® 64 and IA-32 Architectures Software

Developer’s Manual, Volume 4, describes the model-specific registers of Intel 64 and IA-32 processors.

1.1

INTEL® 64 AND IA-32 PROCESSORS COVERED IN THIS MANUAL

This manual set includes information pertaining primarily to the most recent Intel 64 and IA-32 processors, which

include:

• Pentium^® processors

• P6 family processors

• Pentium^® 4 processors

• Pentium^® M processors

• Intel^® Xeon^® processors

• Pentium^® D processors

• Pentium^® processor Extreme Editions

•

64-bit Intel^® Xeon^® processors

• Intel^® Core™ Duo processor

• Intel^® Core™ Solo processor

• Dual-Core Intel^® Xeon^® processor LV

• Intel^® Core™ 2 Duo processor

• Intel^® Core™ 2 Quad processor Q6000 series

• Intel^® Xeon^® processor 3000, 3200 series

• Intel^® Xeon^® processor 5000 series

• Intel^® Xeon^® processor 5100, 5300 series

Vol. 3A

1-1

ABOUT THIS MANUAL

•

Intel^® Core™ 2 Extreme processor X7000 and X6800 series

•

Intel^® Core™ 2 Extreme QX6000 series

•

Intel^® Xeon^® processor 7100 series

•

Intel^® Pentium^® Dual-Core processor

•

Intel^® Xeon^® processor 7200, 7300 series

•

Intel^® Core™ 2 Extreme QX9000 series

•

Intel^® Xeon^® processor 5200, 5400, 7400 series

•

Intel^® Core™ 2 Extreme processor QX9000 and X9000 series

•

Intel^® Core™ 2 Quad processor Q9000 series

•

Intel^® Core™ 2 Duo processor E8000, T9000 series

•

Intel Atom^® processors 200, 300, D400, D500, D2000, N200, N400, N2000, E2000, Z500, Z600, Z2000,

C1000 series are built from 45 nm and 32 nm processes.

•

Intel^® Core™ i7 processor

•

Intel^® Core™ i5 processor

•

Intel^® Xeon^® processor E7-8800/4800/2800 product families

•

Intel^® Core™ i7-3930K processor

•

2nd generation Intel^® Core™ i7-2xxx, Intel^® Core™ i5-2xxx, Intel^® Core™ i3-2xxx processor series

•

Intel^® Xeon^® processor E3-1200 product family

•

Intel^® Xeon^® processor E5-2400/1400 product family

•

Intel^® Xeon^® processor E5-4600/2600/1600 product family

•

3rd generation Intel^® Core™ processors

•

Intel^® Xeon^® processor E3-1200 v2 product family

•

Intel^® Xeon^® processor E5-2400/1400 v2 product families

•

Intel^® Xeon^® processor E5-4600/2600/1600 v2 product families

•

Intel^® Xeon^® processor E7-8800/4800/2800 v2 product families

•

4th generation Intel^® Core™ processors

•

The Intel^® Core™ M processor family

•

Intel^® Core™ i7-59xx Processor Extreme Edition

•

Intel^® Core™ i7-49xx Processor Extreme Edition

•

Intel^® Xeon^® processor E3-1200 v3 product family

•

Intel^® Xeon^® processor E5-2600/1600 v3 product families

•

5th generation Intel^® Core™ processors

•

Intel^® Xeon^® processor D-1500 product family

•

Intel^® Xeon^® processor E5 v4 family

•

Intel Atom^® processor X7-Z8000 and X5-Z8000 series

•

Intel Atom^® processor Z3400 series

•

Intel Atom^® processor Z3500 series

•

6th generation Intel^® Core™ processors

•

Intel^® Xeon^® processor E3-1500m v5 product family

•

7th generation Intel^® Core™ processors

•

Intel^® Xeon Phi™ Processor 3200, 5200, 7200 Series

•

Intel^® Xeon^® Scalable Processor Family

•

8th generation Intel^® Core™ processors

•

Intel^® Xeon Phi™ Processor 7215, 7285, 7295 Series

1-2

Vol. 3A

ABOUT THIS MANUAL

• Intel^® Xeon^® E processors

• 9th generation Intel^® Core™ processors

• 2nd generation Intel^® Xeon^® Scalable Processor Family

•

10th generation Intel^® Core™ processors

•

11th generation Intel^® Core™ processors

• 3rd generation Intel^® Xeon^® Scalable Processor Family

•

12th generation Intel^® Core™ processors

•

13th generation Intel^® Core™ processors

• 4th generation Intel^® Xeon^® Scalable Processor Family

• 5th generation Intel^® Xeon^® Scalable Processor Family

• Intel^® Core™ Ultra 7 processors

P6 family processors are IA-32 processors based on the P6 family microarchitecture. This includes the Pentium^®

Pro, Pentium^® II, Pentium^® III, and Pentium^® III Xeon^® processors.

The Pentium^® 4, Pentium^® D, and Pentium^® processor Extreme Editions are based on the Intel NetBurst^®micro-

architecture. Most early Intel^® Xeon^®processors are based on the Intel NetBurst^®microarchitecture. Intel Xeon

processor 5000, 7100 series are based on the Intel NetBurst^®microarchitecture.

The Intel^® Core™ Duo, Intel^® Core™ Solo and dual-core Intel^®Xeon^® processor LV are based on an improved

Pentium^® M processor microarchitecture.

The Intel^® Xeon^® processor 3000, 3200, 5100, 5300, 7200, and 7300 series, Intel^® Pentium^® dual-core, Intel^®

Core™ 2 Duo, Intel^® Core™ 2 Quad, and Intel^® Core™ 2 Extreme processors are based on Intel^®Core™ microar-

chitecture.

The Intel^® Xeon^® processor 5200, 5400, 7400 series, Intel^® Core™ 2 Quad processor Q9000 series, and Intel^®

Core™ 2 Extreme processors QX9000, X9000 series, Intel^® Core™ 2 processor E8000 series are based on

Enhanced Intel^®Core™ microarchitecture.

The Intel Atom^® processors 200, 300, D400, D500, D2000, N200, N400, N2000, E2000, Z500, Z600, Z2000,

C1000 series are based on the Intel Atom^® microarchitecture and supports Intel 64 architecture.

P6 family, Pentium^® M, Intel^® Core™ Solo, Intel^® Core™ Duo processors, dual-core Intel^®Xeon^® processor LV,

and early generations of Pentium 4 and Intel Xeon processors support IA-32 architecture. The Intel^® Atom^TM

processor Z5xx series support IA-32 architecture.

The Intel^® Xeon^® processor 3000, 3200, 5000, 5100, 5200, 5300, 5400, 7100, 7200, 7300, 7400 series, Intel^®

Core™ 2 Duo, Intel^® Core™ 2 Extreme, Intel^® Core™ 2 Quad processors, Pentium^® D processors, Pentium^® Dual-

Core processor, newer generations of Pentium 4 and Intel Xeon processor family support Intel^® 64 architecture.

The Intel^® Core™ i7 processor and Intel^® Xeon^® processor 3400, 5500, 7500 series are based on 45 nm Nehalem

microarchitecture. Westmere microarchitecture is a 32 nm version of the Nehalem microarchitecture. Intel^®

Xeon^® processor 5600 series, Intel Xeon processor E7 and various Intel Core i7, i5, i3 processors are based on the

Westmere microarchitecture. These processors support Intel 64 architecture.

The Intel^® Xeon^® processor E5 family, Intel^® Xeon^® processor E3-1200 family, Intel^® Xeon^® processor E7-

8800/4800/2800 product families, Intel^® Core™ i7-3930K processor, and 2nd generation Intel^® Core™ i7-2xxx,

Intel^® Core^TM i5-2xxx, Intel^® Core™ i3-2xxx processor series are based on the Sandy Bridge microarchitecture and

support Intel 64 architecture.

The Intel^® Xeon^® processor E7-8800/4800/2800 v2 product families, Intel^® Xeon^® processor E3-1200 v2 product

family and 3rd generation Intel^® Core™ processors are based on the Ivy Bridge microarchitecture and support

Intel 64 architecture.

The Intel^® Xeon^® processor E5-4600/2600/1600 v2 product families, Intel^® Xeon^® processor E5-2400/1400 v2

product families and Intel^® Core™ i7-49xx Processor Extreme Edition are based on the Ivy Bridge-E microarchitec-

ture and support Intel 64 architecture.

The Intel^® Xeon^® processor E3-1200 v3 product family and 4th Generation Intel^® Core™ processors are based on

the Haswell microarchitecture and support Intel 64 architecture.

Vol. 3A

1-3

ABOUT THIS MANUAL

The Intel^® Xeon^® processor E5-2600/1600 v3 product families and the Intel^® Core™ i7-59xx Processor Extreme

Edition are based on the Haswell-E microarchitecture and support Intel 64 architecture.

The Intel Atom^® processor Z8000 series is based on the Airmont microarchitecture.

The Intel Atom^® processor Z3400 series and the Intel Atom^® processor Z3500 series are based on the Silvermont

microarchitecture.

The Intel^® Core™ M processor family, 5th generation Intel^® Core™ processors, Intel^® Xeon^® processor D-1500

product family and the Intel^® Xeon^® processor E5 v4 family are based on the Broadwell microarchitecture and

support Intel 64 architecture.

The Intel^® Xeon^® Scalable Processor Family, Intel^® Xeon^® processor E3-1500m v5 product family and 6th gener-

ation Intel^® Core™ processors are based on the Skylake microarchitecture and support Intel 64 architecture.

The 7th generation Intel^® Core™ processors are based on the Kaby Lake microarchitecture and support Intel 64

architecture.

The Intel Atom^® processor C series, the Intel Atom^® processor X series, the Intel^® Pentium^® processor J series,

the Intel^® Celeron^® processor J series, and the Intel^® Celeron^® processor N series are based on the Goldmont

microarchitecture.

The Intel^® Xeon Phi™ Processor 3200, 5200, 7200 Series is based on the Knights Landing microarchitecture and

supports Intel 64 architecture.

The Intel^® Pentium^® Silver processor series, the Intel^® Celeron^® processor J series, and the Intel^® Celeron^®

processor N series are based on the Goldmont Plus microarchitecture.

The 8th generation Intel^® Core™ processors, 9th generation Intel^® Core™ processors, and Intel^® Xeon^® E proces-

sors are based on the Coffee Lake microarchitecture and support Intel 64 architecture.

The Intel^® Xeon Phi™ Processor 7215, 7285, 7295 Series is based on the Knights Mill microarchitecture and

supports Intel 64 architecture.

The 2nd generation Intel^® Xeon^® Scalable Processor Family is based on the Cascade Lake product and supports

Intel 64 architecture.

Some 10th generation Intel^® Core™ processors are based on the Ice Lake microarchitecture, and some are based

on the Comet Lake microarchitecture; both support Intel 64 architecture.

Some 11th generation Intel^® Core™ processors are based on the Tiger Lake microarchitecture, and some are

based on the Rocket Lake microarchitecture; both support Intel 64 architecture.

Some 3rd generation Intel^® Xeon^® Scalable Processor Family processors are based on the Cooper Lake product,

and some are based on the Ice Lake microarchitecture; both support Intel 64 architecture.

The 12th generation Intel^® Core™ processors supporting Alder Lake performance hybrid architecture support Intel

64 architecture.

The 13th generation Intel^® Core™ processors are based on the Raptor Lake performance hybrid architecture and

support Intel 64 architecture.

The 4th generation Intel^® Xeon^® Scalable Processor Family is based on Sapphire Rapids microarchitecture and

supports Intel 64 architecture.

The 5th generation Intel^® Xeon^® Scalable Processor Family is based on Emerald Rapids microarchitecture and

supports Intel 64 architecture.

The Intel^® Core™ Ultra 7 processor is based on Meteor Lake hybrid architecture and supports Intel 64 architecture.

IA-32 architecture is the instruction set architecture and programming environment for Intel's 32-bit microproces-

sors. Intel^®64 architecture is the instruction set architecture and programming environment which is the superset

of Intel’s 32-bit and 64-bit architectures. It is compatible with the IA-32 architecture.

1.2

OVERVIEW OF THE SYSTEM PROGRAMMING GUIDE

A description of this manual’s content follows¹:

1-4

Vol. 3A

ABOUT THIS MANUAL

Chapter 1 - About This Manual. Gives an overview of all volumes of the Intel^® 64 and IA-32 Architectures Soft-

ware Developer’s Manual. It also describes the notational conventions in these manuals and lists related Intel

manuals and documentation of interest to programmers and hardware designers.

Chapter 2 - System Architecture Overview. Describes the modes of operation used by Intel 64 and IA-32

processors and the mechanisms provided by the architectures to support operating systems and executives,

including the system-oriented registers and data structures and the system-oriented instructions. The steps neces-

sary for switching between real-address and protected modes are also identified.

Chapter 3 - Protected-Mode Memory Management. Describes the data structures, registers, and instructions

that support segmentation and paging. The chapter explains how they can be used to implement a “flat” (unseg-

mented) memory model or a segmented memory model.

Chapter 4 - Paging. Describes the paging modes supported by Intel 64 and IA-32 processors.

Chapter 5 - Protection. Describes the support for page and segment protection provided in the Intel 64 and IA-

32 architectures. This chapter also explains the implementation of privilege rules, stack switching, pointer valida-

tion, user mode, and supervisor mode.

Chapter 6 - Interrupt and Exception Handling. Describes the basic interrupt mechanisms defined in the Intel

64 and IA-32 architectures, shows how interrupts and exceptions relate to protection, and describes how the archi-

tecture handles each exception type. Reference information for each exception is given in this chapter. Includes

programming the LINT0 and LINT1 inputs and gives an example of how to program the LINT0 and LINT1 pins for

specific interrupt vectors.

Chapter 7 - User Interrupts. Describes user interrupts supported by Intel 64 and IA-32 processors.

Chapter 8 - Task Management. Describes mechanisms the Intel 64 and IA-32 architectures provide to support

multitasking and inter-task protection.

Chapter 9 - Multiple-Processor Management. Describes the instructions and flags that support multiple

processors with shared memory, memory ordering, and Intel^® Hyper-Threading Technology. Includes MP initializa-

tion for P6 family processors and gives an example of how to use the MP protocol to boot P6 family processors in

an MP system.

Chapter 10 - Processor Management and Initialization. Defines the state of an Intel 64 or IA-32 processor

after reset initialization. This chapter also explains how to set up an Intel 64 or IA-32 processor for real-address

mode operation and protected- mode operation, and how to switch between modes.

Chapter 11 - Advanced Programmable Interrupt Controller (APIC). Describes the programming interface

to the local APIC and gives an overview of the interface between the local APIC and the I/O APIC. Includes APIC bus

message formats and describes the message formats for messages transmitted on the APIC bus for P6 family and

Pentium processors.

Chapter 12 - Memory Cache Control. Describes the general concept of caching and the caching mechanisms

supported by the Intel 64 or IA-32 architectures. This chapter also describes the memory type range registers

(MTRRs) and how they can be used to map memory types of physical memory. Information on using the new cache

control and memory streaming instructions introduced with the Pentium III, Pentium 4, and Intel Xeon processors

is also given.

Chapter 13 - Intel^® MMX™ Technology System Programming. Describes those aspects of the Intel^® MMX™

technology that must be handled and considered at the system programming level, including: task switching,

exception handling, and compatibility with existing system environments.

Chapter 14 - System Programming For Instruction Set Extensions And Processor Extended States.

Describes the operating system requirements to support SSE/SSE2/SSE3/SSSE3/SSE4 extensions, including task

switching, exception handling, and compatibility with existing system environments. The latter part of this chapter

describes the extensible framework of operating system requirements to support processor extended states.

Processor extended state may be required by instruction set extensions beyond those of

SSE/SSE2/SSE3/SSSE3/SSE4 extensions.

Chapter 15 - Power and Thermal Management. Describes facilities of Intel 64 and IA-32 architecture used for

power management and thermal monitoring.

1. Model-Specific Registers have been moved out of this volume and into a separate volume: Intel^® 64 and IA-32 Architectures Soft-

ware Developer’s Manual, Volume 4.

Vol. 3A

1-5

ABOUT THIS MANUAL

Chapter 16 - Machine-Check Architecture. Describes the machine-check architecture and machine-check

exception mechanism found in the Pentium 4, Intel Xeon, and P6 family processors. Additionally, a signaling mech-

anism for software to respond to hardware corrected machine check error is covered.

Chapter 17 - Interpreting Machine-Check Error Codes. Gives an example of how to interpret the error codes

for a machine-check error that occurred on a P6 family processor.

Chapter 18 - Debug, Branch Profile, TSC, and Resource Monitoring Features. Describes the debugging

registers and other debug mechanism provided in Intel 64 or IA-32 processors. This chapter also describes the

time-stamp counter.

Chapter 19 - Last Branch Records. Describes the Last Branch Records (architectural feature).

Chapter 20 - Performance Monitoring. Describes the Intel 64 and IA-32 architectures’ facilities for monitoring

performance.

Chapter 21 - 8086 Emulation. Describes the real-address and virtual-8086 modes of the IA-32 architecture.

Chapter 22 - Mixing 16-Bit and 32-Bit Code. Describes how to mix 16-bit and 32-bit code modules within the

same program or task.

Chapter 23 - IA-32 Architecture Compatibility. Describes architectural compatibility among IA-32 proces-

sors.

Chapter 24 - Introduction to Virtual Machine Extensions. Describes the basic elements of virtual machine

architecture and the virtual machine extensions for Intel 64 and IA-32 Architectures.

Chapter 25 - Virtual Machine Control Structures. Describes components that manage VMX operation. These

include the working-VMCS pointer and the controlling-VMCS pointer.

Chapter 26 - VMX Non-Root Operation. Describes the operation of a VMX non-root operation. Processor oper-

ation in VMX non-root mode can be restricted programmatically such that certain operations, events or conditions

can cause the processor to transfer control from the guest (running in VMX non-root mode) to the monitor software

(running in VMX root mode).

Chapter 27 - VM Entries. Describes VM entries. VM entry transitions the processor from the VMM running in VMX

root-mode to a VM running in VMX non-root mode. VM-Entry is performed by the execution of VMLAUNCH or VMRE-

SUME instructions.

Chapter 28 - VM Exits. Describes VM exits. Certain events, operations or situations while the processor is in VMX

non-root operation may cause VM-exit transitions. In addition, VM exits can also occur on failed VM entries.

Chapter 29 - VMX Support for Address Translation. Describes virtual-machine extensions that support

address translation and the virtualization of physical memory.

Chapter 30 - APIC Virtualization and Virtual Interrupts. Describes the VMCS including controls that enable

the virtualization of interrupts and the Advanced Programmable Interrupt Controller (APIC).

Chapter 31 - VMX Instruction Reference. Describes the virtual-machine extensions (VMX). VMX is intended

for a system executive to support virtualization of processor hardware and a system software layer acting as a host

to multiple guest software environments.

Chapter 32 - System Management Mode. Describes Intel 64 and IA-32 architectures’ system management

mode (SMM) facilities.

Chapter 33 - Intel^® Processor Trace. Describes details of Intel^® Processor Trace.

Chapter 34 - Introduction to Intel^® Software Guard Extensions. Provides an overview of the Intel^® Soft-

ware Guard Extensions (Intel^® SGX) set of instructions.

Chapter 35 - Enclave Access Control and Data Structures. Describes Enclave Access Control procedures and

defines various Intel SGX data structures.

Chapter 36 - Enclave Operation. Describes enclave creation and initialization, adding pages and measuring an

enclave, and enclave entry and exit.

Chapter 37 - Enclave Exiting Events. Describes enclave-exiting events (EEE) and asynchronous enclave exit

(AEX).

Chapter 38 - SGX Instruction References. Describes the supervisor and user level instructions provided by

Intel SGX.

1-6

Vol. 3A

ABOUT THIS MANUAL

Chapter 39 - Intel^® SGX Interactions with IA32 and Intel^® 64 Architecture. Describes the Intel SGX

collection of enclave instructions for creating protected execution environments on processors supporting IA32 and

Intel 64 architectures.

Chapter 40 - Enclave Code Debug and Profiling. Describes enclave code debug processes and options.

Appendix A - VMX Capability Reporting Facility. Describes the VMX capability MSRs. Support for specific VMX

features is determined by reading capability MSRs.

Appendix B - Field Encoding in VMCS. Enumerates all fields in the VMCS and their encodings. Fields are

grouped by width (16-bit, 32-bit, etc.) and type (guest-state, host-state, etc.).

Appendix C - VM Basic Exit Reasons. Describes the 32-bit fields that encode reasons for a VM exit. Examples

of exit reasons include, but are not limited to: software interrupts, processor exceptions, software traps, NMIs,

external interrupts, and triple faults.

1.3

NOTATIONAL CONVENTIONS

This manual uses specific notation for data-structure formats, for symbolic representation of instructions, and for

hexadecimal and binary numbers. A review of this notation makes the manual easier to read.

1.3.1

Bit and Byte Order

In illustrations of data structures in memory, smaller addresses appear toward the bottom of the figure; addresses

increase toward the top. Bit positions are numbered from right to left. The numerical value of a set bit is equal to

two raised to the power of the bit position. Intel 64 and IA-32 processors are “little endian” machines; this means

the bytes of a word are numbered starting from the least significant byte. Figure 1-1 illustrates these conventions.

1.3.2

Reserved Bits and Software Compatibility

In many register and memory layout descriptions, certain bits are marked as reserved. When bits are marked as

reserved, it is essential for compatibility with future processors that software treat these bits as having a future,

though unknown, effect. The behavior of reserved bits should be regarded as not only undefined, but unpredict-

able. Software should follow these guidelines in dealing with reserved bits:

• Do not depend on the states of any reserved bits when testing the values of registers which contain such bits.

Mask out the reserved bits before testing.

• Do not depend on the states of any reserved bits when storing to memory or to a register.

• Do not depend on the ability to retain information written into any reserved bits.

• When loading a register, always load the reserved bits with the values indicated in the documentation, if any,

or reload them with values previously read from the same register.

NOTE

Avoid any software dependence upon the state of reserved bits in Intel 64 and IA-32 registers.

Depending upon the values of reserved register bits will make software dependent upon the

unspecified manner in which the processor handles these bits. Programs that depend upon

reserved values risk incompatibility with future processors.

Vol. 3A

1-7

ABOUT THIS MANUAL

Data Structure

Highest

24 23

16 15

8 7

Bit offset

Address

Lowest

Byte 3

Byte 2

Byte 1

Byte 0

Address

Byte Offset

Figure 1-1. Bit and Byte Order

1.3.3

Instruction Operands

When instructions are represented symbolically, a subset of assembly language is used. In this subset, an instruc-

tion has the following format:

label: mnemonic argument1, argument2, argument3

where:

• A label is an identifier which is followed by a colon.

• A mnemonic is a reserved name for a class of instruction opcodes which have the same function.

• The operands argument1, argument2, and argument3 are optional. There may be from zero to three

operands, depending on the opcode. When present, they take the form of either literals or identifiers for data

items. Operand identifiers are either reserved names of registers or are assumed to be assigned to data items

declared in another part of the program (which may not be shown in the example).

When two operands are present in an arithmetic or logical instruction, the right operand is the source and the left

operand is the destination.

For example:

LOADREG: MOV EAX, SUBTOTAL

In this example LOADREG is a label, MOV is the mnemonic identifier of an opcode, EAX is the destination operand,

and SUBTOTAL is the source operand. Some assembly languages put the source and destination in reverse order.

1.3.4

Hexadecimal and Binary Numbers

Base 16 (hexadecimal) numbers are represented by a string of hexadecimal digits followed by the character H (for

example, F82EH). A hexadecimal digit is a character from the following set: 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, A, B, C, D,

E, and F.

Base 2 (binary) numbers are represented by a string of 1s and 0s, sometimes followed by the character B (for

example, 1010B). The “B” designation is only used in situations where confusion as to the type of number might

arise.

1.3.5

Segmented Addressing

The processor uses byte addressing. This means memory is organized and accessed as a sequence of bytes.

Whether one or more bytes are being accessed, a byte address is used to locate the byte or bytes memory. The

range of memory that can be addressed is called an address space.

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The processor also supports segmented addressing. This is a form of addressing where a program may have many

independent address spaces, called segments. For example, a program can keep its code (instructions) and stack

in separate segments. Code addresses would always refer to the code space, and stack addresses would always

refer to the stack space. The following notation is used to specify a byte address within a segment:

Segment-register:Byte-address

For example, the following segment address identifies the byte at address FF79H in the segment pointed by the DS

DS:FF79H

The following segment address identifies an instruction address in the code segment. The CS register points to the

code segment and the EIP register contains the address of the instruction.

CS:EIP

1.3.6

Syntax for CPUID, CR, and MSR Values

Obtain feature flags, status, and system information by using the CPUID instruction, by checking control register

bits, and by reading model-specific registers. We are moving toward a single syntax to represent this type of infor-

mation. See Figure 1-2.

CPUID Input and Output

CPUID.01H:EDX.SSE[bit 25] = 1

Input value for EAX register

Output register and feature flag or field

name with bit position(s)

Value (or range) of output

Control Register Values

CR4.OSFXSR[bit 9] = 1

Example CR name

Feature flag or field name

with bit position(s)

Value (or range) of output

Model-Specific Register Values

IA32_MISC_ENABLE.ENABLEFOPCODE[bit 2] = 1

Example MSR name

Feature flag or field name with bit position(s)

Value (or range) of output

Figure 1-2. Syntax for CPUID, CR, and MSR Data Presentation

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1.3.7

Exceptions

An exception is an event that typically occurs when an instruction causes an error. For example, an attempt to

divide by zero generates an exception. However, some exceptions, such as breakpoints, occur under other condi-

tions. Some types of exceptions may provide error codes. An error code reports additional information about the

error. An example of the notation used to show an exception and error code is shown below:

#PF(fault code)

This example refers to a page-fault exception under conditions where an error code naming a type of fault is

reported. Under some conditions, exceptions which produce error codes may not be able to report an accurate

code. In this case, the error code is zero, as shown below for a general-protection exception:

#GP(0)

1.4

RELATED LITERATURE

Literature related to Intel 64 and IA-32 processors is listed and viewable on-line at:

https://software.intel.com/en-us/articles/intel-sdm

Intel 64 and IA-32 Architectures. Software Developer’s Manual (Collection, 2023) - page 3