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General Initialization and Reset Operation
Driver accessible Wakeup Status registers are excluded from all resets except for
LAN_PWR_GOOD. This includes:
• Wakeup Status Register.
• Wakeup Packet Length.
• Wakeup Packet Memory.
Finally, the “Wakeup Context” as defined in the PCI Bus Power Management Interface
Specification is reset on LAN_PWR_GOOD, and is also reset on the deassertion of RST# if
AUX_POWER = 0b. This includes:
• PME_En bit of the Power Management Control/Status Register (PMCSR).
• PME_Status bit of the Power Management Control/Status Register (PMCSR).
The shadow copies of these bits in the Wakeup Control Register are treated identically.
14.8
Initialization of Statistics
Statistics registers are hardware-initialized to values as detailed in each particular register’s
description. The initialization of these registers begins upon transition to D0active power state
(when internal registers become accessible, as enabled by setting the Memory Access Enable of the
PCI Command register), and is guaranteed to be completed within 1 µs of this transition. Access to
statistics registers prior to this interval can return indeterminate values. Given typical system boot
times and the software driver’s Ethernet controller initialization routines, no initialization of these
registers through software should be necessary.
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Diagnostics and Testability
15
15.1
Diagnostics
This section explains the registers provided for diagnostic access.
These registers enable system level integration and debugging, including the ability to access all
internal memories. This information is often critical in determining failure modes and in
developing software workarounds.
At a diagnostic level, all of the major internal data structures visible to and controllable by
software, including all of the FIFO space. However, interlocks are not provided for any operations,
so diagnostic accesses need to be performed under very controlled circumstances.
15.1.1
FIFO State
The internal data FIFO pointers are visible through the head and tail diagnostic data FIFO registers
(see Section 13.8). Diagnostics software uses these FIFO pointers to confirm correct operation and
to directly write packets into, or directly read out of, the FIFO.
These registers are available for diagnostic purposes only and should not be written during normal
operation.
15.1.2
FIFO Data
All of the FIFO data is visible through the PBM register. Locations can be accessed as 32-bit or 64-
bit words. Refer to Section 13.8.11 for details.
15.1.3
Loopback
One loopback mode is provided in the Ethernet controller to assist with system and device debug.
This loopback mode is enabled via RCTL.LBM control bits. The Ethernet controller must be
operating in full-duplex mode for loopback.
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Diagnostics and Testability
15.1.3.1
Internal Loopback
This loopback mode internally loops back the transmit to receive path in the PHY, exercising the
internal GMII/MII bus. Programming both MAC and PHY is required. Following is the flow:
/* Auto-MDI/MDIX Off */
e1000_write_phy_reg(16, 0x0808);
/* reset to update Auto-MDI/MDIX */
e1000_write_phy_reg(0, 0x9140);
/* autoneg off */
e1000_write_phy_reg(0, 0x8140);
/* force 1000, set loopback */
e1000_write_phy_reg(0, 0x4140);
/* Now set up the MAC to the same speed/duplex as the PHY. */
ctrl_reg = E1000_READ_REG(CTRL);
ctrl_reg &= ~E1000_CTRL_SPD_SEL;
/* Clear the speed sel bits */
ctrl_reg |= (E1000_CTRL_FRCSPD |
/* Set the Force Speed Bit */
E1000_CTRL_FRCDPLX |
/* Set the Force Duplex Bit */
E1000_CTRL_SPD_1000 |
/* Force Speed to 1000 */
E1000_CTRL_FD);
/* Force Duplex to FULL */
/* Set the ILOS bit on the fiber Nic is half duplex link is detected. */
stat_reg = E1000_READ_REG(STATUS);
if((stat_reg & E1000_STATUS_FD) = 0)
ctrl_reg |= (E1000_CTRL_ILOS | E1000_CTRL_SLU);
E1000_WRITE_REG(CTRL, ctrl_reg);
15.2
Testability
The Ethernet controller uses full Boundary Scan/IEEE 1149.1 JTAG standard test methods. The
TAP controller supports EXTEST, SAMPLE/PRELOAD, IDCODE, USERCODE, and BYPASS
instructions.
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Diagnostics and Testability
15.2.1
EXTEST Instruction
This instruction allows testing of off-chip circuitry and board level interconnections. Data is
typically loaded onto the latched parallel outputs of the boundary-scan shift register stages using
the SAMPLE/PRELOAD instruction prior to selection of the EXTEST instruction.
15.2.2
SAMPLE/PRELOAD Instruction
This mandatory instruction allows a snapshot of the normal operation of the component to be taken
and examined. It also allows data values to be loaded onto the latched parallel outputs of the
boundary-scan shift register prior to selection of the other boundary-scan test instructions.
15.2.3
IDCODE Instruction
The IDCODE instruction provides information on the base component. When an Ethernet
controller identification register is included in a component design, the IDCODE instruction is
forced into the instruction register’s parallel output latches.
For example, the 82546EB controller’s ID is determined and derived from the manufacturer as
follows:
Component
ID Code
Ver
V
Product
Gen
Model
Manf ID
1
Product Code
(hex)
82546EB
0001
1
001001
0010
00100
00000001001
1
19244013
15.2.4
BYPASS Instruction
This instruction is the only instruction defined by the standard that causes operation of the bypass
register. The bypass register contains a single-shift register stage and is used to provide a minimum
length serial path between the TDI and TDO pins of a component when no test operation of that
component is required. This allows more rapid movement of test data to and from other
components on a board that are required to perform test operations.
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Diagnostics and Testability
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392
Appendix (Changes From 82544EI/82544GC)
A
A.1
Introduction
This section describes the new features that have been added to the PCI/PCI-X Family of Gigabit
Ethernet Controllers from its predecessor, the 82544EI/82544GC and highlights its registers that
have been changed.
A.2
New Features
Following is a list of the new features in the Ethernet controller, along with sections in this manual
that describe these features in detail:
• Integrated dual-port solution. The 82546GB/EB architecture includes two instances of both
the MAC and PHY. The Ethernet controller contains a single PCI/PCI-X interface so that each
of the logical LAN devices appear as a distinct PCI/PCI-X bus device (see Chapter 12).
• IPv6 Support. The Ethernet controller supports IP/TCP/UDP receive checksum offload for
IPv6 packets, IPv6 wakeup filters, and IPv6 TCP segmentation (see Chapter 3).
• Improved Interrupts. The Ethernet controller has the following new interrupt generation
features to enhance driver performance:
- Packet timers and absolute delay timers for transmit and receive (see Section 3.2.7).
- Short packet detection interrupts (see Section 3.2.7).
- Transmit descriptor low interrupts (see Section 3.4.3).
- Interrupt throttling control to limit maximum interrupt rate (see Section 13.4.8).
- Acknowledge interrupts by writing 1b’s to the ICR (see Section 13.4.17).
• EEPROM access. Because the 82546GB/EB has two MAC/PHY instances that could
potentially access the EEPROM at the same time, a semaphore has been added to gate access.
In addition, the EERD now allows easy EEPROM access (see Section 12.3.2).
• Manageability. The Ethernet controller introduces manageability for ASF 1.0 and AOL 2.0.
• Configurable LED. The Ethernet controller enables software to customize LED displays (see
Chapter 10).
• Power Management. The internal copper PHY features 10/100/1000-BaseT signalling and is
capable of performing intelligent power-management based on both the system power-state
and LAN energy-detection (detection of unplugged cables). See Chapter 6.
393
Appendix (Changes From 82544EI/82544GC)
A.3
Register Changes
Table A-1 lists the registers that have been added or changed in the Ethernet controller.
Table A-1. Register Changes
Register
Offset
CTRL
00000h
STATUS
00008h
EEC
00010h
EERD
00014h
CTRL_EXT
00018h
LEDCTL
00E00h
ICR
000C0h
ITR
000C4h
ICS
000C8h
IMS
000D0h
IMC
000D8h
RDTR
02820h
RXDCTL
02828h
RADV
0282Ch
RSRPD
02C00h
RXCSUM
05000h
TXDCTL
03828h
TADV
0382Ch
TPT
040D4h
PTC64
040D8h
PTC127
040DCh
PTC255
040E0h
PTC511
040E4h
PTC1023
040E8h
PTC1522
040ECh
MPTC
040F0h
BPTC
040F4h
394
Appendix (82540EP/EM and 82545GM/EM
Differences)
B
B.1
Introduction
This section describes the differences between the 82546GB/EB, the 82540EP/EM and the
82545GM/EM. All three of these Ethernet controllers come from the same family so their register
sets are essentially the same. The sections that follow describe the differences between the
82546GB/EB and the 82540EP/EM or 82545GM/EM, and resulting register differences and
developer impact.
B.2
82540EP/EM Differences
Below are the differences between the 82540EP/EM and the 82546GM/EM:
• Serial FLASH interface. The 82540EP/EM does not support a parallel FLASH interface.
• No TBI/internal SerDes interface. The 82540EP/EM provides internal GMII / MII
interfaces only
• Single-port functionality. The dual-port functionality of the 82546GB/EB is not included.
• 32-bit PCI support only. The 82540EP/EM does not support 64-bit PCI or PCI-X.
• Internal SerDes. The 82540EP/EM does not support internal SerDes.
The impact to registers and the developer are outlined in the following sections.
B.2.1
Serial FLASH Interface
The 82540EP/EM provides an external interface to a serial Flash or Boot EPROM device.
Hardware implements a serial command set compatible with the Atmel AT25-series devices in the
512 Kb (64 KB) thru 1024 Kb (128 KB) sizes. The size of the FLASH used with the 82540EP/EM
should be encoded into bits in EEPROM to configure the amount of address space required when
mapped. All accesses to this device are controlled by hardware and are accessible to software as
normal PCI reads or writes to the FLASH memory mapping range. The FLASH and Expansion
ROM BARs are reconfigured based on these EEPROM settings.
Note: The 82540EP/EM serial FLASH controller supports reads from programmed FLASH devices, and
writes to erased FLASH devices. Chip and sector-erase commands are not supported. It is
recommended that FLASH devices be socketed to enable removal for re-programming if
necessary.
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Appendix (82540EP/EM and 82545GM/EM Differences)
Note: Though the 82540EP/EM supports devices with up to 512 KB of memory, smaller devices may
also be used. Accesses to memory beyond the FLASH device size results in access wrapping as
only the lower address bits are utilized by the FLASH.
The 82540EP/EM does not provide an interface for performing an “Erase” operation to the serial
Flash device. Flash write operations must be performed to an initialized or pre-erased Flash device.
If in-circuit erase is required, an external source (such as hardware's software-definable pins) can
be used to drive the Flash pins to perform the erase operation.
B.2.2
No TBI/Internal SerDes Interface
The 82540EP/EM does not support a TBI/internal Serdes interface. As a result, all TBI/internal
SerDes-related registers (for example, RXCW) should not be used.
B.2.3
Single-Port Functionality
The 82540EP/EM and the 82545GM/EM do not have the dual-port functionality of the
82546GB/EB. As a result, the 82540EP/EM and the 82545GM/EM appear as single PCI bus
devices.
B.2.4
32-Bit PCI Support
No developer impact.
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