Content .. 10 11 12 13 ..

LoongArch Reference Manual. Volume 1: Basic Architecture (Version 1.02) - page 12

Table 77. Definition of fetch watchpoint overall controller register

Bits

Name

Read/Write

Description

5:0

Num

the number of fetch watchpoints.

If the virtualization extension is not implemented, the field is read-

19:16

only constant 0, and writing to this field is ignored.

31:20

Reserved field. Reads return 0 and the software does not allow to

change its value.

7.9.5. Fetch Watchpoint Overall Status (FWPS)

Table 78. Definition of fetch watchpoint overall status register

Bits

Name

Read/Write

Description

RW1^[3]

The hit status of the surveillance point. It corresponds to the

n-1:0

Status

watchpoint one by one, with bit i corresponding to watchpoint i.

When a PC with a fetch instruction hits a watchpoint, its

corresponding bit is set to 1, the hardware does not clear the bits

in this field except during reset.

The software can only clear them by writing 1, writing 0 is

ignored.

15:n .

Read-only constant 0, writing to this field is ignored.

Skip

The software notifies the hardware to ignore the next fetch point

hit result by setting this location to 1. By ignore, it means that

neither the corresponding bit in the Stauts field of this register is

set to 1 nor the watchpoint exception is triggered. This function

can avoid endlessly triggering the same watchpoint repeatedly

without canceling it, thus simplifying the handling of watchpoint

exceptions.

When the Skip bit is 1, if the hardware encounters a hit on a fetch

point, it will ignore the hit and clear the Skip bit to 0. This means

that each time the software sets the Skip bit to 1, the hardware

will ignore at most one hit on the point. This feature also causes

the software to write 1 to this bit and then read out the value

which may not be 1.

This Skip bit corresponds to all fetch watchpoints. If the

software modifies the configuration of the breakpoint and

replaces it, do not set this bit, or even write 0 to clear it for safety

reasons.

31:17

Read-only constant 0, writing to this field is ignored.

7.9.6. Fetch Watchpoint n Configuration (FWPnCFG1-FWPnCFG3)

The information contained in the configuration 1 to 3 registers of each fetch instruction watchpoint is used

directly for comparison judgments of watchpoint checks. The process of judging the hit of each watchpoint

is as follows:

157

If CSR.CRMD.WE=0, the judgment is terminated, otherwise turn 2;

If the current is not in debug mode but the DMOnly bit of FWPCFG3 is equal to 1, the judgment is

terminated, otherwise turn to 3;

If the bit corresponding to the current privilege level in PLV0-PLV3 of FWPCFG3 is equal to 0, judge and

terminate, otherwise turn to 4;

If the LCL bit in FWPCFG3 is equal to 1, but the CSR.ASID.ASID is not equal to the ASID in FWPCFG4,

the judgment is terminated, otherwise turn 6;

If (pc &

(~FWPCFG2.Mask)) != (FWPCFG1.VAddr & (~FWPCFG2.Mask)), that is, the address

comparison is not equal, the judgment is terminated, otherwise the watchpoint is considered hit.

Table 79. Definition of fetch watchpoint n configuration 1 register

Bits

Name

Read/Write

Description

the virtual address of the fatch watchpoint to be compared.

GRLEN-1:0

VAddr

Table 80. Definition of fetch watchpoint n configuration 2 register

Bits

Name

Read/Write

Description

GRLEN-1:0

Mask

the mask bit of the fetch watchpoint address comparison. If bit i

≤ i < GRLEN) is 1, it means that bit i of the address is not

involved in the comparison.

Table 81. Definition of fetch watchpoint n configuration 3 register

Bits

Name

Read/Write

Description

DMOnly

A bit of 1 indicates that the fetch point is only available in debug

mode. Here "available" contains two meanings: First, the

configuration register of the fetch watchpoint can be modified by

software in this mode, and second, the check hit of the

watchpoint will trigger a watchpoint exception and mark the

status of the watchpoint only in this mode.

This bit can only be modified in debug mode (CSR.DBG.DM=1).

This means that the (Host) software running in debug mode has

the priority to use the watchpoint.

PLV0

This watchpoint triggers the enable of the watchpoint exception

at the PLV0 privilege level. 1 - enable, 0 - disable.

PLV1

The watchpoint triggers the watchpoint exception enable at PLV1

privilege level. 1 - enable, 0 - disable.

PLV2

The watchpoint triggers the enable of the watchpoint exception at

the PLV2 privilege level. 1 - enable, 0 - disable.

This watchpoint triggers the enablement of the watchpoint

PLV3

exception at the PLV3 privilege level. 1 - enable, 0 - disable.

If virtualization extensions are not implemented, the field is read-

6:5

only constant to 0 and writes are ignored.

LCL

1 indicates that the comparison of ASIDs is performed during the

watchpoint check.

31:8

Reserved field. Return 0 if read this field and software is not

allowed to change its value.

158

Table 82. Definition of fetch watchpoint n configuration 4 register

Bits

Name

Read/Write

Description

9:0

ASID

The ASID being compared

15:10

Read-only constant 0, writing to this field is ignored.

23:16

If the virtualization extension is not implemented, the field is read-

only constant 0 and writing to this field is ignored.

31:24

Read-only constant 0, writing to this field is ignored.

7.10. Control and Status Registers Related to Debugging

7.10.1. Debug Register (DBG)

Table 83. Definition of debug data save register

Bits

Name

Read/Write

Description

DST

1 to indicate that it is currently in debug mode.

The hardware sets this bit to 1 when a debug exception is

triggered in non-debug mode.

When this bit is 1, the ERTN instruction is executed to clear this

bit to 0.

7:1

DRev

The version number of the debugging mechanism. 1 is the initial

version.

DEI

1 indicates that the debug exception type caught in debug mode

is DEbug Interrupt (DEI).

DCL

1 indicates that the type of debug exception caught in debug

mode is a Debug CaLl exception (DCL).

DFW

1 indicates that the type of debug exception caught in debug

mode is the Debug Fetch Watchpoint exception (DFW).

DMW

1 indicates that the debug exception type caught in debug mode

is the Debug load/store (Memory) Watchpoint exception (DMW).

15:12

Read only as 0.

When a non-debug exception occurs in debug mode, the

21:16

Ecode

exception type code is recorded here. The meaning of the codes

here is basically the same as the definitions in Table of exception

encoding, with only three differences:

•

The TLB refill exception reuses the 0x7 exception code;

•

The debug call exception uses the 0xC exception code;

•

The machine error exception uses the 0xE exception code.

31:22

Read only as 0.

159

7.10.2. Debug Exception Return Address (DERA)

Table 84. Definition of debug exception program counter register

Bits

Name

Read/Write

Description

When a debug exception is triggered in non-debug mode, the

63:0

hardware records the PC that triggered the exception here.

When CSR.DBG.DM=1, the return address is fetched from here

when the ERTN instruction is executed.

7.10.3. Debug Data Save Register (DSAVE)

This register is used to store data temporarily for the system software. Each dava save register can hold

the data of one general-purpose register.

An additional SAVE register for debug exception handler is provided because debug exceptions can occur

in any scenario and the handling of debug exceptions should be transparent to the software on the Host

being debugged.

Table 85. Definition of debug register

Bits

Name

Read/Write

Description

63:0

Data

Data for software to read and write only. The hardware does not

modify the contents of this field except for the execution of CSR

instructions.

1. The instructions affected by this control bit include LD[X].{H[U]/W[U]/D}, ST[X].{H/W/D}, LDPTR.{W/D}, STPTR.{W/D},

FLD[X].{S/D}, FST[X].{S/D}, LDPTE, LDDIR, IOCSRRD.{H/W/D} and IOCSRWR.{H/WD}.

2. Translator’s note: This may be the fifth attribute not listed in Attributes of Reading and Writing.

3. Translator’s note: This may be the fifth attribute not listed in Attributes of Reading and Writing.

160

Appendix A: Pseudocode Descriptions of the

Function Definitions

A.1. Interpretation of Operators in Pseudocode

This section lists the meaning of the statement keywords and various operators involved in pseudocode, as

well as the operator precedence relationships. In addition, the common conventions for different binary

representations of numeric values in pseudocode are as follows:

•

No prefix or 'd or ##'d prefix for decimal numbers, where the ##'d prefix means that the decimal

number is ## bits wide;

•

The prefix 'b or ##'b is used for binary numbers, where the prefix ##'b indicates that the length of the

binary number is ## bits;

•

The prefix 'h or ##'h indicates the hexadecimal number, where the prefix ##'h indicates that the

hexadecimal number is ## bits wide, and the hexadecimal value of A-F uses uppercase letters.

Table 86. Interpretation of semantic keyword

Operators

Meaning

Function Definition

Return_Type

Function_Name(Variable, ...):

Function_Body

return Return_Value

Conditional Statements

if Condition1:

Statement1

elif Condition2:

Statement2

else:

Statement3

case conditional statement

case Variable of:

value1: Statement1

value2: Statement2

default: Default_Statement

Conditional Judgment Statements

Condition ? TRUE_Statement:

FALSE_Statement

for loop statement

for Variable in Sequence:

Statements

161

Operators

Meaning

A sequence of integers from 0 to N-1 in steps of 1

range(N)

Sequence of specified step values from the start

range(Start, End, Step)

value (inclusive) to the end value (exclusive)

Terminate the current loop

break

Signed integers

signed(...)

Unsigned integers

unsigned(...)

Half-precision floating-point numbers

fp16(...)

Single-precision floating-point numbers

fp32(...)

Double-precision floating-point numbers

fp64(...)

Boolean Type

boolean

Bit type

bit

Integer type

integer

N-bit type

bits(N)

Variable zero extended to N bits

ZeroExtend(Variable, N)

Variable sign extended to N bits

SignExtend(Variable, N)

TRUE if the variable is a signaling NaN number,

isSNaN(Variable)

FALSE otherwise

TRUE if the variable is quiet NaN number, FALSE

isQNaN(Variable)

otherwise

162

Operators

Meaning

Trigger exception

SignalException(Exception)

Single line comment

Assignment

Table 87. Interpretation of bit string operators

Operators

Meaning

[M:N]

Bit N to bit M of the bit string

{N{M}}

Copy bit string M N times and splice them

{N, M, …}

Splice bit strings N, M, … in order

Table 88. Interpretation of arithmetic operators

Operators

Meaning

Add

Subtract

Multiply

Divide

Modulo

Power

Table 89. Interpretation of comparison operators

Operators

Meaning

equal to

Not equal to

Greater than

Less than

Greater than or equal to

Less than or equal to

Table 90. Interpretation of bit operators

Operators

Meaning

Bitwise AND

Bitwise OR

Bitwise XOR

Bitwise INVERSE

163

Operators

Meaning

Logical Left Shift

Logical Right Shift

Arithmetic Right Shift

>>>

Table 91. Interpretation of logical operators

Operators

Meaning

and

Logical AND

Logical OR

Logical NOT

not

Table 92. Operator priority

Operators

Meaning

Power

Inverse by place

Multiply, Divide, Modulo

*, /, %

+, -

Add, Subtract

Logical left shift, logical right shift, arithmetic right

<<, >>, >>>

shift

Bitwise AND

^, |

Bitwise XOR, bitwise OR

Greater than, less than, greater than or equal to, less

>, <, >=, <=

than or equal to

==, !=

Equal to, not equal to

Logical NOT

not

Logical AND, logical OR

and, or

A.2. Pseudocode Descriptions of Functional Functions

The pseudocode involved in the instruction descriptions in this manual is defined as follows.

A.2.1. Logical Left Shift

bits(N) SLL(bits(N) x, integer sa):

if sa == 0:

result = x

else:

result = {x[N-sa-1:0], {sa{1'b0}}}

return result

164

A.2.2. Logical Right Shift

bits(N) SRL(bits(N) x, integer sa):

if sa == 0:

result = x

else:

result = {{sa{1'b0}}, x[N-1:sa]}

return result

A.2.3. Arithmetic Right Shift

bits(N) SRA(bits(N) x, integer sa):

if sa == 0:

result = x

else:

result = {{sa{x[N-1]}}, x[N-1:sa]}

return result

A.2.4. Circular Right Shift

bits(N) ROTR(bits(N) x, integer sa):

if sa == 0:

result = x

else:

result = {x[sa-1:0], x[N-1:sa]}

return result

A.2.5. Count the Number of Consecutive 1’s Starting from High Order Bits

{bits(N)} CLO(bits(N) x):

cnt = 0

for i in range(N):

if x[N-1-i] == 1'b0:

return cnt

else:

cnt = cnt + 1

A.2.6. Count the Number of Consecutive 0’s Starting from High Order Bits

{bits(N)} CLZ(bits(N) x):

165

cnt = 0

for i in range(N):

if x[N-1-i] == 1'b1:

return cnt

else:

cnt = cnt + 1

A.2.7. Count the Number of Consecutive 1’s Starting from Low Order Bits

{bits(N)} CTO(bits(N) x):

cnt = 0

for i in range(N):

if x[i] == 1'b0:

return cnt

else:

cnt = cnt + 1

A.2.8. Count the Number of Consecutive 0’s Starting from Low Order Bits

{bits(N)} CTZ(bits(N) x):

cnt = 0

for i in range(N):

if x[i] == 1'b1:

return cnt

else:

cnt = cnt + 1

A.2.9. Reverse the Order of the Bit String

{bits(N)} BITREV(bits(N) x):

for i in range(N):

res[i] = x[N-1-i]

return res

A.2.10. CRC-32 Checksum Calculation

bits(32) CRC32(old_chksum, msg, width, poly):

new_chksum = (old_chksum & 0xFFFFFFFF) ^ {{(64-width){1'b0}}, msg}

for i in range(width):

if (new_chksum & 1'b1):

166

new_chksum = (new_chksum >> 1) ^ poly

else:

new_chksum = (new_chksum >> 1)

return new_chksum

A.2.11. Single Precision Floating-point to Signed Word Integer

{bits(32)} FP32convertToSint32(bits(32) x, bits(1) I_en, bits(2) rm):

case {I_en, rm} of:

{1'b1, 2'd0}: return Sint32_convertToIntegerExactTiesToEven(x)

{1'b1, 2'd1}: return Sint32_convertToIntegerExactTowardZero(x)

{1'b1, 2'd2}: return

Sint32_convertToIntegerExactTowardPositive(x)

{1'b1, 2'd3}: return

Sint32_convertToIntegerExactTowardNegative(x)

{1'b0, 2'd0}: return Sint32_convertToIntegerTiesToEven(x)

{1'b0, 2'd1}: return Sint32_convertToIntegerTowardZero(x)

{1'b0, 2'd2}: return Sint32_convertToIntegerTowardPositive(x)

{1'b0, 2'd3}: return Sint32_convertToIntegerTowardNegative(x)

A.2.12. Single Precision Floating-point to Signed Double Word Integer

{bits(64)} FP32convertToSint64(bits(32) x, bits(1) I_en, bits(2) rm):

case {I_en, rm} of:

{1'b1, 2'd0}: return Sint32_convertToIntegerExactTiesToEven(x)

{1'b1, 2'd1}: return Sint32_convertToIntegerExactTowardZero(x)

{1'b1, 2'd2}: return

Sint32_convertToIntegerExactTowardPositive(x)

{1'b1, 2'd3}: return

Sint32_convertToIntegerExactTowardNegative(x)

{1'b0, 2'd0}: return Sint32_convertToIntegerTiesToEven(x)

{1'b0, 2'd1}: return Sint32_convertToIntegerTowardZero(x)

{1'b0, 2'd2}: return Sint32_convertToIntegerTowardPositive(x)

{1'b0, 2'd3}: return Sint32_convertToIntegerTowardNegative(x)

A.2.13. Double Precision Floating-point to Signed Word Integer

{bits(64)} FP64convertToSint32(bits(64) x, bits(1) I_en, bits(2) rm):

case {I_en, rm} of:

{1'b1, 2'd0}: return Sint64_convertToIntegerExactTiesToEven(x)

{1'b1, 2'd1}: return Sint64_convertToIntegerExactTowardZero(x)

{1'b1, 2'd2}: return

167

Sint64_convertToIntegerExactTowardPositive(x)

{1'b1, 2'd3}: return

Sint64_convertToIntegerExactTowardNegative(x)

{1'b0, 2'd0}: return Sint64_convertToIntegerTiesToEven(x)

{1'b0, 2'd1}: return Sint64_convertToIntegerTowardZero(x)

{1'b0, 2'd2}: return Sint64_convertToIntegerTowardPositive(x)

{1'b0, 2'd3}: return Sint64_convertToIntegerTowardNegative(x)

A.2.14. Double Precision Floating-point to Signed Double Word Integer

{bits(64)} FP64convertToSint64(bits(64) x, bits(1) I_en, bits(2) rm):

case {I_en, rm} of:

{1'b1, 2'd0}: return Sint64_convertToIntegerExactTiesToEven(x)

{1'b1, 2'd1}: return Sint64_convertToIntegerExactTowardZero(x)

{1'b1, 2'd2}: return

Sint64_convertToIntegerExactTowardPositive(x)

{1'b1, 2'd3}: return

Sint64_convertToIntegerExactTowardNegative(x)

{1'b0, 2'd0}: return Sint64_convertToIntegerTiesToEven(x)

{1'b0, 2'd1}: return Sint64_convertToIntegerTowardZero(x)

{1'b0, 2'd2}: return Sint64_convertToIntegerTowardPositive(x)

{1'b0, 2'd3}: return Sint64_convertToIntegerTowardNegative(x)

A.2.15. Round Single Precision Floating-point

{bits(32)} FP32_roundToInteger(bits(N) x, bits(1) I_en, bits(2) rm):

if (I_en):

return FP32_roundToIntegralExact(x)

elif (rm == 0):

return FP32_roundToIntegerTiesToEven(x)

elif (rm == 1):

return FP32_roundToIntegerTowardZero(x)

elif (rm == 2):

return FP32_roundToIntegerTowardPositive(x)

elif (rm == 3):

return FP32_roundToIntegerTowardNegative(x)

A.2.16. Round Double Precision Floating-point

{bits(64)} FP64_roundToInteger(bits(N) x, bits(1) I_en, bits(2) rm):

if (I_en):

return FP64_roundToIntegralExact(x)

168

elif (rm=0):

return FP64_roundToIntegerTi esToEven(x)

elif (rm=1):

return FP64_roundToIntegerTowardZero(x)

elif (rm=2):

return FP64_roundToIntegerTowardPositive(x)

elif (rm=3):

return FP64_roundToIntegerTowardNegative(x)

169

Appendix B: Table of Instruction Encoding

Table 93. Table of instruction encoding

CLO

rd,

CLZ

rd,

CTO

rd,

CTZ

rd,

CLO

rd,

CLZ

rd,

CTO

rd,

CTZ

rd,

REV

rd,

B.2

REV

rd,

B.4

REV

rd,

B.2

REV

rd,

B.D

REV

rd,

H.2

REV

rd,

H.D

BIT

rd,

REV

.4B

170

BIT

rd,

REV

.8B

BIT

rd,

REV

BIT

rd,

REV

EXT

rd,

.W.

EXT

rd,

.W.

RDT

rd,

IME

L.W

RDT

rd,

IME

H.W

RDT

rd,

IME

CPU

rd,

CFG

ASR

rj,

TLE

ASR

rj,

TGT

ALS

rd,

sa2

L.W

rj,

rk,

sa2

ALS

rd,

sa2

L.W

rj,

rk,

sa2

171

Content .. 10 11 12 13 ..