|
|
|
Bits
Name
Read/Write
Description
9
RPCNTL1
RW
Whether to allow software reads of the performance counter at
the PLV1 privilege level. When this bit is 1, the PLV1 privilege level
PCNT will not trigger an instruction privilege level error exception
(IPE), if the CSRRD instruction is used to access any of the
implemented performance counters at the PLV1 privilege level.
RW
Whether software reads of the performance counter are allowed
10
RPCNTL2
at the PLV2 privilege level. When this bit is 1, the PLV2 privilege
level When this bit is 1, accessing any implemented performance
counter PCNT with CSRRD instruction at the PLV2 privilege level
does not trigger instruction privilege level error exception (IPE).
11
RPCNTL3
RW
Whether software reads of the read performance counter are
allowed at the PLV3 privilege level. When this bit is 1, the PLV3
privilege level When this bit is 1, accessing any implemented
performance counter PCNT with the CSRRD instruction at the
PLV3 privilege level does not trigger an instruction privilege level
error exception (IPE).
12
ALCL0
RW
Whether to perform a non-alignment check for non-vector
load/store instructions that are allowed to be non-aligned at PLV0
privilege level. 1 indicates that the check is performed, and an
address alignment error exception is triggered if illegal. This bit is
read/write only if the hardware implementation supports non-
aligned addresses for these non-vector load/store instructions.
Otherwise, the bit is a read-only constant 1.
RW
Whether to perform a non-alignment check for non-vector
13
ALCL1
load/store instructions[1] that are allowed to be non-aligned at the
PLV1 privilege level. 1 indicates that the check is performed and
triggers an address alignment error exception if illegal.
This bit is read/write only if the hardware implementation
supports non-aligned addresses for these non-vector load/store
instructions. Otherwise, the bit is a read-only constant 1.
RW
Whether to perform a non-alignment check for non-vector
14
ALCL2
load/store instructions[1] that are allowed to be non-aligned at the
PLV2 privilege level. 1 indicates that the check is performed and
triggers an address alignment error exception if illegal.
This bit is read/write only if the hardware implementation
supports non-aligned addresses for these non-vector load/store
instructions. Otherwise, the bit is a read-only constant 1.
RW
Whether to perform a non-alignment check for non-vector
15
ALCL3
load/store instructions[1] that are allowed to be non-aligned at the
PLV3 privilege level. 1 indicates that the check is performed and
triggers an address alignment error exception if illegal.
This bit is read/write only if the hardware implementation
supports non-aligned addresses for these non-vector load/store
instructions. Otherwise, the bit is a read-only constant 1.
127
Bits
Name
Read/Write
Description
16
DWPL0
RW
Whether to disable the check of the page table entry write
protection during TLB virtual and real address translation at the
PLV0 privilege level. When this bit is 1, the store instruction will
not trigger a page modification exception even if it accesses a
page table entry with D=0.
RW
Whether to disable the check of the page table entry write
17
DWPL1
protection during TLB virtual and real address translation at the
PLV1 privilege level. When this bit is 1, the store instruction will
not trigger a page modification exception even if it accesses a
page table entry with D=0.
18
DWPL2
RW
Whether to disable the check of the page table entry write
protection during TLB virtual and real address translation at the
PLV2 privilege level. When this bit is 1, the store instruction will
not trigger a page modification exception even if it accesses a
page table entry with D=0.
RO
31:19
0
Reserved field. Return 0 if read this field and software is not
allowed to change its value.
7.4.5. Exception Configuration (ECFG)
This register is used to control the entry calculation method of exceptions and interrupts and the local
enable bit of each interrupt.
Table 19. Definition of exception configuration register
Bits
Name
Read/Write
Description
RW
Local interrupt enable bits, which are high valid. These local
12:0
LIE
interrupt enable bits correspond to the 13 interrupt sources
recorded in the IS field in CSR.ESTAT. Each bit controls one
interrupt source.
R0
15:13
0
Reserved field. Return 0 if read this field, and software is not
allowed to change its value.
KW
Configure the spacing of exceptions and interrupt entries. When
18:16
VS
VS=0, all exceptions and interrupts have the same entry base
address. When VS!=0, the entry base address spacing between
each exception and interrupt is 2VS instructions. Since the TLB
refill exceptions and machine error exceptions have separate
entry base addresses, the entry of both exceptions is not affected
by the VS field.
RO
31:19
0
Reserved field. Return 0 if read this field, and software is not
allowed to change its value.
7.4.6. Exception Status (ESTAT)
This register records the status information of the exceptions, including the first and second level encoding
of the triggered exceptions, and the status of each interrupt.
Table 20. Definition of exception status register
128
Bits
Name
Read/Write
Description
1:0
IS[1:0]
RW
The status bits of the two software interrupts. Bit 0 and 1
correspond to SWI0 and SWI1 respectively.
Software interrupt setting is also done by these two bits, writing 1
sets the interrupt, and writing 0 clears the interrupt.
12:2
IS[12:2]
R
The interrupt status bit. 1 indicates that the corresponding
interrupt is set up. There is 1 inter-processor interrupt (IPI), 1
timer interrupt (TI), 1 performance counter overflow interrupt
(PCOV), 8 hardware interrupts (HWI0-HWI7).
In line-based interrupt mode, the hardware only records each
interrupt source per clock cycle to these bits. The requirement
that all interrupts must be level interrupts at this time is
guaranteed by the interrupt source and is not maintained here.
15:13
0
R0
Reserved field. Return 0 if read this field, and software is not
allowed to change its value.
R
Exception encoding. When an exception is triggered: if it is a TLB
21:16
Ecode
refill exception or a machine error exception, this field remains
unchanged; otherwise, the hardware writes the value defined in
the Ecode column in the following table to this field according to
the exception type.
R
Exception sub encoding. When an exception is triggered: if it is a
30:22
EsubCode
TLB refill exception or a machine error exception, the field
remains unchanged; otherwise, the hardware writes the value
defined in the EsubCode column in the following table to this
field according to the exception type.
R0
31
0
Reserved field. Return 0 if read this field and software is not
allowed to change its value.
Table 21. Table of exception encoding
Ecode
EsubCode
Exception Code
Exception Type
0x0
INT
Only when CSR.ECFG.VS=0, it means it is an
INTerrupt.
Page Invalid exception for Load operation
0x1
PIL
0x2
PIS
Page Invalid exception for Store operation
Page Invalid exception for Fetch operation
0x3
PIF
Page Modification Exception
0x4
PME
0x5
PNR
Page Non-Readable exception
Page Non-eXecutable exception
0x6
PNX
Page Privilege level Illegal exception
0x7
PPI
0x8
0
ADEF
ADdress error Exception for Fetching instructions
ADdress error Exception for Memory access
1
ADEM
instructions
0x9
ALE
Address aLignment fault Exception
129
Ecode
EsubCode
Exception Code
Exception Type
0xA
BCE
Bound Check Exception
SYStem call exception
0xB
SYS
BReaKpoint exception
0xC
BRK
0xD
INE
Instruction Non-defined Exception
Instruction Privilege error Exception
0xE
IPE
Floating-Point instruction Disable exception
0xF
FPD
0x10
SXD
128-bit vector (SIMD instructions) eXpansion
instruction Disable exception
256-bit vector (Advanced SIMD instructions) e
0x11
ASXD
Xpansion instruction Disable exception
0x12
0
FPE
Floating-Point error Exception
Vecctor Floating-Point error Exception
1
VFPE
WatchPoint Exception for Fetch watchpoint
0x13
0
WPEF
1
WPEM
WatchPoint Exception for Memory load/store
watchpoint
Binary Translation expansion instruction Disable
0x14
BTD
exception
Binary Translation related exceptions
0x15
BTE
Guest Sensitive Privileged Resource exception
0x16
GSPR
0x17
HVC
HyperVisor Call exception
0x18
0
GCSC
Guest CSR Software Change exception
Guest CSR Hardware Change exception
1
GCHC
0x1A-0x3E
Reserved Codes
7.4.7. Exception Return Address (ERA)
When an exception is triggered, if the exception type is neither a TLB refill exception nor a machine error
exception, the PC of the instruction that triggered the exception will be recorded in this register.
Table 22. Definition of exception program counter register
Bits
Name
Read/Write
Description
RW
When an exception is triggered:
GRLEN-1:0
PC
this field remains unchanged if the exception is a TLB refill
exception or a machine error exception;
otherwise, the hardware records the PC of the instruction that
triggered the exception here. For LA64, in this case, if the privilege
level that triggered the exception is in 32-bit address mode, then
the higher 32 bits of the recorded PC are forced to 0.
130
7.4.8. Bad Virtual Address (BADV)
This register is used to record the bad address when a bad address exception is triggered. Such exceptions
include:
•
ADdress error Exception for Fetching instructions (ADEF), at this time the PC of the instruction is
recorded
• ADdress error Exception for Memory access instructions (ADEM)
• Address aLignment fault Exception (ALE)
• Bound Check Exception (BCE)
• Page Invalid exception for Load operation (PIL)
• Page Invalid exception for Store operation (PIS)
• Page Invalid exception for Fetch operation (PIF)
• Page Modification Exception (PME)
• Page Non-Readable exception (PNR)
• Page Non-eXecutable exception (PNX)
• Page Privilege level Illegal exception (PPI)
Table 23. Definition of bad virtual address register
Bits
Name
Read/Write
Description
GRLEN-1:0
VAddr
RW
When a bad address exception exception is triggered, the
hardware records the bad address here. For LA64, if the privilege
level that triggered the exception is in 32-bit address mode, the
high 32 bits of the recorded virtual address are forced to 0.
7.4.9. Bad Instruction (BADI)
This register is used to record the instruction code of the instruction that triggers the synchronous-related
exception. The so-called synchronous-related exceptions are all exceptions except the INTerrupt (INT), the
Guest CSR Hardware Change exception (GCHC), and the Machine ERRor exception (MERR).
Table 24. Definition of bad instruction register
Bits
Name
Read/Write
Description
R
When a synchronous-related exception is triggered, the hardware
31:0
Inst
records the instruction code that triggered the exception here.
7.4.10. Exception Entry Base Address (EENTRY)
This register is used to configure the entry base address for general exceptions and interrupts.
Table 25. Definition of exception entry base address register
Bits
Name
Read/Write
Description
11:0
0
R
Read-only constant 0, writing to this field is ignored.
GRLEN-
VPN
RW
The virtual page table number of the entry base address for
general exceptions and interrupts.
1:12
131
7.4.11. Reduced Virtual Address Configuration (RVACFG)
This register is used to control the length of the address being reduced in the virtual address reduction
mode.
Table 26. Definition of reduced virtual address configuration register
Bits
Name
Read/Write
Description
RW
The number of the high order bits of the address to be reduced in
3:0
RBits
the virtual address reduction mode. It can be configured to a
value between 0 and 8.
0 is a special configuration value that means that the virtual
address reduction mode is disabled.
If the configured value is greater than 8, the processor behavior is
undefined.
R0
31:4
0
Reserved field. Return 0 if read this field and software is not
allowed to change its value.
7.4.12. CPU Identity (CPUID)
This register contains the processor core number information.
Table 27. Definition of CPU identity register
Bits
Name
Read/Write
Description
8:0
CoreID
R
The number of the processor core. This information is used by
the software to distinguish the individual processor cores in a
multi-core system. When the system is integrated, the processor
core number information for each processor core is set by the
hardware according to the specific implementation. It is
recommended that the processor core number be incremented
from 0 in the system.
R0
31:9
0
Reserved field. Return 0 if read this field and software is not
allowed to change its value.
7.4.13. Privileged Resource Configuration 1 (PRCFG1)
This register contains the privileged resources information.
Table 28. Definition of privileged resource configuration 1 register
Bits
Name
Read/Write
Description
3:0
SAVENum
R
The number of SAVE control and status registers.
11:4
TimerBits
R
The number of valid bits of the timer minus 1.
R
The maximum value that can be set for the exception and
14:12
VSMax
interrupt vector entry spacing (CSR.ECTL.VS).
R0
31:15
0
Reserved field. Return 0 if read this field and software is not
allowed to change its value.
132
7.4.14. Privileged Resource Configuration 2 (PRCFG2)
This register contains the privileged resources information.
Table 29. Definition of privileged resource configuration 2 register
Bits
Name
Read/Write
Description
GRLEN-1:0
PSAVL
R
Indicates the page size that the TLB can support (Page Size).
When bit i is 1, it indicates that a page size of 2i bytes is
supported.
7.4.15. Privileged Resource Configuration 3 (PRCFG3)
This register contains the privileged resources information.
Table 30. Definition of privileged resource configuration 3 register
Bits
Name
Read/Write
Description
3:0
TLBType
R
Indicates how the TLB is organized:
0: No TLB;
1: a fully associated Multiple page size TLB (MTLB)
2: One fully associative Multiple page size TLB (MTLB) + one
group associative Singular-Page-Size TLB (STLB);
Other values: Reserved.
11:4
MTLBEntri
R
When TLBType=0, the field is read-only constant 0;
es
When TLBType=1 or TLBType=2, the value of this field is the
number of entries in the fully associative multipage size TLB
minus 1.
19:12
STLBWays
R
When TLBType=0 or TLBType=1, the field is read-only constant
at 0;
When TLBType=2, the value of this field is the number of ways in
the group associative singular-page-size TLB minus 1.
25:20
STLBSets
R
When TLBType=0 or TLBType=1, the field is read-only constant
to 0;
When TLBType=2, the value of this field is the power of the
number of entries per way in the group associative singular-page-
size TLB, i.e., 2STLBSets entries per way.
31:26
0
R0
Reserved field. Return 0 if read this field and the software is not
allowed to change its value.
7.4.16. Data Save Register (SAVE)
The data save registers are used to temporarily store data for the system software. Each data save register
can store data from one general-purpose register.
133
The minimum number of data save registers is 1, and the maximum number is 16. The exact number of
registers can be found in CSR.PRCFG1.SAVENum. Starting from SAVE0, the addresses of each SAVE
register are 0x30, 0x31, … , 0x30+SAVENum-1.
All data save control and status registers have the same format, as shown in the table.
Table 31. Definition of data save register
Bits
Name
Read/Write
Description
GRLEN-1:0
Data
RW
Data for software to read and write only. The hardware does not
modify the contents of this field except for the execution of CSR
instructions.
7.4.17. LLBit Controller (LLBCTL)
This register is used for the access control operations performed on the LLBit.
Table 32. Definition of LLBit controller register
Bits
Name
Read/Write
Description
R
A read-only bit. Reading this bit will return the value of the current
0
ROLLB
LLBit.
W1
1
WCLLB
A software writing 1 to this bit will clear the LLBit to 0. A
software writing 0 to this bit will be ignored by hardware.
RW
2
KLO
Used to control the operation of the LLBit when the ERTN
instruction is executed. When this bit is 1, the LLBit is not
cleared to 0 when the ERTN instruction is executed. But the bit is
automatically cleared to 0 by the hardware; it means that each
time KLO is set to 1, it can only affect the execution of the ERTN
instruction once.
R0
31:3
0
Reserved field. Return 0 if read this field, and software is not
allowed to change its value.
7.4.18. Implementation-specific Controller 1 (IMPCTL1)
This register contains control information related to the microstructure characteristics at the time of the
specific implementation. Its format and the specific meaning of each field are defined by the specific
implementation.
7.4.19. Implementation-specific Controller 2 (IMPCTL2)
This register contains control information related to the microstructure characteristics at the time of the
specific implementation. Its format and the specific meaning of each field are defined by the specific
implementation.
7.4.20. Cache Tags (CTAG)
This register is used when the CACOP instruction accesses the Cache directly, to store the contents read
from the CacheTag or the contents to be written to the CacheTag. The format and the meaning of each
field are defined by the implementation.
134
7.5. Control and Status Registers Related to Mapped Address
Translation
7.5.1. TLB Index (TLBIDX)
This register contains information such as the index associated with the TLB-related instruction when
executing TLB-related instructions. The length of the Index field in the table depends on implementation,
although LoongArch allows for an Index length of no more than 16 bits.
This register also contains the information related to the PS and P fields in the TLB table entry when
executing TLB-related instructions.
Table 33. Definition of TLB index register
Bits
Name
Read/Write
Description
RW
n-1:0
Index
When executing the TLBRD and TLBWR instructions, the index of
the access TLB table entry comes from here.
When executing the TLBSRCH instruction, if it hits, the index of the
hit entry is recorded here.
For the correspondence between index values and TLB table
entries, refer to the relevant section in TLB Maintenance
Instructions.
R
15:n
0
Read-only constant 0, writing to this field is ignored.
23:16
0
RO
Reserved field. Return 0 if read this field and software is not
allowed to change its value.
RW
29:24
PS
When executing the TLBRD instruction, the value read from the PS
field of the TLB table entry is recorded here.
When executing the TLBWR and TLBFILL instructions with
CSR.TLBRERA.IsTLBR=0, the value written to the PS field of the
TLB table entry comes from here.
30
0
RO
Reserved field. Return 0 if read this field and the software does
not allow to change its value.
RW
31
NE
1 means the TLB table entry is empty (invalid TLB table entry),
and 0 means the TLB table entry is non-empty (valid TLB table
entry)
When executing the TLBSRCH instruction, this bit is recorded as 0
if there is a hit entry, otherwise it is recorded as 1.
When executing the TLBRD instruction, the E bit read from the
TLB table entry is inverted and recorded here.
When executing the TLBWR instruction, and when
CSR.TI.BRFPC.IsTT.BR=0, the value written to the E bit of the
TLB entry is written after it is inverted. If
CSR.TLBRERA.IsTLBR=1, then the E bit of the TLB entry being
written is always set to 1, regardless of the value of that bit.
135
7.5.2. TLB Entry High-order Bits (TLBEHI)
This register contains the information related to the virtual page number of the high-order bits of the TLB
table entry during ececuting TLB-related instructions. Since the length of the VPPN field contained in the
high-order bits of the TLB table entry is related to the range of valid virtual addresses supported by the
implementation, the definition of the relevant register field is expressed separately.
Table 34. Definition of TLB entry high order bits register in LA64
Bits
Name
Read/Write
Description
R
12:0
0
Read-only constant 0, writing to this field is ignored.
RW
VALEN-
VPPN
When executing the TLBRD instruction, the value of the VPPN field
1:13
read from the TLB table entry is recorded here.
If CSR.TLBRERA.IsTLBR=0, the VPPN value used to query TLB
when executing TLBSRCH instruction and the value of VPPN field
written to TLB table entry when executing TLBWR and TLBFILL
instructions come from here.
When the page invalid exception for load operation, page invalid
exception for store operation, page invalid exception for fetch
operation, page modification exception, page non-readable
exception, page non-executable exception, and page privilege
level ilegal exception are triggered, the [VALEN-1:13] bits of the
virual address that triggered the exception are recorded here.
63:VALEN
Sign_Ext
R
Return a signed extension value of the highest bits of the VPPN
field if read this field and writing to this field is ignored.
Table 35. Definition of TLB entry high order bits register in LA32
Bits
Name
Read/Write
Description
R
12:0
0
Read-only constant 0, writing to this field is ignored.
RW
31:13
VPPN
When executing the TLBRD instruction, the value of the VPPN field
read from the TLB table entry is recorded here.
If CSR.TLBRERA.IsTLBR=0, the VPPN value used to query TLB
when executing TLBSRCH instruction and the value of VPPN field
written to TLB table entry when executing TLBWR and TLBFILL
instructions come from here.
When the page invalid exception for load operation, page invalid
exception for store operation, page invalid exception for fetch
operation, page modification exception, page non-readable
exception, page non-executable exception, and page privilege
level ilegal exception are triggered, the [31:13] bits of the virual
address that triggered the exception are recorded here.
7.5.3. TLB Entry Low-order Bits (TLBELO0, TLBELO1)
TLBELO0 and TLBELO1 registers contain the information related to the physical page number of the low-
order bits of the TLB table entry during executing TLB-related instructions. Since TLB adopts a dual-page
structure, the low-order bits of TLB table entry corresponds to the odd and even physical page table entries,
where the even page information is in TLBELO0 and the odd page information is in TLBELO1. TLBELO0 and
136
TLBELO1 registers have exactly the same format definition, and the definition of each field is in the table.
When CSR.TLBRERA.IsTLBR=0, and when executing the TLBWR and TLBFILL instructions, and the
written values of the G, PFN0, V0, PLV0, MATO, D0, NR0, NX0, RPLV0, PFN1, V1, PLV1, MATl, D1, NR1, NX1,
and RPLV1 fields of the TLB table entry come from TLBELOO and TLBELO1 fields, respectively.
When executing the TLBRD instruction, the above information read from the TLB table entry is written to the
corresponding fields in the TLBELO0 and TLBELO1 registers one by one.
Table 36. Definition of TLB entry low order bits in LA64
Bits
Name
Read/Write
Description
RW
0
V
Valid bit (V) of the page table entry.
RW
1
D
Dirty bit (D) of the page table entry.
3:2
PLV
RW
Privilege LeVel of the page table entry (PLV).
5:4
MAT
RW
Memory Access Type (MAT) of the page table entry.
6
G
RW
Global flag bit (G) of the page table entry.
When executing the TLBFILL and TLBWR instructions, the G bit in
TLBELO0 and TLBELO1 is 1 only if both bits are 1.
The G bit of the page table entry filled into the TLB will be 1 only
when the G bit in both TLBELO0 and TLBELO1 is 1.
When executing the TLBRD instruction, when the G bit of the TLB
table entry read is 1, the G bits in TLBELO0 and TLBELO1 are set
to 1 at the same time.
11:7
0
R
Read-only constant 0, writing to this field is ignored.
RW
PALEN-
PPN
Physical Page Number (PPN) of the page table.
1:12
R
60:PALEN
0
Read-only constant 0, writing to this field is ignored.
61
NR
RW
Non-Readable bit (NR) of the page table entry.
62
NX
RW
Non-eXecutable bit (NX) of the page table entry.
63
RPLV
RW
Restricted Privilege LeVel enable (RPLV) of the page table. When
RPLV=0, the page table entry can be accessed by any program
whose privilege level is not lower than PLV; when RPLV=1, the
page table entry can only be accessed by programs whose
privilege level is equal to PLV.
Table 37. Definition of TLB entry low order bits in LA32
Bits
Name
Read/Write
Description
0
V
RW
Valid bit (V) of the page table entry.
1
D
RW
Dirty bit (D) of the page table entry.
3:2
PLV
RW
Privilege LeVel (PLV) of the page table entry.
137
Bits
Name
Read/Write
Description
5:4
MAT
RW
Memory Access Type (MAT) of the page table entry.
6
G
G
Global flag bit (G) of the page table entry.
When executing the TLBFILL and TLBWR instructions, the G bit in
TLBELO0 and TLBELO1 is 1 only if both bits are 1.
The G bit of the page table entry filled into the TLB will be 1 only
when the G bit in both TLBELO0 and TLBELO1 is 1.
When executing the TLBRD instruction, when the G bit of the TLB
table entry read is 1, the G bits in TLBELO0 and TLBELO1 are set
to 1 at the same time.
7
0
R
Read-only constant 0, writing to this field is ignored.
RW
31:8
PPN
Physical Page Number (PPN) of the page table.
7.5.4. Address Space Identifier (ASID)
This register contains the Address Space IDentifier (ASID) information for access operations and TLB-
related instructions. The length of the ASID may increase further as the architecture specification evolves,
and this information is given directly to facilitate software to specify the length of the ASID.
Table 38. Definition of address space identifier register
Bits
Name
Read/Write
Description
RW
The address space identifier corresponding to the currently
9:0
ASID
executing program.
It is used as the ASID key value information for querying the TLB
when fetching instructions and executing the load/store
instructions.
When executing the TLBSRCH, TLBCLR and INVTLB instructions,
it is used as the ASID key value information for querying the TLB.
When executing the TLBWR or TLBFILL instructions, the value
written to the ASID field of the TLB table entry is derived from this.
The contents of the ASID field read from the TLB table entry
when executing the TLBRD instruction are recorded here.
15:0
0
R
Read-only constant 0, writing to this field is ignored.
R
23:16
ASIDBITS
The length of the ASID field. It is directly equal to the value of this
field.
R0
31:24
0
Reserved field. Return 0 if read this field and software is not
allowed to change its value.
7.5.5. Page Global Directory Base Address for Lower Half Address Space (PGDL)
This register is used to configure the base address of the global directory for the lower half address space.
138
It is required that the base address of the global directory must be aligned to a 4KB bound address.
This register also contains the information related to the PS and P fields in the TLB table entry when
executing the TLB-related instructions.
Table 39. Definition of page global directory base address for lower half address space register
Bits
Name
Read/Write
Description
11:0
0
R
Read-only constant 0, writing to this field is ignored.
GRLEN-
Base
RW
The base address of the global directory in the lower half address
1:12
space. By lower half address space, it means that the [VALEN-1]
bit of the virtual address is equal to 0.
7.5.6. Page Global Directory Base Address for Higher Half Address Space (PGDH)
This register is used to configure the base address of the global directory for the higher half address space.
The base address of the global directory must be aligned to the 4KB bound address, so the lowest 12 bits
of this register are not configurable by software and are read-only constant 0.
Table 40. Definition of page global directory base address for higher half address space register
Bits
Name
Read/Write
Description
11:0
0
R
Read-only constant 0, writing to this field is ignored.
RW
The base address of the global directory in the high half address
GRLEN-
Base
1:12
space. By higher half address space, it means that the [VALEN-
1] bit of the virtual address is equal to 1.
7.5.7. Page Global Directory Base Address (PGD)
This register is a read-only register, whose content is the global directory base address information
corresponding to the bad virtual address in the current context.
Table 41. Definition of page global directory base address register
Bits
Name
Read/Write
Description
R
11:0
0
Read-only constant 0, writing to this field is ignored.
R
If the highest bit of the bad virtual address in the current context
GRLEN_1:1
Base
is 0, the return value of reading is equal to the Base field of
2
CSR.PGDL; otherwise, the read return value is equal to the Base
field of CSR.PGDH.
When CSR.TLBRERA.IsTLBR=0, the bad virtual address
information in the current context is located in CSR.BADV;
otherwise, the bad virtual address information is located in
CSR.TLBRBADV.
7.5.8. Page Walk Controller for Lower Half Address Space (PWCL)
The information in this register and the CSR.PWCH register together define the page table structure used in
the operating system. This information will be used to instruct software or hardware to perform page table
walking. See Multi-level Page Table Structure Supported by page walking for an illustration of the page
table structure and walking process.
139
PWCL is implemented in LA32 only, for which the PWCL register must contain all the information needed to
describe the page table structure, resulting in the last page table and the lowest two levels of the directory
starting at no more than 32 bits, a restriction that still exists in LA64.
Table 42. Definition of page walk controller for lower half address space register
Bits
Name
Read/Write
Description
RW
The start address of the last page table.
4:0
PTbase
9:5
PTwidth
RW
The number of index bits of the last level page table.
RW
The starting address of the lowest level directory.
14:10
Dirl_base
RW
19:15
Dirl_widt
The number of index bits of the lowest level directory. 0 means
h
there is no such level.
RW
The starting address of the next lower level directory.
24:20
Dir2_base
RW
29:25
Dir2_widt
The number of index bits of the next lowest level directory. 0
h
means there is no such level.
RW
31:30
PTEWidth
The length of each page table entry in the memory. 0 - 64 bit; 1 -
128 bit; 2 - 192 bit; 3 - 256 bit.
7.5.9. Page Walk Controller for Higher Half Address Space (PWCH)
This register and the information in the CSR.PWCL register together define the page table structure used in
the operating system. This information will be used to instruct software or hardware to perform page table
walking. See Multi-level Page Table Structure Supported by page walking for an illustration of the page
table structure and walking process.
This register is only defined in LA64.
Table 43. Definition of page walk controller for higher half address space register
Bits
Name
Read/Write
Description
RW
The starting address of the next higher level directory.
5:0
Dir3_base
RW
11:6
Dir3_widt
The number of index bits of the next higher level directory. 0
h
means there is no such level.
RW
The starting address of the highest level directory.
17:12
Dir4_base
RW
23:18
Dir4_widt
The number of index bits of the highest level directory. 0 means
h
there is no such level.
R0
31:24
0
Reserved field. Return 0 if read this field, and the software does
not allow to change its value.
7.5.10. STLB Page Size (STLBPS)
This register is used to configure the size of the page in the STLB.
Table 44. Definition of STLB page size register
Bits
Name
Read/Write
Description
5:0
PS
RW
The STLB is a power of 2 of the page size. For example, if the
page size is 16KB, then PS=0xE.
140
Bits
Name
Read/Write
Description
31:6
0
R0
Reserved field. Return 0 if read this field and software is not
allowed to change its value.
7.5.11. TLB Refill Exception Entry Base Address (TLBRENTRY)
This register is used to configure the entry base address of the TLB refill exception. Since the processor
core will enter direct address translation mode after the TLB refill exception is triggered, the entry base
address filled here should be a physical address.
Table 45. Definition of TLB refill exception entry base address register in LA64
Bits
Name
Read/Write
Description
R
11:0
0
Read-only constant 0, writing to this field is ignored.
RW
PALEN-
PPN
The [PALEN-1:12] bits of the entry base address of the TLB
1:12
refill exception entry base address. The address filled in here by
the system software should be the physical address.
R
63:PALEN
0
Read-only constant 0, writing to this field is ignored.
Table 46. Definition of TLB refill exception entry base address register in LA32
Bits
Name
Read/Write
Description
R
11:0
0
Read-only constant 0, writing to this field is ignored.
31:12
PPN
RW
The [31:12] bits of the entry base address of the TLB refill
exception entry base address. The address filled in here by the
system software should be the physical address.
7.5.12. TLB Refill Exception Bad Virtual Address (TLBRBADV)
This register is used to record the bad virtual address that triggered the TLB refill exception.
Table 47. Definition of TLB refill exception bad virtual address register
Bits
Name
Read/Write
Description
GRLEN-1:0
VAddr
RW
When the TLB refill exception is triggered, the hardware records
the bad virtual address here. For LA64, in this case, if the privilege
level that triggered the exception is in 32-bit address mode, then
the high 32 bits of the recorded virtual address will be set to 0.
7.5.13. TLB Refill Exception Return Address (TLBRERA)
This register is used to record the PC of the instruction that triggered the TLB refill exception. In addition,
this register contains flag bits to identify the current exception as a TLB refill exception.
Table 48. Definition of TLB refill exception program counter register
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