Intel 64 and IA-32 Architectures. Software Developer’s Manual (2026) - page 25
VPMOVZXBD __m512i _mm512_mask_cvtepu8_epi32(__m512i a, __mmask16 k, __m128i b);
VPMOVZXBD __m512i _mm512_maskz_cvtepu8_epi32( __mmask16 k, __m128i b);
VPMOVZXBQ __m512i _mm512_cvtepu8_epi64(__m128i a);
VPMOVZXBQ __m512i _mm512_mask_cvtepu8_epi64(__m512i a, __mmask8 k, __m128i b);
VPMOVZXBQ __m512i _mm512_maskz_cvtepu8_epi64( __mmask8 k, __m128i a);
VPMOVZXDQ __m512i _mm512_cvtepu32_epi64(__m256i a);
VPMOVZXDQ __m512i _mm512_mask_cvtepu32_epi64(__m512i a, __mmask8 k, __m256i b);
VPMOVZXDQ __m512i _mm512_maskz_cvtepu32_epi64( __mmask8 k, __m256i a);
VPMOVZXWD __m512i _mm512_cvtepu16_epi32(__m128i a);
VPMOVZXWD __m512i _mm512_mask_cvtepu16_epi32(__m512i a, __mmask16 k, __m128i b);
VPMOVZXWD __m512i _mm512_maskz_cvtepu16_epi32(__mmask16 k, __m128i a);
VPMOVZXWQ __m512i _mm512_cvtepu16_epi64(__m256i a);
VPMOVZXWQ __m512i _mm512_mask_cvtepu16_epi64(__m512i a, __mmask8 k, __m256i b);
VPMOVZXWQ __m512i _mm512_maskz_cvtepu16_epi64( __mmask8 k, __m256i a);
VPMOVZXBW __m256i _mm256_cvtepu8_epi16(__m256i a);
VPMOVZXBW __m256i _mm256_mask_cvtepu8_epi16(__m256i a, __mmask16 k, __m128i b);
VPMOVZXBW __m256i _mm256_maskz_cvtepu8_epi16( __mmask16 k, __m128i b);
VPMOVZXBD __m256i _mm256_cvtepu8_epi32(__m128i a);
VPMOVZXBD __m256i _mm256_mask_cvtepu8_epi32(__m256i a, __mmask8 k, __m128i b);
VPMOVZXBD __m256i _mm256_maskz_cvtepu8_epi32( __mmask8 k, __m128i b);
VPMOVZXBQ __m256i _mm256_cvtepu8_epi64(__m128i a);
VPMOVZXBQ __m256i _mm256_mask_cvtepu8_epi64(__m256i a, __mmask8 k, __m128i b);
VPMOVZXBQ __m256i _mm256_maskz_cvtepu8_epi64( __mmask8 k, __m128i a);
VPMOVZXDQ __m256i _mm256_cvtepu32_epi64(__m128i a);
VPMOVZXDQ __m256i _mm256_mask_cvtepu32_epi64(__m256i a, __mmask8 k, __m128i b);
VPMOVZXDQ __m256i _mm256_maskz_cvtepu32_epi64( __mmask8 k, __m128i a);
VPMOVZXWD __m256i _mm256_cvtepu16_epi32(__m128i a);
VPMOVZXWD __m256i _mm256_mask_cvtepu16_epi32(__m256i a, __mmask16 k, __m128i b);
VPMOVZXWD __m256i _mm256_maskz_cvtepu16_epi32(__mmask16 k, __m128i a);
VPMOVZXWQ __m256i _mm256_cvtepu16_epi64(__m128i a);
VPMOVZXWQ __m256i _mm256_mask_cvtepu16_epi64(__m256i a, __mmask8 k, __m128i b);
VPMOVZXWQ __m256i _mm256_maskz_cvtepu16_epi64( __mmask8 k, __m128i a);
VPMOVZXBW __m128i _mm_mask_cvtepu8_epi16(__m128i a, __mmask8 k, __m128i b);
VPMOVZXBW __m128i _mm_maskz_cvtepu8_epi16( __mmask8 k, __m128i b);
VPMOVZXBD __m128i _mm_mask_cvtepu8_epi32(__m128i a, __mmask8 k, __m128i b);
VPMOVZXBD __m128i _mm_maskz_cvtepu8_epi32( __mmask8 k, __m128i b);
VPMOVZXBQ __m128i _mm_mask_cvtepu8_epi64(__m128i a, __mmask8 k, __m128i b);
VPMOVZXBQ __m128i _mm_maskz_cvtepu8_epi64( __mmask8 k, __m128i a);
VPMOVZXDQ __m128i _mm_mask_cvtepu32_epi64(__m128i a, __mmask8 k, __m128i b);
VPMOVZXDQ __m128i _mm_maskz_cvtepu32_epi64( __mmask8 k, __m128i a);
VPMOVZXWD __m128i _mm_mask_cvtepu16_epi32(__m128i a, __mmask16 k, __m128i b);
VPMOVZXWD __m128i _mm_maskz_cvtepu16_epi32(__mmask8 k, __m128i a);
VPMOVZXWQ __m128i _mm_mask_cvtepu16_epi64(__m128i a, __mmask8 k, __m128i b);
VPMOVZXWQ __m128i _mm_maskz_cvtepu16_epi64( __mmask8 k, __m128i a);
PMOVZXBW __m128i _mm_ cvtepu8_epi16 ( __m128i a);
PMOVZXBD __m128i _mm_ cvtepu8_epi32 ( __m128i a);
PMOVZXBQ __m128i _mm_ cvtepu8_epi64 ( __m128i a);
PMOVZXWD __m128i _mm_ cvtepu16_epi32 ( __m128i a);
PMOVZXWQ __m128i _mm_ cvtepu16_epi64 ( __m128i a);
PMOVZXDQ __m128i _mm_ cvtepu32_epi64 ( __m128i a);
SIMD Floating-Point Exceptions
None.
PMOVZX-Packed Move With Zero Extend
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4-370
Other Exceptions
Non-EVEX-encoded instruction, see Table 2-22, “Type 5 Class Exception Conditions.”
EVEX-encoded instruction, see Table 2-53, “Type E5 Class Exception Conditions.”
Additionally:
#UD
If VEX.vvvv != 1111B, or EVEX.vvvv != 1111B.
PMOVZX-Packed Move With Zero Extend
Vol. 2B
4-371
PMULDQ-Multiply Packed Doubleword Integers
Opcode/
Op /
64/32 bit
CPUID Feature
Description
Instruction
En
Mode
Flag
Support
66 0F 38 28 /r
A
V/V
SSE4_1
Multiply packed signed doubleword integers in xmm1 by
PMULDQ xmm1, xmm2/m128
packed signed doubleword integers in xmm2/m128, and
store the quadword results in xmm1.
VEX.128.66.0F38.WIG 28 /r
B
V/V
AVX
Multiply packed signed doubleword integers in xmm2 by
VPMULDQ xmm1, xmm2,
packed signed doubleword integers in xmm3/m128, and
xmm3/m128
store the quadword results in xmm1.
VEX.256.66.0F38.WIG 28 /r
B
V/V
AVX2
Multiply packed signed doubleword integers in ymm2 by
VPMULDQ ymm1, ymm2,
packed signed doubleword integers in ymm3/m256, and
ymm3/m256
store the quadword results in ymm1.
EVEX.128.66.0F38.W1 28 /r
C
V/V
(AVX512VL AND
Multiply packed signed doubleword integers in xmm2 by
VPMULDQ xmm1 {k1}{z}, xmm2,
AVX512F) OR
packed signed doubleword integers in
xmm3/m128/m64bcst
AVX10.1
xmm3/m128/m64bcst, and store the quadword results
in xmm1 using writemask k1.
EVEX.256.66.0F38.W1 28 /r
C
V/V
(AVX512VL AND
Multiply packed signed doubleword integers in ymm2 by
VPMULDQ ymm1 {k1}{z}, ymm2,
AVX512F) OR
packed signed doubleword integers in
ymm3/m256/m64bcst
AVX10.1
ymm3/m256/m64bcst, and store the quadword results
in ymm1 using writemask k1.
EVEX.512.66.0F38.W1 28 /r
C
V/V
AVX512F
Multiply packed signed doubleword integers in zmm2 by
VPMULDQ zmm1 {k1}{z}, zmm2,
OR AVX10.1
packed signed doubleword integers in
zmm3/m512/m64bcst
zmm3/m512/m64bcst, and store the quadword results
in zmm1 using writemask k1.
Instruction Operand Encoding
Op/En
Tuple Type
Operand 1
Operand 2
Operand 3
Operand 4
A
N/A
ModRM:reg (r, w)
ModRM:r/m (r)
N/A
N/A
B
N/A
ModRM:reg (w)
VEX.vvvv (r)
ModRM:r/m (r)
N/A
C
Full
ModRM:reg (w)
EVEX.vvvv (r)
ModRM:r/m (r)
N/A
Description
Multiplies packed signed doubleword integers in the even-numbered (zero-based reference) elements of the first
source operand with the packed signed doubleword integers in the corresponding elements of the second source
operand and stores packed signed quadword results in the destination operand.
128-bit Legacy SSE version: The input signed doubleword integers are taken from the even-numbered elements of
the source operands, i.e., the first (low) and third doubleword element. For 128-bit memory operands, 128 bits are
fetched from memory, but only the first and third doublewords are used in the computation. The first source
operand and the destination XMM operand is the same. The second source operand can be an XMM register or 128-
bit memory location. Bits (MAXVL-1:128) of the corresponding destination register remain unchanged.
VEX.128 encoded version: The input signed doubleword integers are taken from the even-numbered elements of
the source operands, i.e., the first (low) and third doubleword element. For 128-bit memory operands, 128 bits are
fetched from memory, but only the first and third doublewords are used in the computation.The first source
operand and the destination operand are XMM registers. The second source operand can be an XMM register or
128-bit memory location. Bits (MAXVL-1:128) of the corresponding destination register are zeroed.
VEX.256 encoded version: The input signed doubleword integers are taken from the even-numbered elements of
the source operands, i.e., the first, 3rd, 5th, 7th doubleword element. For 256-bit memory operands, 256 bits are
fetched from memory, but only the four even-numbered doublewords are used in the computation. The first source
operand and the destination operand are YMM registers. The second source operand can be a YMM register or 256-
bit memory location. Bits (MAXVL-1:256) of the corresponding destination ZMM register are zeroed.
PMULDQ-Multiply Packed Doubleword Integers
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EVEX encoded version: The input signed doubleword integers are taken from the even-numbered elements of the
source operands. The first source operand is a ZMM/YMM/XMM registers. The second source operand can be an
ZMM/YMM/XMM register, a 512/256/128-bit memory location or a 512/256/128-bit vector broadcasted from a 64-
bit memory location. The destination is a ZMM/YMM/XMM register, and updated according to the writemask at 64-
bit granularity.
Operation
VPMULDQ (EVEX Encoded Versions)
(KL, VL) = (2, 128), (4, 256), (8, 512)
FOR j := 0 TO KL-1
i := j * 64
IF k1[j] OR *no writemask*
THEN
IF (EVEX.b = 1) AND (SRC2 *is memory*)
THEN DEST[i+63:i] := SignExtend64( SRC1[i+31:i]) * SignExtend64( SRC2[31:0])
ELSE DEST[i+63:i] := SignExtend64( SRC1[i+31:i]) * SignExtend64( SRC2[i+31:i])
FI;
ELSE
IF *merging-masking*
; merging-masking
THEN *DEST[i+63:i] remains unchanged*
ELSE *zeroing-masking*
; zeroing-masking
DEST[i+63:i] := 0
FI
FI;
ENDFOR
DEST[MAXVL-1:VL] := 0
VPMULDQ (VEX.256 Encoded Version)
DEST[63:0] := SignExtend64( SRC1[31:0]) * SignExtend64( SRC2[31:0])
DEST[127:64] := SignExtend64( SRC1[95:64]) * SignExtend64( SRC2[95:64])
DEST[191:128] := SignExtend64( SRC1[159:128]) * SignExtend64( SRC2[159:128])
DEST[255:192] := SignExtend64( SRC1[223:192]) * SignExtend64( SRC2[223:192])
DEST[MAXVL-1:256] := 0
VPMULDQ (VEX.128 Encoded Version)
DEST[63:0] := SignExtend64( SRC1[31:0]) * SignExtend64( SRC2[31:0])
DEST[127:64] := SignExtend64( SRC1[95:64]) * SignExtend64( SRC2[95:64])
DEST[MAXVL-1:128] := 0
PMULDQ (128-bit Legacy SSE Version)
DEST[63:0] := SignExtend64( DEST[31:0]) * SignExtend64( SRC[31:0])
DEST[127:64] := SignExtend64( DEST[95:64]) * SignExtend64( SRC[95:64])
DEST[MAXVL-1:128] (Unmodified)
PMULDQ-Multiply Packed Doubleword Integers
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Intel C/C++ Compiler Intrinsic Equivalent
VPMULDQ __m512i _mm512_mul_epi32(__m512i a, __m512i b);
VPMULDQ __m512i _mm512_mask_mul_epi32(__m512i s, __mmask8 k, __m512i a, __m512i b);
VPMULDQ __m512i _mm512_maskz_mul_epi32( __mmask8 k, __m512i a, __m512i b);
VPMULDQ __m256i _mm256_mask_mul_epi32(__m256i s, __mmask8 k, __m256i a, __m256i b);
VPMULDQ __m256i _mm256_mask_mul_epi32( __mmask8 k, __m256i a, __m256i b);
VPMULDQ __m128i _mm_mask_mul_epi32(__m128i s, __mmask8 k, __m128i a, __m128i b);
VPMULDQ __m128i _mm_mask_mul_epi32( __mmask8 k, __m128i a, __m128i b);
(V)PMULDQ __m128i _mm_mul_epi32( __m128i a, __m128i b);
VPMULDQ __m256i _mm256_mul_epi32( __m256i a, __m256i b);
SIMD Floating-Point Exceptions
None.
Other Exceptions
Non-EVEX-encoded instruction, see Table 2-21, “Type 4 Class Exception Conditions.”
EVEX-encoded instruction, see Table 2-51, “Type E4 Class Exception Conditions.”
PMULDQ-Multiply Packed Doubleword Integers
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4-374
PMULHRSW-Packed Multiply High With Round and Scale
Opcode/
Op/
64/32 bit
CPUID Feature
Description
Instruction
En
Mode
Flag
Support
NP 0F 38 0B /r1
A
V/V
SSSE3
Multiply 16-bit signed words, scale and
round signed doublewords, pack high 16
PMULHRSW mm1, mm2/m64
bits to mm1.
66 0F 38 0B /r
A
V/V
SSSE3
Multiply 16-bit signed words, scale and
round signed doublewords, pack high 16
PMULHRSW xmm1, xmm2/m128
bits to xmm1.
VEX.128.66.0F38.WIG 0B /r
B
V/V
AVX
Multiply 16-bit signed words, scale and
round signed doublewords, pack high 16
VPMULHRSW xmm1, xmm2, xmm3/m128
bits to xmm1.
VEX.256.66.0F38.WIG 0B /r
B
V/V
AVX2
Multiply 16-bit signed words, scale and
round signed doublewords, pack high 16
VPMULHRSW ymm1, ymm2, ymm3/m256
bits to ymm1.
EVEX.128.66.0F38.WIG 0B /r
C
V/V
(AVX512VL AND
Multiply 16-bit signed words, scale and
VPMULHRSW xmm1 {k1}{z}, xmm2, xmm3/m128
AVX512BW) OR
round signed doublewords, pack high 16
AVX10.1
bits to xmm1 under writemask k1.
EVEX.256.66.0F38.WIG 0B /r
C
V/V
(AVX512VL AND
Multiply 16-bit signed words, scale and
VPMULHRSW ymm1 {k1}{z}, ymm2, ymm3/m256
AVX512BW) OR
round signed doublewords, pack high 16
AVX10.1
bits to ymm1 under writemask k1.
EVEX.512.66.0F38.WIG 0B /r
C
V/V
AVX512BW
Multiply 16-bit signed words, scale and
VPMULHRSW zmm1 {k1}{z}, zmm2, zmm3/m512
OR AVX10.1
round signed doublewords, pack high 16
bits to zmm1 under writemask k1.
NOTES:
1. See note in Section 2.5, “Intel® AVX and Intel® SSE Instruction Exception Classification,” in the Intel® 64 and IA-32 Architectures Soft-
ware Developer’s Manual, Volume 2A, and Section 25.25.3, “Exception Conditions of Legacy SIMD Instructions Operating on MMX Reg-
isters,” in the Intel® 64 and IA-32 Architectures Software Developer’s Manual, Volume 3B.
Instruction Operand Encoding
Op/En
Tuple Type
Operand 1
Operand 2
Operand 3
Operand 4
A
N/A
ModRM:reg (r, w)
ModRM:r/m (r)
N/A
N/A
B
N/A
ModRM:reg (w)
VEX.vvvv (r)
ModRM:r/m (r)
N/A
C
Full Mem
ModRM:reg (w)
EVEX.vvvv (r)
ModRM:r/m (r)
N/A
Description
PMULHRSW multiplies vertically each signed 16-bit integer from the destination operand (first operand) with the
corresponding signed 16-bit integer of the source operand (second operand), producing intermediate, signed 32-
bit integers. Each intermediate 32-bit integer is truncated to the 18 most significant bits. Rounding is always
performed by adding 1 to the least significant bit of the 18-bit intermediate result. The final result is obtained by
selecting the 16 bits immediately to the right of the most significant bit of each 18-bit intermediate result and
packed to the destination operand.
When the source operand is a 128-bit memory operand, the operand must be aligned on a 16-byte boundary or a
general-protection exception (#GP) will be generated.
In 64-bit mode and not encoded with VEX/EVEX, use the REX prefix to access XMM8-XMM15 registers.
Legacy SSE version 64-bit operand: Both operands can be MMX registers. The second source operand is an MMX
register or a 64-bit memory location.
PMULHRSW-Packed Multiply High With Round and Scale
Vol. 2B
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128-bit Legacy SSE version: The first source and destination operands are XMM registers. The second source
operand is an XMM register or a 128-bit memory location. Bits (MAXVL-1:128) of the corresponding YMM destina-
tion register remain unchanged.
VEX.128 encoded version: The first source and destination operands are XMM registers. The second source
operand is an XMM register or a 128-bit memory location. Bits (MAXVL-1:128) of the destination YMM register are
zeroed.
VEX.256 encoded version: The second source operand can be an YMM register or a 256-bit memory location. The
first source and destination operands are YMM registers.
EVEX encoded versions: The first source operand is a ZMM/YMM/XMM register. The second source operand can be
a ZMM/YMM/XMM register, a 512/256/128-bit memory location. The destination operand is a ZMM/YMM/XMM
register conditionally updated with writemask k1.
Operation
PMULHRSW (With 64-bit Operands)
temp0[31:0] = INT32 ((DEST[15:0] * SRC[15:0]) >>14) + 1;
temp1[31:0] = INT32 ((DEST[31:16] * SRC[31:16]) >>14) + 1;
temp2[31:0] = INT32 ((DEST[47:32] * SRC[47:32]) >> 14) + 1;
temp3[31:0] = INT32 ((DEST[63:48] * SRc[63:48]) >> 14) + 1;
DEST[15:0] = temp0[16:1];
DEST[31:16] = temp1[16:1];
DEST[47:32] = temp2[16:1];
DEST[63:48] = temp3[16:1];
PMULHRSW (With 128-bit Operands)
temp0[31:0] = INT32 ((DEST[15:0] * SRC[15:0]) >>14) + 1;
temp1[31:0] = INT32 ((DEST[31:16] * SRC[31:16]) >>14) + 1;
temp2[31:0] = INT32 ((DEST[47:32] * SRC[47:32]) >>14) + 1;
temp3[31:0] = INT32 ((DEST[63:48] * SRC[63:48]) >>14) + 1;
temp4[31:0] = INT32 ((DEST[79:64] * SRC[79:64]) >>14) + 1;
temp5[31:0] = INT32 ((DEST[95:80] * SRC[95:80]) >>14) + 1;
temp6[31:0] = INT32 ((DEST[111:96] * SRC[111:96]) >>14) + 1;
temp7[31:0] = INT32 ((DEST[127:112] * SRC[127:112) >>14) + 1;
DEST[15:0] = temp0[16:1];
DEST[31:16] = temp1[16:1];
DEST[47:32] = temp2[16:1];
DEST[63:48] = temp3[16:1];
DEST[79:64] = temp4[16:1];
DEST[95:80] = temp5[16:1];
DEST[111:96] = temp6[16:1];
DEST[127:112] = temp7[16:1];
VPMULHRSW (VEX.128 Encoded Version)
temp0[31:0] := INT32 ((SRC1[15:0] * SRC2[15:0]) >>14) + 1
temp1[31:0] := INT32 ((SRC1[31:16] * SRC2[31:16]) >>14) + 1
temp2[31:0] := INT32 ((SRC1[47:32] * SRC2[47:32]) >>14) + 1
temp3[31:0] := INT32 ((SRC1[63:48] * SRC2[63:48]) >>14) + 1
temp4[31:0] := INT32 ((SRC1[79:64] * SRC2[79:64]) >>14) + 1
temp5[31:0] := INT32 ((SRC1[95:80] * SRC2[95:80]) >>14) + 1
temp6[31:0] := INT32 ((SRC1[111:96] * SRC2[111:96]) >>14) + 1
temp7[31:0] := INT32 ((SRC1[127:112] * SRC2[127:112) >>14) + 1
DEST[15:0] := temp0[16:1]
DEST[31:16] := temp1[16:1]
DEST[47:32] := temp2[16:1]
PMULHRSW-Packed Multiply High With Round and Scale
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DEST[63:48] := temp3[16:1]
DEST[79:64] := temp4[16:1]
DEST[95:80] := temp5[16:1]
DEST[111:96] := temp6[16:1]
DEST[127:112] := temp7[16:1]
DEST[MAXVL-1:128] := 0
VPMULHRSW (VEX.256 Encoded Version)
temp0[31:0] := INT32 ((SRC1[15:0] * SRC2[15:0]) >>14) + 1
temp1[31:0] := INT32 ((SRC1[31:16] * SRC2[31:16]) >>14) + 1
temp2[31:0] := INT32 ((SRC1[47:32] * SRC2[47:32]) >>14) + 1
temp3[31:0] := INT32 ((SRC1[63:48] * SRC2[63:48]) >>14) + 1
temp4[31:0] := INT32 ((SRC1[79:64] * SRC2[79:64]) >>14) + 1
temp5[31:0] := INT32 ((SRC1[95:80] * SRC2[95:80]) >>14) + 1
temp6[31:0] := INT32 ((SRC1[111:96] * SRC2[111:96]) >>14) + 1
temp7[31:0] := INT32 ((SRC1[127:112] * SRC2[127:112) >>14) + 1
temp8[31:0] := INT32 ((SRC1[143:128] * SRC2[143:128]) >>14) + 1
temp9[31:0] := INT32 ((SRC1[159:144] * SRC2[159:144]) >>14) + 1
temp10[31:0] := INT32 ((SRC1[75:160] * SRC2[175:160]) >>14) + 1
temp11[31:0] := INT32 ((SRC1[191:176] * SRC2[191:176]) >>14) + 1
temp12[31:0] := INT32 ((SRC1[207:192] * SRC2[207:192]) >>14) + 1
temp13[31:0] := INT32 ((SRC1[223:208] * SRC2[223:208]) >>14) + 1
temp14[31:0] := INT32 ((SRC1[239:224] * SRC2[239:224]) >>14) + 1
temp15[31:0] := INT32 ((SRC1[255:240] * SRC2[255:240) >>14) + 1
DEST[15:0] := temp0[16:1]
DEST[31:16] := temp1[16:1]
DEST[47:32] := temp2[16:1]
DEST[63:48] := temp3[16:1]
DEST[79:64] := temp4[16:1]
DEST[95:80] := temp5[16:1]
DEST[111:96] := temp6[16:1]
DEST[127:112] := temp7[16:1]
DEST[143:128] := temp8[16:1]
DEST[159:144] := temp9[16:1]
DEST[175:160] := temp10[16:1]
DEST[191:176] := temp11[16:1]
DEST[207:192] := temp12[16:1]
DEST[223:208] := temp13[16:1]
DEST[239:224] := temp14[16:1]
DEST[255:240] := temp15[16:1]
DEST[MAXVL-1:256] := 0
PMULHRSW-Packed Multiply High With Round and Scale
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VPMULHRSW (EVEX Encoded Version)
(KL, VL) = (8, 128), (16, 256), (32, 512)
FOR j := 0 TO KL-1
i := j * 16
IF k1[j] OR *no writemask*
THEN
temp[31:0] := ((SRC1[i+15:i] * SRC2[i+15:i]) >>14) + 1
DEST[i+15:i] := tmp[16:1]
ELSE
IF *merging-masking*
; merging-masking
THEN *DEST[i+15:i] remains unchanged*
ELSE *zeroing-masking*
; zeroing-masking
DEST[i+15:i] := 0
FI
FI;
ENDFOR
DEST[MAXVL-1:VL] := 0
Intel C/C++ Compiler Intrinsic Equivalents
VPMULHRSW __m512i _mm512_mulhrs_epi16(__m512i a, __m512i b);
VPMULHRSW __m512i _mm512_mask_mulhrs_epi16(__m512i s, __mmask32 k, __m512i a, __m512i b);
VPMULHRSW __m512i _mm512_maskz_mulhrs_epi16( __mmask32 k, __m512i a, __m512i b);
VPMULHRSW __m256i _mm256_mask_mulhrs_epi16(__m256i s, __mmask16 k, __m256i a, __m256i b);
VPMULHRSW __m256i _mm256_maskz_mulhrs_epi16( __mmask16 k, __m256i a, __m256i b);
VPMULHRSW __m128i _mm_mask_mulhrs_epi16(__m128i s, __mmask8 k, __m128i a, __m128i b);
VPMULHRSW __m128i _mm_maskz_mulhrs_epi16( __mmask8 k, __m128i a, __m128i b);
PMULHRSW __m64 _mm_mulhrs_pi16 (__m64 a, __m64 b)
(V)PMULHRSW __m128i _mm_mulhrs_epi16 (__m128i a, __m128i b)
VPMULHRSW __m256i _mm256_mulhrs_epi16 (__m256i a, __m256i b)
SIMD Floating-Point Exceptions
None.
Other Exceptions
Non-EVEX-encoded instruction, see Table 2-21, “Type 4 Class Exception Conditions.”
EVEX-encoded instruction, see Exceptions Type E4.nb in Table 2-51, “Type E4 Class Exception Conditions.”
PMULHRSW-Packed Multiply High With Round and Scale
Vol. 2B
4-378
PMULHUW-Multiply Packed Unsigned Integers and Store High Result
Opcode/
Op/
64/32 bit
CPUID Feature
Description
Instruction
En
Mode
Flag
Support
NP 0F E4 /r1
A
V/V
SSE
Multiply the packed unsigned word integers
in mm1 register and mm2/m64, and store the
PMULHUW mm1, mm2/m64
high 16 bits of the results in mm1.
66 0F E4 /r
A
V/V
SSE2
Multiply the packed unsigned word integers
in xmm1 and xmm2/m128, and store the
PMULHUW xmm1, xmm2/m128
high 16 bits of the results in xmm1.
VEX.128.66.0F.WIG E4 /r
B
V/V
AVX
Multiply the packed unsigned word integers
in xmm2 and xmm3/m128, and store the
VPMULHUW xmm1, xmm2, xmm3/m128
high 16 bits of the results in xmm1.
VEX.256.66.0F.WIG E4 /r
B
V/V
AVX2
Multiply the packed unsigned word integers
in ymm2 and ymm3/m256, and store the
VPMULHUW ymm1, ymm2, ymm3/m256
high 16 bits of the results in ymm1.
EVEX.128.66.0F.WIG E4 /r
C
V/V
(AVX512VL AND
Multiply the packed unsigned word integers
VPMULHUW xmm1 {k1}{z}, xmm2, xmm3/m128
AVX512BW) OR
in xmm2 and xmm3/m128, and store the
AVX10.1
high 16 bits of the results in xmm1 under
writemask k1.
EVEX.256.66.0F.WIG E4 /r
C
V/V
(AVX512VL AND
Multiply the packed unsigned word integers
VPMULHUW ymm1 {k1}{z}, ymm2, ymm3/m256
AVX512BW) OR
in ymm2 and ymm3/m256, and store the
AVX10.1
high 16 bits of the results in ymm1 under
writemask k1.
EVEX.512.66.0F.WIG E4 /r
C
V/V
AVX512BW
Multiply the packed unsigned word integers
VPMULHUW zmm1 {k1}{z}, zmm2, zmm3/m512
OR AVX10.1
in zmm2 and zmm3/m512, and store the
high 16 bits of the results in zmm1 under
writemask k1.
NOTES:
1. See note in Section 2.5, “Intel® AVX and Intel® SSE Instruction Exception Classification,” in the Intel® 64 and IA-32 Architectures Soft-
ware Developer’s Manual, Volume 2A, and Section 25.25.3, “Exception Conditions of Legacy SIMD Instructions Operating on MMX
Registers,” in the Intel® 64 and IA-32 Architectures Software Developer’s Manual, Volume 3B.
Instruction Operand Encoding
Op/En
Tuple Type
Operand 1
Operand 2
Operand 3
Operand 4
A
N/A
ModRM:reg (r, w)
ModRM:r/m (r)
N/A
N/A
B
N/A
ModRM:reg (w)
VEX.vvvv (r)
ModRM:r/m (r)
N/A
C
Full Mem
ModRM:reg (w)
EVEX.vvvv (r)
ModRM:r/m (r)
N/A
Description
Performs a SIMD unsigned multiply of the packed unsigned word integers in the destination operand (first operand)
and the source operand (second operand), and stores the high 16 bits of each 32-bit intermediate results in the
destination operand. (Figure 4-12 shows this operation when using 64-bit operands.)
In 64-bit mode and not encoded with VEX/EVEX, using a REX prefix in the form of REX.R permits this instruction to
access additional registers (XMM8-XMM15).
Legacy SSE version 64-bit operand: The source operand can be an MMX technology register or a 64-bit memory
location. The destination operand is an MMX technology register.
128-bit Legacy SSE version: The first source and destination operands are XMM registers. The second source
operand is an XMM register or a 128-bit memory location. Bits (MAXVL-1:128) of the corresponding YMM destina-
tion register remain unchanged.
PMULHUW-Multiply Packed Unsigned Integers and Store High Result
Vol. 2B
4-379
VEX.128 encoded version: The first source and destination operands are XMM registers. The second source
operand is an XMM register or a 128-bit memory location. Bits (MAXVL-1:128) of the destination YMM register are
zeroed. VEX.L must be 0, otherwise the instruction will #UD.
VEX.256 encoded version: The second source operand can be an YMM register or a 256-bit memory location. The
first source and destination operands are YMM registers.
EVEX encoded versions: The first source operand is a ZMM/YMM/XMM register. The second source operand can be
a ZMM/YMM/XMM register, a 512/256/128-bit memory location. The destination operand is a ZMM/YMM/XMM
register conditionally updated with writemask k1.
SRC
X3
X2
X1
X0
DEST
Y3
Y2
Y1
Y0
TEMP
Z3 = X3 ∗ Y3
Z2 = X2 ∗ Y2
Z1 = X1 ∗ Y1
Z0 = X0 ∗ Y0
DEST
Z3[31:16]
Z2[31:16]
Z1[31:16]
Z0[31:16]
Figure 4-12. PMULHUW and PMULHW Instruction Operation Using 64-bit Operands
Operation
PMULHUW (With 64-bit Operands)
TEMP0[31:0] := DEST[15:0] ∗ SRC[15:0]; (* Unsigned multiplication *)
TEMP1[31:0] := DEST[31:16] ∗ SRC[31:16];
TEMP2[31:0] := DEST[47:32] ∗ SRC[47:32];
TEMP3[31:0] := DEST[63:48] ∗ SRC[63:48];
DEST[15:0] := TEMP0[31:16];
DEST[31:16] := TEMP1[31:16];
DEST[47:32] := TEMP2[31:16];
DEST[63:48] := TEMP3[31:16];
PMULHUW (With 128-bit Operands)
TEMP0[31:0] := DEST[15:0] ∗ SRC[15:0]; (* Unsigned multiplication *)
TEMP1[31:0] := DEST[31:16] ∗ SRC[31:16];
TEMP2[31:0] := DEST[47:32] ∗ SRC[47:32];
TEMP3[31:0] := DEST[63:48] ∗ SRC[63:48];
TEMP4[31:0] := DEST[79:64] ∗ SRC[79:64];
TEMP5[31:0] := DEST[95:80] ∗ SRC[95:80];
TEMP6[31:0] := DEST[111:96] ∗ SRC[111:96];
TEMP7[31:0] := DEST[127:112] ∗ SRC[127:112];
DEST[15:0] := TEMP0[31:16];
DEST[31:16] := TEMP1[31:16];
DEST[47:32] := TEMP2[31:16];
DEST[63:48] := TEMP3[31:16];
DEST[79:64] := TEMP4[31:16];
DEST[95:80] := TEMP5[31:16];
DEST[111:96] := TEMP6[31:16];
DEST[127:112] := TEMP7[31:16];
VPMULHUW (VEX.128 Encoded Version)
PMULHUW-Multiply Packed Unsigned Integers and Store High Result
Vol. 2B
4-380
TEMP0[31:0] := SRC1[15:0] * SRC2[15:0]
TEMP1[31:0] := SRC1[31:16] * SRC2[31:16]
TEMP2[31:0] := SRC1[47:32] * SRC2[47:32]
TEMP3[31:0] := SRC1[63:48] * SRC2[63:48]
TEMP4[31:0] := SRC1[79:64] * SRC2[79:64]
TEMP5[31:0] := SRC1[95:80] * SRC2[95:80]
TEMP6[31:0] := SRC1[111:96] * SRC2[111:96]
TEMP7[31:0] := SRC1[127:112] * SRC2[127:112]
DEST[15:0] := TEMP0[31:16]
DEST[31:16] := TEMP1[31:16]
DEST[47:32] := TEMP2[31:16]
DEST[63:48] := TEMP3[31:16]
DEST[79:64] := TEMP4[31:16]
DEST[95:80] := TEMP5[31:16]
DEST[111:96] := TEMP6[31:16]
DEST[127:112] := TEMP7[31:16]
DEST[MAXVL-1:128] := 0
PMULHUW (VEX.256 Encoded Version)
TEMP0[31:0] := SRC1[15:0] * SRC2[15:0]
TEMP1[31:0] := SRC1[31:16] * SRC2[31:16]
TEMP2[31:0] := SRC1[47:32] * SRC2[47:32]
TEMP3[31:0] := SRC1[63:48] * SRC2[63:48]
TEMP4[31:0] := SRC1[79:64] * SRC2[79:64]
TEMP5[31:0] := SRC1[95:80] * SRC2[95:80]
TEMP6[31:0] := SRC1[111:96] * SRC2[111:96]
TEMP7[31:0] := SRC1[127:112] * SRC2[127:112]
TEMP8[31:0] := SRC1[143:128] * SRC2[143:128]
TEMP9[31:0] := SRC1[159:144] * SRC2[159:144]
TEMP10[31:0] := SRC1[175:160] * SRC2[175:160]
TEMP11[31:0] := SRC1[191:176] * SRC2[191:176]
TEMP12[31:0] := SRC1[207:192] * SRC2[207:192]
TEMP13[31:0] := SRC1[223:208] * SRC2[223:208]
TEMP14[31:0] := SRC1[239:224] * SRC2[239:224]
TEMP15[31:0] := SRC1[255:240] * SRC2[255:240]
DEST[15:0] := TEMP0[31:16]
DEST[31:16] := TEMP1[31:16]
DEST[47:32] := TEMP2[31:16]
DEST[63:48] := TEMP3[31:16]
DEST[79:64] := TEMP4[31:16]
DEST[95:80] := TEMP5[31:16]
DEST[111:96] := TEMP6[31:16]
DEST[127:112] := TEMP7[31:16]
DEST[143:128] := TEMP8[31:16]
DEST[159:144] := TEMP9[31:16]
DEST[175:160] := TEMP10[31:16]
DEST[191:176] := TEMP11[31:16]
DEST[207:192] := TEMP12[31:16]
DEST[223:208] := TEMP13[31:16]
DEST[239:224] := TEMP14[31:16]
DEST[255:240] := TEMP15[31:16]
DEST[MAXVL-1:256] := 0
PMULHUW (EVEX Encoded Versions)
PMULHUW-Multiply Packed Unsigned Integers and Store High Result
Vol. 2B
4-381
(KL, VL) = (8, 128), (16, 256), (32, 512)
FOR j := 0 TO KL-1
i := j * 16
IF k1[j] OR *no writemask*
THEN
temp[31:0] := SRC1[i+15:i] * SRC2[i+15:i]
DEST[i+15:i] := tmp[31:16]
ELSE
IF *merging-masking*
; merging-masking
THEN *DEST[i+15:i] remains unchanged*
ELSE *zeroing-masking*
; zeroing-masking
DEST[i+15:i] := 0
FI
FI;
ENDFOR
DEST[MAXVL-1:VL] := 0
Intel C/C++ Compiler Intrinsic Equivalent
VPMULHUW __m512i _mm512_mulhi_epu16(__m512i a, __m512i b);
VPMULHUW __m512i _mm512_mask_mulhi_epu16(__m512i s, __mmask32 k, __m512i a, __m512i b);
VPMULHUW __m512i _mm512_maskz_mulhi_epu16( __mmask32 k, __m512i a, __m512i b);
VPMULHUW __m256i _mm256_mask_mulhi_epu16(__m256i s, __mmask16 k, __m256i a, __m256i b);
VPMULHUW __m256i _mm256_maskz_mulhi_epu16( __mmask16 k, __m256i a, __m256i b);
VPMULHUW __m128i _mm_mask_mulhi_epu16(__m128i s, __mmask8 k, __m128i a, __m128i b);
VPMULHUW __m128i _mm_maskz_mulhi_epu16( __mmask8 k, __m128i a, __m128i b);
PMULHUW __m64 _mm_mulhi_pu16(__m64 a, __m64 b)
(V)PMULHUW __m128i _mm_mulhi_epu16 ( __m128i a, __m128i b)
VPMULHUW __m256i _mm256_mulhi_epu16 ( __m256i a, __m256i b)
Flags Affected
None.
Numeric Exceptions
None.
Other Exceptions
Non-EVEX-encoded instruction, see Table 2-21, “Type 4 Class Exception Conditions.”
EVEX-encoded instruction, see Exceptions Type E4.nb in Table 2-51, “Type E4 Class Exception Conditions.”
PMULHUW-Multiply Packed Unsigned Integers and Store High Result
Vol. 2B
4-382
PMULHW-Multiply Packed Signed Integers and Store High Result
Opcode/
Op/
64/32 bit
CPUID Feature
Description
Instruction
En
Mode
Flag
Support
NP 0F E5 /r1
A
V/V
MMX
Multiply the packed signed word integers in mm1
register and mm2/m64, and store the high 16
PMULHW mm, mm/m64
bits of the results in mm1.
66 0F E5 /r
A
V/V
SSE2
Multiply the packed signed word integers in
xmm1 and xmm2/m128, and store the high 16
PMULHW xmm1, xmm2/m128
bits of the results in xmm1.
VEX.128.66.0F.WIG E5 /r
B
V/V
AVX
Multiply the packed signed word integers in
xmm2 and xmm3/m128, and store the high 16
VPMULHW xmm1, xmm2, xmm3/m128
bits of the results in xmm1.
VEX.256.66.0F.WIG E5 /r
B
V/V
AVX2
Multiply the packed signed word integers in
ymm2 and ymm3/m256, and store the high 16
VPMULHW ymm1, ymm2, ymm3/m256
bits of the results in ymm1.
EVEX.128.66.0F.WIG E5 /r
C
V/V
(AVX512VL AND
Multiply the packed signed word integers in
VPMULHW xmm1 {k1}{z}, xmm2,
AVX512BW) OR
xmm2 and xmm3/m128, and store the high 16
xmm3/m128
AVX10.1
bits of the results in xmm1 under writemask k1.
EVEX.256.66.0F.WIG E5 /r
C
V/V
(AVX512VL AND
Multiply the packed signed word integers in
VPMULHW ymm1 {k1}{z}, ymm2,
AVX512BW) OR
ymm2 and ymm3/m256, and store the high 16
ymm3/m256
AVX10.1
bits of the results in ymm1 under writemask k1.
EVEX.512.66.0F.WIG E5 /r
C
V/V
AVX512BW
Multiply the packed signed word integers in
VPMULHW zmm1 {k1}{z}, zmm2,
OR AVX10.1
zmm2 and zmm3/m512, and store the high 16
zmm3/m512
bits of the results in zmm1 under writemask k1.
NOTES:
1. See note in Section 2.5, “Intel® AVX and Intel® SSE Instruction Exception Classification,” in the Intel® 64 and IA-32 Architectures Soft-
ware Developer’s Manual, Volume 2A, and Section 25.25.3, “Exception Conditions of Legacy SIMD Instructions Operating on MMX Reg-
isters,” in the Intel® 64 and IA-32 Architectures Software Developer’s Manual, Volume 3B.
Instruction Operand Encoding
Op/En
Tuple Type
Operand 1
Operand 2
Operand 3
Operand 4
A
N/A
ModRM:reg (r, w)
ModRM:r/m (r)
N/A
N/A
B
N/A
ModRM:reg (w)
VEX.vvvv (r)
ModRM:r/m (r)
N/A
C
Full Mem
ModRM:reg (w)
EVEX.vvvv (r)
ModRM:r/m (r)
N/A
Description
Performs a SIMD signed multiply of the packed signed word integers in the destination operand (first operand) and
the source operand (second operand), and stores the high 16 bits of each intermediate 32-bit result in the destina-
tion operand. (Figure 4-12 shows this operation when using 64-bit operands.)
n 64-bit mode and not encoded with VEX/EVEX, using a REX prefix in the form of REX.R permits this instruction to
access additional registers (XMM8-XMM15).
Legacy SSE version 64-bit operand: The source operand can be an MMX technology register or a 64-bit memory
location. The destination operand is an MMX technology register.
128-bit Legacy SSE version: The first source and destination operands are XMM registers. The second source
operand is an XMM register or a 128-bit memory location. Bits (MAXVL-1:128) of the corresponding YMM destina-
tion register remain unchanged.
PMULHW-Multiply Packed Signed Integers and Store High Result
Vol. 2B
4-383
VEX.128 encoded version: The first source and destination operands are XMM registers. The second source
operand is an XMM register or a 128-bit memory location. Bits (MAXVL-1:128) of the destination YMM register are
zeroed. VEX.L must be 0, otherwise the instruction will #UD.
VEX.256 encoded version: The second source operand can be an YMM register or a 256-bit memory location. The
first source and destination operands are YMM registers.
EVEX encoded versions: The first source operand is a ZMM/YMM/XMM register. The second source operand can be
a ZMM/YMM/XMM register, a 512/256/128-bit memory location. The destination operand is a ZMM/YMM/XMM
register conditionally updated with writemask k1.
Operation
PMULHW (With 64-bit Operands)
TEMP0[31:0] := DEST[15:0] ∗ SRC[15:0]; (* Signed multiplication *)
TEMP1[31:0] := DEST[31:16] ∗ SRC[31:16];
TEMP2[31:0] := DEST[47:32] ∗ SRC[47:32];
TEMP3[31:0] := DEST[63:48] ∗ SRC[63:48];
DEST[15:0] := TEMP0[31:16];
DEST[31:16] := TEMP1[31:16];
DEST[47:32] := TEMP2[31:16];
DEST[63:48] := TEMP3[31:16];
PMULHW (With 128-bit Operands)
TEMP0[31:0] := DEST[15:0] ∗ SRC[15:0]; (* Signed multiplication *)
TEMP1[31:0] := DEST[31:16] ∗ SRC[31:16];
TEMP2[31:0] := DEST[47:32] ∗ SRC[47:32];
TEMP3[31:0] := DEST[63:48] ∗ SRC[63:48];
TEMP4[31:0] := DEST[79:64] ∗ SRC[79:64];
TEMP5[31:0] := DEST[95:80] ∗ SRC[95:80];
TEMP6[31:0] := DEST[111:96] ∗ SRC[111:96];
TEMP7[31:0] := DEST[127:112] ∗ SRC[127:112];
DEST[15:0] := TEMP0[31:16];
DEST[31:16] := TEMP1[31:16];
DEST[47:32] := TEMP2[31:16];
DEST[63:48] := TEMP3[31:16];
DEST[79:64] := TEMP4[31:16];
DEST[95:80] := TEMP5[31:16];
DEST[111:96] := TEMP6[31:16];
DEST[127:112] := TEMP7[31:16];
VPMULHW (VEX.128 Encoded Version)
TEMP0[31:0] := SRC1[15:0] * SRC2[15:0] (*Signed Multiplication*)
TEMP1[31:0] := SRC1[31:16] * SRC2[31:16]
TEMP2[31:0] := SRC1[47:32] * SRC2[47:32]
TEMP3[31:0] := SRC1[63:48] * SRC2[63:48]
TEMP4[31:0] := SRC1[79:64] * SRC2[79:64]
TEMP5[31:0] := SRC1[95:80] * SRC2[95:80]
TEMP6[31:0] := SRC1[111:96] * SRC2[111:96]
TEMP7[31:0] := SRC1[127:112] * SRC2[127:112]
DEST[15:0] := TEMP0[31:16]
DEST[31:16] := TEMP1[31:16]
DEST[47:32] := TEMP2[31:16]
DEST[63:48] := TEMP3[31:16]
DEST[79:64] := TEMP4[31:16]
DEST[95:80] := TEMP5[31:16]
PMULHW-Multiply Packed Signed Integers and Store High Result
Vol. 2B
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DEST[111:96] := TEMP6[31:16]
DEST[127:112] := TEMP7[31:16]
DEST[MAXVL-1:128] := 0
PMULHW (VEX.256 Encoded Version)
TEMP0[31:0] := SRC1[15:0] * SRC2[15:0] (*Signed Multiplication*)
TEMP1[31:0] := SRC1[31:16] * SRC2[31:16]
TEMP2[31:0] := SRC1[47:32] * SRC2[47:32]
TEMP3[31:0] := SRC1[63:48] * SRC2[63:48]
TEMP4[31:0] := SRC1[79:64] * SRC2[79:64]
TEMP5[31:0] := SRC1[95:80] * SRC2[95:80]
TEMP6[31:0] := SRC1[111:96] * SRC2[111:96]
TEMP7[31:0] := SRC1[127:112] * SRC2[127:112]
TEMP8[31:0] := SRC1[143:128] * SRC2[143:128]
TEMP9[31:0] := SRC1[159:144] * SRC2[159:144]
TEMP10[31:0] := SRC1[175:160] * SRC2[175:160]
TEMP11[31:0] := SRC1[191:176] * SRC2[191:176]
TEMP12[31:0] := SRC1[207:192] * SRC2[207:192]
TEMP13[31:0] := SRC1[223:208] * SRC2[223:208]
TEMP14[31:0] := SRC1[239:224] * SRC2[239:224]
TEMP15[31:0] := SRC1[255:240] * SRC2[255:240]
DEST[15:0] := TEMP0[31:16]
DEST[31:16] := TEMP1[31:16]
DEST[47:32] := TEMP2[31:16]
DEST[63:48] := TEMP3[31:16]
DEST[79:64] := TEMP4[31:16]
DEST[95:80] := TEMP5[31:16]
DEST[111:96] := TEMP6[31:16]
DEST[127:112] := TEMP7[31:16]
DEST[143:128] := TEMP8[31:16]
DEST[159:144] := TEMP9[31:16]
DEST[175:160] := TEMP10[31:16]
DEST[191:176] := TEMP11[31:16]
DEST[207:192] := TEMP12[31:16]
DEST[223:208] := TEMP13[31:16]
DEST[239:224] := TEMP14[31:16]
DEST[255:240] := TEMP15[31:16]
DEST[MAXVL-1:256] := 0
PMULHW-Multiply Packed Signed Integers and Store High Result
Vol. 2B
4-385
PMULHW (EVEX Encoded Versions)
(KL, VL) = (8, 128), (16, 256), (32, 512)
FOR j := 0 TO KL-1
i := j * 16
IF k1[j] OR *no writemask*
THEN
temp[31:0] := SRC1[i+15:i] * SRC2[i+15:i]
DEST[i+15:i] := tmp[31:16]
ELSE
IF *merging-masking*
; merging-masking
THEN *DEST[i+15:i] remains unchanged*
ELSE *zeroing-masking*
; zeroing-masking
DEST[i+15:i] := 0
FI
FI;
ENDFOR
DEST[MAXVL-1:VL] := 0
Intel C/C++ Compiler Intrinsic Equivalent
VPMULHW __m512i _mm512_mulhi_epi16(__m512i a, __m512i b);
VPMULHW __m512i _mm512_mask_mulhi_epi16(__m512i s, __mmask32 k, __m512i a, __m512i b);
VPMULHW __m512i _mm512_maskz_mulhi_epi16( __mmask32 k, __m512i a, __m512i b);
VPMULHW __m256i _mm256_mask_mulhi_epi16(__m256i s, __mmask16 k, __m256i a, __m256i b);
VPMULHW __m256i _mm256_maskz_mulhi_epi16( __mmask16 k, __m256i a, __m256i b);
VPMULHW __m128i _mm_mask_mulhi_epi16(__m128i s, __mmask8 k, __m128i a, __m128i b);
VPMULHW __m128i _mm_maskz_mulhi_epi16( __mmask8 k, __m128i a, __m128i b);
PMULHW __m64 _mm_mulhi_pi16 (__m64 m1, __m64 m2)
(V)PMULHW __m128i _mm_mulhi_epi16 ( __m128i a, __m128i b)
VPMULHW __m256i _mm256_mulhi_epi16 ( __m256i a, __m256i b)
Flags Affected
None.
SIMD Floating-Point Exceptions
None.
Other Exceptions
Non-EVEX-encoded instruction, see Table 2-21, “Type 4 Class Exception Conditions.”
EVEX-encoded instruction, see Exceptions Type E4.nb in Table 2-51, “Type E4 Class Exception Conditions.”
PMULHW-Multiply Packed Signed Integers and Store High Result
Vol. 2B
4-386
PMULLD/PMULLQ-Multiply Packed Integers and Store Low Result
Opcode/
Op/En
64/32 bit
CPUID Feature
Description
Instruction
Mode
Flag
Support
66 0F 38 40 /r
A
V/V
SSE4_1
Multiply the packed dword signed integers in xmm1 and
PMULLD xmm1, xmm2/m128
xmm2/m128 and store the low 32 bits of each product
in xmm1.
VEX.128.66.0F38.WIG 40 /r
B
V/V
AVX
Multiply the packed dword signed integers in xmm2 and
VPMULLD xmm1, xmm2,
xmm3/m128 and store the low 32 bits of each product
xmm3/m128
in xmm1.
VEX.256.66.0F38.WIG 40 /r
B
V/V
AVX2
Multiply the packed dword signed integers in ymm2 and
VPMULLD ymm1, ymm2,
ymm3/m256 and store the low 32 bits of each product
ymm3/m256
in ymm1.
EVEX.128.66.0F38.W0 40 /r
C
V/V
(AVX512VL AND
Multiply the packed dword signed integers in xmm2 and
VPMULLD xmm1 {k1}{z}, xmm2,
AVX512F) OR
xmm3/m128/m32bcst and store the low 32 bits of
xmm3/m128/m32bcst
AVX10.1
each product in xmm1 under writemask k1.
EVEX.256.66.0F38.W0 40 /r
C
V/V
(AVX512VL AND
Multiply the packed dword signed integers in ymm2 and
VPMULLD ymm1 {k1}{z}, ymm2,
AVX512F) OR
ymm3/m256/m32bcst and store the low 32 bits of
ymm3/m256/m32bcst
AVX10.1
each product in ymm1 under writemask k1.
EVEX.512.66.0F38.W0 40 /r
C
V/V
AVX512F
Multiply the packed dword signed integers in zmm2 and
VPMULLD zmm1 {k1}{z}, zmm2,
OR AVX10.1
zmm3/m512/m32bcst and store the low 32 bits of
zmm3/m512/m32bcst
each product in zmm1 under writemask k1.
EVEX.128.66.0F38.W1 40 /r
C
V/V
(AVX512VL AND
Multiply the packed qword signed integers in xmm2 and
VPMULLQ xmm1 {k1}{z}, xmm2,
AVX512DQ) OR
xmm3/m128/m64bcst and store the low 64 bits of
xmm3/m128/m64bcst
AVX10.1
each product in xmm1 under writemask k1.
EVEX.256.66.0F38.W1 40 /r
C
V/V
(AVX512VL AND
Multiply the packed qword signed integers in ymm2 and
VPMULLQ ymm1 {k1}{z}, ymm2,
AVX512DQ) OR
ymm3/m256/m64bcst and store the low 64 bits of
ymm3/m256/m64bcst
AVX10.1
each product in ymm1 under writemask k1.
EVEX.512.66.0F38.W1 40 /r
C
V/V
AVX512DQ
Multiply the packed qword signed integers in zmm2 and
VPMULLQ zmm1 {k1}{z}, zmm2,
OR AVX10.1
zmm3/m512/m64bcst and store the low 64 bits of
zmm3/m512/m64bcst
each product in zmm1 under writemask k1.
Instruction Operand Encoding
Op/En
Tuple Type
Operand 1
Operand 2
Operand 3
Operand 4
A
N/A
ModRM:reg (r, w)
ModRM:r/m (r)
N/A
N/A
B
N/A
ModRM:reg (w)
VEX.vvvv (r)
ModRM:r/m (r)
N/A
C
Full
ModRM:reg (w)
EVEX.vvvv (r)
ModRM:r/m (r)
N/A
Description
Performs a SIMD signed multiply of the packed signed dword/qword integers from each element of the first source
operand with the corresponding element in the second source operand. The low 32/64 bits of each 64/128-bit
intermediate results are stored to the destination operand.
128-bit Legacy SSE version: The first source and destination operands are XMM registers. The second source
operand is an XMM register or a 128-bit memory location. Bits (MAXVL-1:128) of the corresponding ZMM destina-
tion register remain unchanged.
VEX.128 encoded version: The first source and destination operands are XMM registers. The second source
operand is an XMM register or a 128-bit memory location. Bits (MAXVL-1:128) of the corresponding ZMM register
are zeroed.
VEX.256 encoded version: The first source operand is a YMM register; The second source operand is a YMM register
or 256-bit memory location. Bits (MAXVL-1:256) of the corresponding destination ZMM register are zeroed.
PMULLD/PMULLQ-Multiply Packed Integers and Store Low Result
Vol. 2B
4-387
EVEX encoded versions: The first source operand is a ZMM/YMM/XMM register. The second source operand is a
ZMM/YMM/XMM register, a 512/256/128-bit memory location or a 512/256/128-bit vector broadcasted from a
32/64-bit memory location. The destination operand is conditionally updated based on writemask k1.
Operation
VPMULLQ (EVEX Encoded Versions)
(KL, VL) = (2, 128), (4, 256), (8, 512)
FOR j := 0 TO KL-1
i := j * 64
IF k1[j] OR *no writemask* THEN
IF (EVEX.b == 1) AND (SRC2 *is memory*)
THEN Temp[127:0] := SRC1[i+63:i] * SRC2[63:0]
ELSE Temp[127:0] := SRC1[i+63:i] * SRC2[i+63:i]
FI;
DEST[i+63:i] := Temp[63:0]
ELSE
IF *merging-masking*
; merging-masking
THEN *DEST[i+63:i] remains unchanged*
ELSE
; zeroing-masking
DEST[i+63:i] := 0
FI
FI;
ENDFOR
DEST[MAXVL-1:VL] := 0
VPMULLD (EVEX Encoded Versions)
(KL, VL) = (4, 128), (8, 256), (16, 512)
FOR j := 0 TO KL-1
i := j * 32
IF k1[j] OR *no writemask* THEN
IF (EVEX.b = 1) AND (SRC2 *is memory*)
THEN Temp[63:0] := SRC1[i+31:i] * SRC2[31:0]
ELSE Temp[63:0] := SRC1[i+31:i] * SRC2[i+31:i]
FI;
DEST[i+31:i] := Temp[31:0]
ELSE
IF *merging-masking*
; merging-masking
*DEST[i+31:i] remains unchanged*
ELSE
; zeroing-masking
DEST[i+31:i] := 0
FI
FI;
ENDFOR
DEST[MAXVL-1:VL] := 0
PMULLD/PMULLQ-Multiply Packed Integers and Store Low Result
Vol. 2B
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VPMULLD (VEX.256 Encoded Version)
Temp0[63:0] := SRC1[31:0] * SRC2[31:0]
Temp1[63:0] := SRC1[63:32] * SRC2[63:32]
Temp2[63:0] := SRC1[95:64] * SRC2[95:64]
Temp3[63:0] := SRC1[127:96] * SRC2[127:96]
Temp4[63:0] := SRC1[159:128] * SRC2[159:128]
Temp5[63:0] := SRC1[191:160] * SRC2[191:160]
Temp6[63:0] := SRC1[223:192] * SRC2[223:192]
Temp7[63:0] := SRC1[255:224] * SRC2[255:224]
DEST[31:0] := Temp0[31:0]
DEST[63:32] := Temp1[31:0]
DEST[95:64] := Temp2[31:0]
DEST[127:96] := Temp3[31:0]
DEST[159:128] := Temp4[31:0]
DEST[191:160] := Temp5[31:0]
DEST[223:192] := Temp6[31:0]
DEST[255:224] := Temp7[31:0]
DEST[MAXVL-1:256] := 0
VPMULLD (VEX.128 Encoded Version)
Temp0[63:0] := SRC1[31:0] * SRC2[31:0]
Temp1[63:0] := SRC1[63:32] * SRC2[63:32]
Temp2[63:0] := SRC1[95:64] * SRC2[95:64]
Temp3[63:0] := SRC1[127:96] * SRC2[127:96]
DEST[31:0] := Temp0[31:0]
DEST[63:32] := Temp1[31:0]
DEST[95:64] := Temp2[31:0]
DEST[127:96] := Temp3[31:0]
DEST[MAXVL-1:128] := 0
PMULLD (128-bit Legacy SSE Version)
Temp0[63:0] := DEST[31:0] * SRC[31:0]
Temp1[63:0] := DEST[63:32] * SRC[63:32]
Temp2[63:0] := DEST[95:64] * SRC[95:64]
Temp3[63:0] := DEST[127:96] * SRC[127:96]
DEST[31:0] := Temp0[31:0]
DEST[63:32] := Temp1[31:0]
DEST[95:64] := Temp2[31:0]
DEST[127:96] := Temp3[31:0]
DEST[MAXVL-1:128] (Unmodified)
PMULLD/PMULLQ-Multiply Packed Integers and Store Low Result
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Intel C/C++ Compiler Intrinsic Equivalent
VPMULLD __m512i _mm512_mullo_epi32(__m512i a, __m512i b);
VPMULLD __m512i _mm512_mask_mullo_epi32(__m512i s, __mmask16 k, __m512i a, __m512i b);
VPMULLD __m512i _mm512_maskz_mullo_epi32( __mmask16 k, __m512i a, __m512i b);
VPMULLD __m256i _mm256_mask_mullo_epi32(__m256i s, __mmask8 k, __m256i a, __m256i b);
VPMULLD __m256i _mm256_maskz_mullo_epi32( __mmask8 k, __m256i a, __m256i b);
VPMULLD __m128i _mm_mask_mullo_epi32(__m128i s, __mmask8 k, __m128i a, __m128i b);
VPMULLD __m128i _mm_maskz_mullo_epi32( __mmask8 k, __m128i a, __m128i b);
VPMULLD __m256i _mm256_mullo_epi32(__m256i a, __m256i b);
PMULLD __m128i _mm_mullo_epi32(__m128i a, __m128i b);
VPMULLQ __m512i _mm512_mullo_epi64(__m512i a, __m512i b);
VPMULLQ __m512i _mm512_mask_mullo_epi64(__m512i s, __mmask8 k, __m512i a, __m512i b);
VPMULLQ __m512i _mm512_maskz_mullo_epi64( __mmask8 k, __m512i a, __m512i b);
VPMULLQ __m256i _mm256_mullo_epi64(__m256i a, __m256i b);
VPMULLQ __m256i _mm256_mask_mullo_epi64(__m256i s, __mmask8 k, __m256i a, __m256i b);
VPMULLQ __m256i _mm256_maskz_mullo_epi64( __mmask8 k, __m256i a, __m256i b);
VPMULLQ __m128i _mm_mullo_epi64(__m128i a, __m128i b);
VPMULLQ __m128i _mm_mask_mullo_epi64(__m128i s, __mmask8 k, __m128i a, __m128i b);
VPMULLQ __m128i _mm_maskz_mullo_epi64( __mmask8 k, __m128i a, __m128i b);
SIMD Floating-Point Exceptions
None.
Other Exceptions
Non-EVEX-encoded instruction, see Table 2-21, “Type 4 Class Exception Conditions.”
EVEX-encoded instruction, see Table 2-51, “Type E4 Class Exception Conditions.”
PMULLD/PMULLQ-Multiply Packed Integers and Store Low Result
Vol. 2B
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PMULLW-Multiply Packed Signed Integers and Store Low Result
Opcode/
Op/
64/32 bit
CPUID Feature
Description
Instruction
En
Mode
Flag
Support
NP 0F D5 /r1
A
V/V
MMX
Multiply the packed signed word integers in
mm1 register and mm2/m64, and store the low
PMULLW mm, mm/m64
16 bits of the results in mm1.
66 0F D5 /r
A
V/V
SSE2
Multiply the packed signed word integers in
xmm1 and xmm2/m128, and store the low 16
PMULLW xmm1, xmm2/m128
bits of the results in xmm1.
VEX.128.66.0F.WIG D5 /r
B
V/V
AVX
Multiply the packed dword signed integers in
xmm2 and xmm3/m128 and store the low 32
VPMULLW xmm1, xmm2, xmm3/m128
bits of each product in xmm1.
VEX.256.66.0F.WIG D5 /r
B
V/V
AVX2
Multiply the packed signed word integers in
ymm2 and ymm3/m256, and store the low 16
VPMULLW ymm1, ymm2, ymm3/m256
bits of the results in ymm1.
EVEX.128.66.0F.WIG D5 /r
C
V/V
(AVX512VL AND
Multiply the packed signed word integers in
VPMULLW xmm1 {k1}{z}, xmm2,
AVX512BW) OR
xmm2 and xmm3/m128, and store the low 16
xmm3/m128
AVX10.1
bits of the results in xmm1 under writemask k1.
EVEX.256.66.0F.WIG D5 /r
C
V/V
(AVX512VL AND
Multiply the packed signed word integers in
VPMULLW ymm1 {k1}{z}, ymm2,
AVX512BW) OR
ymm2 and ymm3/m256, and store the low 16
ymm3/m256
AVX10.1
bits of the results in ymm1 under writemask k1.
EVEX.512.66.0F.WIG D5 /r
C
V/V
AVX512BW
Multiply the packed signed word integers in
VPMULLW zmm1 {k1}{z}, zmm2, zmm3/m512
OR AVX10.1
zmm2 and zmm3/m512, and store the low 16
bits of the results in zmm1 under writemask k1.
NOTES:
1. See note in Section 2.5, “Intel® AVX and Intel® SSE Instruction Exception Classification,” in the Intel® 64 and IA-32 Architectures Soft-
ware Developer’s Manual, Volume 2A, and Section 25.25.3, “Exception Conditions of Legacy SIMD Instructions Operating on MMX
Registers,” in the Intel® 64 and IA-32 Architectures Software Developer’s Manual, Volume 3B.
Instruction Operand Encoding
Op/En
Tuple Type
Operand 1
Operand 2
Operand 3
Operand 4
A
N/A
ModRM:reg (r, w)
ModRM:r/m (r)
N/A
N/A
B
N/A
ModRM:reg (w)
VEX.vvvv (r)
ModRM:r/m (r)
N/A
C
Full Mem
ModRM:reg (w)
EVEX.vvvv (r)
ModRM:r/m (r)
N/A
Description
Performs a SIMD signed multiply of the packed signed word integers in the destination operand (first operand) and
the source operand (second operand), and stores the low 16 bits of each intermediate 32-bit result in the destina-
tion operand. (Figure 4-12 shows this operation when using 64-bit operands.)
In 64-bit mode and not encoded with VEX/EVEX, using a REX prefix in the form of REX.R permits this instruction to
access additional registers (XMM8-XMM15).
Legacy SSE version 64-bit operand: The source operand can be an MMX technology register or a 64-bit memory
location. The destination operand is an MMX technology register.
128-bit Legacy SSE version: The first source and destination operands are XMM registers. The second source
operand is an XMM register or a 128-bit memory location. Bits (MAXVL-1:128) of the corresponding YMM destina-
tion register remain unchanged.
PMULLW-Multiply Packed Signed Integers and Store Low Result
Vol. 2B
4-391
VEX.128 encoded version: The first source and destination operands are XMM registers. The second source
operand is an XMM register or a 128-bit memory location. Bits (MAXVL-1:128) of the destination YMM register are
zeroed. VEX.L must be 0, otherwise the instruction will #UD.
VEX.256 encoded version: The second source operand can be an YMM register or a 256-bit memory location. The
first source and destination operands are YMM registers.
EVEX encoded versions: The first source operand is a ZMM/YMM/XMM register. The second source operand is a
ZMM/YMM/XMM register, a 512/256/128-bit memory location. The destination operand is conditionally updated
based on writemask k1.
SRC
X3
X2
X1
X0
DEST
Y3
Y2
Y1
Y0
TEMP
Z3 = X3 ∗ Y3
Z2 = X2 ∗ Y2
Z1 = X1 ∗ Y1
Z0 = X0 ∗ Y0
DEST
Z3[15:0]
Z2[15:0]
Z1[15:0]
Z0[15:0]
Figure 4-13. PMULLU Instruction Operation Using 64-bit Operands
Operation
PMULLW (With 64-bit Operands)
TEMP0[31:0] := DEST[15:0] ∗ SRC[15:0]; (* Signed multiplication *)
TEMP1[31:0] := DEST[31:16] ∗ SRC[31:16];
TEMP2[31:0] := DEST[47:32] ∗ SRC[47:32];
TEMP3[31:0] := DEST[63:48] ∗ SRC[63:48];
DEST[15:0] := TEMP0[15:0];
DEST[31:16] := TEMP1[15:0];
DEST[47:32] := TEMP2[15:0];
DEST[63:48] := TEMP3[15:0];
PMULLW (With 128-bit Operands)
TEMP0[31:0] := DEST[15:0] ∗ SRC[15:0]; (* Signed multiplication *)
TEMP1[31:0] := DEST[31:16] ∗ SRC[31:16];
TEMP2[31:0] := DEST[47:32] ∗ SRC[47:32];
TEMP3[31:0] := DEST[63:48] ∗ SRC[63:48];
TEMP4[31:0] := DEST[79:64] ∗ SRC[79:64];
TEMP5[31:0] := DEST[95:80] ∗ SRC[95:80];
TEMP6[31:0] := DEST[111:96] ∗ SRC[111:96];
TEMP7[31:0] := DEST[127:112] ∗ SRC[127:112];
DEST[15:0] := TEMP0[15:0];
DEST[31:16] := TEMP1[15:0];
DEST[47:32] := TEMP2[15:0];
DEST[63:48] := TEMP3[15:0];
DEST[79:64] := TEMP4[15:0];
DEST[95:80] := TEMP5[15:0];
DEST[111:96] := TEMP6[15:0];
DEST[127:112] := TEMP7[15:0];
DEST[MAXVL-1:256] := 0
PMULLW-Multiply Packed Signed Integers and Store Low Result
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VPMULLW (VEX.128 Encoded Version)
Temp0[31:0] := SRC1[15:0] * SRC2[15:0]
Temp1[31:0] := SRC1[31:16] * SRC2[31:16]
Temp2[31:0] := SRC1[47:32] * SRC2[47:32]
Temp3[31:0] := SRC1[63:48] * SRC2[63:48]
Temp4[31:0] := SRC1[79:64] * SRC2[79:64]
Temp5[31:0] := SRC1[95:80] * SRC2[95:80]
Temp6[31:0] := SRC1[111:96] * SRC2[111:96]
Temp7[31:0] := SRC1[127:112] * SRC2[127:112]
DEST[15:0] := Temp0[15:0]
DEST[31:16] := Temp1[15:0]
DEST[47:32] := Temp2[15:0]
DEST[63:48] := Temp3[15:0]
DEST[79:64] := Temp4[15:0]
DEST[95:80] := Temp5[15:0]
DEST[111:96] := Temp6[15:0]
DEST[127:112] := Temp7[15:0]
DEST[MAXVL-1:128] := 0
PMULLW (EVEX Encoded Versions)
(KL, VL) = (8, 128), (16, 256), (32, 512)
FOR j := 0 TO KL-1
i := j * 16
IF k1[j] OR *no writemask*
THEN
temp[31:0] := SRC1[i+15:i] * SRC2[i+15:i]
DEST[i+15:i] := temp[15:0]
ELSE
IF *merging-masking*
; merging-masking
THEN *DEST[i+15:i] remains unchanged*
ELSE *zeroing-masking*
; zeroing-masking
DEST[i+15:i] := 0
FI
FI;
ENDFOR
DEST[MAXVL-1:VL] := 0
Intel C/C++ Compiler Intrinsic Equivalent
VPMULLW __m512i _mm512_mullo_epi16(__m512i a, __m512i b);
VPMULLW __m512i _mm512_mask_mullo_epi16(__m512i s, __mmask32 k, __m512i a, __m512i b);
VPMULLW __m512i _mm512_maskz_mullo_epi16( __mmask32 k, __m512i a, __m512i b);
VPMULLW __m256i _mm256_mask_mullo_epi16(__m256i s, __mmask16 k, __m256i a, __m256i b);
VPMULLW __m256i _mm256_maskz_mullo_epi16( __mmask16 k, __m256i a, __m256i b);
VPMULLW __m128i _mm_mask_mullo_epi16(__m128i s, __mmask8 k, __m128i a, __m128i b);
VPMULLW __m128i _mm_maskz_mullo_epi16( __mmask8 k, __m128i a, __m128i b);
PMULLW __m64 _mm_mullo_pi16(__m64 m1, __m64 m2)
(V)PMULLW __m128i _mm_mullo_epi16 ( __m128i a, __m128i b)
VPMULLW __m256i _mm256_mullo_epi16 ( __m256i a, __m256i b);
Flags Affected
None.
PMULLW-Multiply Packed Signed Integers and Store Low Result
Vol. 2B
4-393
SIMD Floating-Point Exceptions
None.
Other Exceptions
Non-EVEX-encoded instruction, see Table 2-21, “Type 4 Class Exception Conditions.”
EVEX-encoded instruction, see Exceptions Type E4.nb in Table 2-51, “Type E4 Class Exception Conditions.”
PMULLW-Multiply Packed Signed Integers and Store Low Result
Vol. 2B
4-394
PMULUDQ-Multiply Packed Unsigned Doubleword Integers
Opcode/
Op/
64/32 bit
CPUID Feature
Description
Instruction
En
Mode
Flag
Support
NP 0F F4 /r1
A
V/V
SSE2
Multiply unsigned doubleword integer in mm1 by
unsigned doubleword integer in mm2/m64, and
PMULUDQ mm1, mm2/m64
store the quadword result in mm1.
66 0F F4 /r
A
V/V
SSE2
Multiply packed unsigned doubleword integers in
xmm1 by packed unsigned doubleword integers
PMULUDQ xmm1, xmm2/m128
in xmm2/m128, and store the quadword results
in xmm1.
VEX.128.66.0F.WIG F4 /r
B
V/V
AVX
Multiply packed unsigned doubleword integers in
xmm2 by packed unsigned doubleword integers
VPMULUDQ xmm1, xmm2, xmm3/m128
in xmm3/m128, and store the quadword results
in xmm1.
VEX.256.66.0F.WIG F4 /r
B
V/V
AVX2
Multiply packed unsigned doubleword integers in
ymm2 by packed unsigned doubleword integers
VPMULUDQ ymm1, ymm2, ymm3/m256
in ymm3/m256, and store the quadword results
in ymm1.
EVEX.128.66.0F.W1 F4 /r
C
V/V
(AVX512VL AND
Multiply packed unsigned doubleword integers in
VPMULUDQ xmm1 {k1}{z}, xmm2,
AVX512F) OR
xmm2 by packed unsigned doubleword integers
xmm3/m128/m64bcst
AVX10.1
in xmm3/m128/m64bcst, and store the
quadword results in xmm1 under writemask k1.
EVEX.256.66.0F.W1 F4 /r
C
V/V
(AVX512VL AND
Multiply packed unsigned doubleword integers in
VPMULUDQ ymm1 {k1}{z}, ymm2,
AVX512F) OR
ymm2 by packed unsigned doubleword integers
ymm3/m256/m64bcst
AVX10.1
in ymm3/m256/m64bcst, and store the
quadword results in ymm1 under writemask k1.
EVEX.512.66.0F.W1 F4 /r
C
V/V
AVX512F
Multiply packed unsigned doubleword integers in
VPMULUDQ zmm1 {k1}{z}, zmm2,
OR AVX10.1
zmm2 by packed unsigned doubleword integers
zmm3/m512/m64bcst
in zmm3/m512/m64bcst, and store the
quadword results in zmm1 under writemask k1.
NOTES:
1. See note in Section 2.5, “Intel® AVX and Intel® SSE Instruction Exception Classification,” in the Intel® 64 and IA-32 Architectures Soft-
ware Developer’s Manual, Volume 2A, and Section 25.25.3, “Exception Conditions of Legacy SIMD Instructions Operating on MMX
Registers,” in the Intel® 64 and IA-32 Architectures Software Developer’s Manual, Volume 3B.
Instruction Operand Encoding
Op/En
Tuple Type
Operand 1
Operand 2
Operand 3
Operand 4
A
N/A
ModRM:reg (r, w)
ModRM:r/m (r)
N/A
N/A
B
N/A
ModRM:reg (w)
VEX.vvvv (r)
ModRM:r/m (r)
N/A
C
Full
ModRM:reg (w)
EVEX.vvvv (r)
ModRM:r/m (r)
N/A
Description
Multiplies the first operand (destination operand) by the second operand (source operand) and stores the result in
the destination operand.
In 64-bit mode and not encoded with VEX/EVEX, using a REX prefix in the form of REX.R permits this instruction to
access additional registers (XMM8-XMM15).
Legacy SSE version 64-bit operand: The source operand can be an unsigned doubleword integer stored in the low
doubleword of an MMX technology register or a 64-bit memory location. The destination operand can be an
unsigned doubleword integer stored in the low doubleword an MMX technology register. The result is an unsigned
PMULUDQ-Multiply Packed Unsigned Doubleword Integers
Vol. 2B
4-395
quadword integer stored in the destination an MMX technology register. When a quadword result is too large to be
represented in 64 bits (overflow), the result is wrapped around and the low 64 bits are written to the destination
element (that is, the carry is ignored).
For 64-bit memory operands, 64 bits are fetched from memory, but only the low doubleword is used in the compu-
tation.
128-bit Legacy SSE version: The second source operand is two packed unsigned doubleword integers stored in the
first (low) and third doublewords of an XMM register or a 128-bit memory location. For 128-bit memory operands,
128 bits are fetched from memory, but only the first and third doublewords are used in the computation. The first
source operand is two packed unsigned doubleword integers stored in the first and third doublewords of an XMM
register. The destination contains two packed unsigned quadword integers stored in an XMM register. Bits (MAXVL-
1:128) of the corresponding YMM destination register remain unchanged.
VEX.128 encoded version: The second source operand is two packed unsigned doubleword integers stored in the
first (low) and third doublewords of an XMM register or a 128-bit memory location. For 128-bit memory operands,
128 bits are fetched from memory, but only the first and third doublewords are used in the computation. The first
source operand is two packed unsigned doubleword integers stored in the first and third doublewords of an XMM
register. The destination contains two packed unsigned quadword integers stored in an XMM register. Bits (MAXVL-
1:128) of the destination YMM register are zeroed.
VEX.256 encoded version: The second source operand is four packed unsigned doubleword integers stored in the
first (low), third, fifth, and seventh doublewords of a YMM register or a 256-bit memory location. For 256-bit
memory operands, 256 bits are fetched from memory, but only the first, third, fifth, and seventh doublewords are
used in the computation. The first source operand is four packed unsigned doubleword integers stored in the first,
third, fifth, and seventh doublewords of an YMM register. The destination contains four packed unaligned quadword
integers stored in an YMM register.
EVEX encoded version: The input unsigned doubleword integers are taken from the even-numbered elements of
the source operands. The first source operand is a ZMM/YMM/XMM registers. The second source operand can be an
ZMM/YMM/XMM register, a 512/256/128-bit memory location or a 512/256/128-bit vector broadcasted from a 64-
bit memory location. The destination is a ZMM/YMM/XMM register, and updated according to the writemask at 64-
bit granularity.
Operation
PMULUDQ (With 64-Bit Operands)
DEST[63:0] := DEST[31:0] ∗ SRC[31:0];
PMULUDQ (With 128-Bit Operands)
DEST[63:0] := DEST[31:0] ∗ SRC[31:0];
DEST[127:64] := DEST[95:64] ∗ SRC[95:64];
VPMULUDQ (VEX.128 Encoded Version)
DEST[63:0] := SRC1[31:0] * SRC2[31:0]
DEST[127:64] := SRC1[95:64] * SRC2[95:64]
DEST[MAXVL-1:128] := 0
VPMULUDQ (VEX.256 Encoded Version)
DEST[63:0] := SRC1[31:0] * SRC2[31:0]
DEST[127:64] := SRC1[95:64] * SRC2[95:64
DEST[191:128] := SRC1[159:128] * SRC2[159:128]
DEST[255:192] := SRC1[223:192] * SRC2[223:192]
DEST[MAXVL-1:256] := 0
PMULUDQ-Multiply Packed Unsigned Doubleword Integers
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VPMULUDQ (EVEX Encoded Versions)
(KL, VL) = (2, 128), (4, 256), (8, 512)
FOR j := 0 TO KL-1
i := j * 64
IF k1[j] OR *no writemask* THEN
IF (EVEX.b = 1) AND (SRC2 *is memory*)
THEN DEST[i+63:i] := ZeroExtend64( SRC1[i+31:i]) * ZeroExtend64( SRC2[31:0] )
ELSE DEST[i+63:i] := ZeroExtend64( SRC1[i+31:i]) * ZeroExtend64( SRC2[i+31:i] )
FI;
ELSE
IF *merging-masking*
; merging-masking
THEN *DEST[i+63:i] remains unchanged*
ELSE *zeroing-masking*
; zeroing-masking
DEST[i+63:i] := 0
FI
FI;
ENDFOR
DEST[MAXVL-1:VL] := 0
Intel C/C++ Compiler Intrinsic Equivalent
VPMULUDQ __m512i _mm512_mul_epu32(__m512i a, __m512i b);
VPMULUDQ __m512i _mm512_mask_mul_epu32(__m512i s, __mmask8 k, __m512i a, __m512i b);
VPMULUDQ __m512i _mm512_maskz_mul_epu32( __mmask8 k, __m512i a, __m512i b);
VPMULUDQ __m256i _mm256_mask_mul_epu32(__m256i s, __mmask8 k, __m256i a, __m256i b);
VPMULUDQ __m256i _mm256_maskz_mul_epu32( __mmask8 k, __m256i a, __m256i b);
VPMULUDQ __m128i _mm_mask_mul_epu32(__m128i s, __mmask8 k, __m128i a, __m128i b);
VPMULUDQ __m128i _mm_maskz_mul_epu32( __mmask8 k, __m128i a, __m128i b);
PMULUDQ __m64 _mm_mul_su32 (__m64 a, __m64 b)
(V)PMULUDQ __m128i _mm_mul_epu32 ( __m128i a, __m128i b)
VPMULUDQ __m256i _mm256_mul_epu32( __m256i a, __m256i b);
Flags Affected
None.
SIMD Floating-Point Exceptions
None.
Other Exceptions
Non-EVEX-encoded instruction, see Table 2-21, “Type 4 Class Exception Conditions.”
EVEX-encoded instruction, see Table 2-51, “Type E4 Class Exception Conditions.”
PMULUDQ-Multiply Packed Unsigned Doubleword Integers
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4-397
POP-Pop a Value From the Stack
Opcode
Instruction
Op/
64-Bit
Compat/
Description
En
Mode
Leg Mode
8F /0
POP r/m16
M
Valid
Valid
Pop top of stack into m16; increment stack pointer.
8F /0
POP r/m32
M
N.E.
Valid
Pop top of stack into m32; increment stack pointer.
8F /0
POP r/m64
M
Valid
N.E.
Pop top of stack into m64; increment stack pointer. Cannot
encode 32-bit operand size.
58+ rw
POP r16
O
Valid
Valid
Pop top of stack into r16; increment stack pointer.
58+ rd
POP r32
O
N.E.
Valid
Pop top of stack into r32; increment stack pointer.
58+ rd
POP r64
O
Valid
N.E.
Pop top of stack into r64; increment stack pointer. Cannot
encode 32-bit operand size.
1F
POP DS
ZO
Invalid
Valid
Pop top of stack into DS; increment stack pointer.
07
POP ES
ZO
Invalid
Valid
Pop top of stack into ES; increment stack pointer.
17
POP SS
ZO
Invalid
Valid
Pop top of stack into SS; increment stack pointer.
0F A1
POP FS
ZO
Valid
Valid
Pop top of stack into FS; increment stack pointer by 16 bits.
0F A1
POP FS
ZO
N.E.
Valid
Pop top of stack into FS; increment stack pointer by 32 bits.
0F A1
POP FS
ZO
Valid
N.E.
Pop top of stack into FS; increment stack pointer by 64 bits.
0F A9
POP GS
ZO
Valid
Valid
Pop top of stack into GS; increment stack pointer by 16 bits.
0F A9
POP GS
ZO
N.E.
Valid
Pop top of stack into GS; increment stack pointer by 32 bits.
0F A9
POP GS
ZO
Valid
N.E.
Pop top of stack into GS; increment stack pointer by 64 bits.
Instruction Operand Encoding
Op/En
Operand 1
Operand 2
Operand 3
Operand 4
M
ModRM:r/m (w)
N/A
N/A
N/A
O
opcode + rd (w)
N/A
N/A
N/A
ZO
N/A
N/A
N/A
N/A
Description
Loads the value from the top of the stack to the location specified with the destination operand (or explicit opcode)
and then increments the stack pointer. The destination operand can be a general-purpose register, memory loca-
tion, or segment register.
Address and operand sizes are determined and used as follows:
• Address size. The D flag in the current code-segment descriptor determines the default address size; it may be
overridden by an instruction prefix (67H).
The address size is used only when writing to a destination operand in memory.
• Operand size. The D flag in the current code-segment descriptor determines the default operand size; it may
be overridden by instruction prefixes (66H or REX.W).
The operand size (16, 32, or 64 bits) determines the amount by which the stack pointer is incremented (2, 4
or 8).
• Stack-address size. Outside of 64-bit mode, the B flag in the current stack-segment descriptor determines the
size of the stack pointer (16 or 32 bits); in 64-bit mode, the size of the stack pointer is always 64 bits.
The stack-address size determines the width of the stack pointer when reading from the stack in memory and
when incrementing the stack pointer. (As stated above, the amount by which the stack pointer is incremented
is determined by the operand size.)
If the destination operand is one of the segment registers DS, ES, FS, GS, or SS, the value loaded into the register
must be a valid segment selector. In protected mode, popping a segment selector into a segment register automat-
POP-Pop a Value From the Stack
Vol. 2B
4-398
ically causes the descriptor information associated with that segment selector to be loaded into the hidden
(shadow) part of the segment register and causes the selector and the descriptor information to be validated (see
the “Operation” section below).
A NULL value (0000-0003) may be popped into the DS, ES, FS, or GS register without causing a general protection
fault. However, any subsequent attempt to reference a segment whose corresponding segment register is loaded
with a NULL value causes a general protection exception (#GP). In this situation, no memory reference occurs and
the saved value of the segment register is NULL.
The POP instruction cannot pop a value into the CS register. To load the CS register from the stack, use the RET
instruction.
If the ESP register is used as a base register for addressing a destination operand in memory, the POP instruction
computes the effective address of the operand after it increments the ESP register. For the case of a 16-bit stack
where ESP wraps to 0H as a result of the POP instruction, the resulting location of the memory write is processor-
family-specific.
The POP ESP instruction increments the stack pointer (ESP) before data at the old top of stack is written into the
destination.
Loading the SS register with a POP instruction suppresses or inhibits some debug exceptions and inhibits interrupts
on the following instruction boundary. (The inhibition ends after delivery of an exception or the execution of the
next instruction.) This behavior allows a stack pointer to be loaded into the ESP register with the next instruction
(POP ESP) before an event can be delivered. See Section 7.8.3, “Masking Exceptions and Interrupts When
Switching Stacks,” in the Intel® 64 and IA-32 Architectures Software Developer’s Manual, Volume 3A. Intel recom-
mends that software use the LSS instruction to load the SS register and ESP together.
In 64-bit mode, using a REX prefix in the form of REX.R permits access to additional registers (R8-R15). When in
64-bit mode, POPs using 32-bit operands are not encodable and POPs to DS, ES, SS are not valid. See the
summary chart at the beginning of this section for encoding data and limits.
Operation
IF StackAddrSize = 32
THEN
IF OperandSize = 32
THEN
DEST := SS:ESP; (* Copy a doubleword *)
ESP := ESP + 4;
ELSE (* OperandSize = 16*)
DEST := SS:ESP; (* Copy a word *)
ESP := ESP + 2;
FI;
ELSE IF StackAddrSize = 64
THEN
IF OperandSize = 64
THEN
DEST := SS:RSP; (* Copy quadword *)
RSP := RSP + 8;
ELSE (* OperandSize = 16*)
DEST := SS:RSP; (* Copy a word *)
RSP := RSP + 2;
FI;
FI;
ELSE StackAddrSize = 16
THEN
IF OperandSize = 16
THEN
DEST := SS:SP; (* Copy a word *)
SP := SP + 2;
POP-Pop a Value From the Stack
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4-399
ELSE (* OperandSize = 32 *)
DEST := SS:SP; (* Copy a doubleword *)
SP := SP + 4;
FI;
FI;
Loading a segment register while in protected mode results in special actions, as described in the following listing.
These checks are performed on the segment selector and the segment descriptor it points to.
64-BIT_MODE
IF FS, or GS is loaded with non-NULL selector;
THEN
IF segment selector index is outside descriptor table limits
OR segment is not a data or readable code segment
OR ((segment is a data or nonconforming code segment)
AND ((RPL > DPL) or (CPL > DPL))
THEN #GP(selector);
IF segment not marked present
THEN #NP(selector);
ELSE
SegmentRegister := segment selector;
SegmentRegister := segment descriptor;
FI;
FI;
IF FS, or GS is loaded with a NULL selector;
THEN
SegmentRegister := segment selector;
SegmentRegister := segment descriptor;
FI;
PREOTECTED MODE OR COMPATIBILITY MODE;
IF SS is loaded;
THEN
IF segment selector is NULL
THEN #GP(0);
FI;
IF segment selector index is outside descriptor table limits
or segment selector's RPL ≠ CPL
or segment is not a writable data segment
or DPL ≠ CPL
THEN #GP(selector);
FI;
IF segment not marked present
THEN #SS(selector);
ELSE
SS := segment selector;
SS := segment descriptor;
FI;
FI;
IF DS, ES, FS, or GS is loaded with non-NULL selector;
THEN
POP-Pop a Value From the Stack
Vol. 2B
4-400
IF segment selector index is outside descriptor table limits
or segment is not a data or readable code segment
or ((segment is a data or nonconforming code segment)
and ((RPL > DPL) or (CPL > DPL))
THEN #GP(selector);
FI;
IF segment not marked present
THEN #NP(selector);
ELSE
SegmentRegister := segment selector;
SegmentRegister := segment descriptor;
FI;
FI;
IF DS, ES, FS, or GS is loaded with a NULL selector
THEN
SegmentRegister := segment selector;
SegmentRegister := segment descriptor;
FI;
Flags Affected
None.
Protected Mode Exceptions
#GP(0)
If attempt is made to load SS register with NULL segment selector.
If the destination operand is in a non-writable segment.
If a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit.
If the DS, ES, FS, or GS register is used to access memory and it contains a NULL segment
selector.
#GP(selector)
If segment selector index is outside descriptor table limits.
If the SS register is being loaded and the segment selector's RPL and the segment descriptor’s
DPL are not equal to the CPL.
If the SS register is being loaded and the segment pointed to is a
non-writable data segment.
If the DS, ES, FS, or GS register is being loaded and the segment pointed to is not a data or
readable code segment.
If the DS, ES, FS, or GS register is being loaded and the segment pointed to is a data or
nonconforming code segment, but both the RPL and the CPL are greater than the DPL.
#SS(0)
If the current top of stack is not within the stack segment.
If a memory operand effective address is outside the SS segment limit.
#SS(selector)
If the SS register is being loaded and the segment pointed to is marked not present.
#NP
If the DS, ES, FS, or GS register is being loaded and the segment pointed to is marked not
present.
#PF(fault-code)
If a page fault occurs.
#AC(0)
If an unaligned memory reference is made while the current privilege level is 3 and alignment
checking is enabled.
#UD
If the LOCK prefix is used.
POP-Pop a Value From the Stack
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4-401
Real-Address Mode Exceptions
#GP
If a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit.
#UD
If the LOCK prefix is used.
Virtual-8086 Mode Exceptions
#GP(0)
If a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit.
#PF(fault-code)
If a page fault occurs.
#AC(0)
If an unaligned memory reference is made while alignment checking is enabled.
#UD
If the LOCK prefix is used.
Compatibility Mode Exceptions
Same as for protected mode exceptions.
64-Bit Mode Exceptions
#GP(0)
If the memory address is in a non-canonical form.
#SS(0)
If the stack address is in a non-canonical form.
#GP(selector)
If the descriptor is outside the descriptor table limit.
If the FS or GS register is being loaded and the segment pointed to is not a data or readable
code segment.
If the FS or GS register is being loaded and the segment pointed to is a data or nonconforming
code segment, but both the RPL and the CPL are greater than the DPL.
#AC(0)
If an unaligned memory reference is made while alignment checking is enabled.
#PF(fault-code)
If a page fault occurs.
#NP
If the FS or GS register is being loaded and the segment pointed to is marked not present.
#UD
If the LOCK prefix is used.
If the DS, ES, or SS register is being loaded.
POP-Pop a Value From the Stack
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POPA/POPAD-Pop All General-Purpose Registers
Opcode
Instruction
Op/
64-Bit
Compat/
Description
En
Mode
Leg Mode
61
POPA
ZO
Invalid
Valid
Pop DI, SI, BP, BX, DX, CX, and AX.
61
POPAD
ZO
Invalid
Valid
Pop EDI, ESI, EBP, EBX, EDX, ECX, and EAX.
Instruction Operand Encoding
Op/En
Operand 1
Operand 2
Operand 3
Operand 4
ZO
N/A
N/A
N/A
N/A
Description
Pops doublewords (POPAD) or words (POPA) from the stack into the general-purpose registers. The registers are
loaded in the following order: EDI, ESI, EBP, EBX, EDX, ECX, and EAX (if the operand-size attribute is 32) and DI,
SI, BP, BX, DX, CX, and AX (if the operand-size attribute is 16). (These instructions reverse the operation of the
PUSHA/PUSHAD instructions.) The value on the stack for the ESP or SP register is ignored. Instead, the ESP or SP
register is incremented after each register is loaded.
The POPA (pop all) and POPAD (pop all double) mnemonics reference the same opcode. The POPA instruction is
intended for use when the operand-size attribute is 16 and the POPAD instruction for when the operand-size attri-
bute is 32. Some assemblers may force the operand size to 16 when POPA is used and to 32 when POPAD is used
(using the operand-size override prefix [66H] if necessary). Others may treat these mnemonics as synonyms
(POPA/POPAD) and use the current setting of the operand-size attribute to determine the size of values to be
popped from the stack, regardless of the mnemonic used. (The D flag in the current code segment’s segment
descriptor determines the operand-size attribute.)
This instruction executes as described in non-64-bit modes. It is not valid in 64-bit mode.
Operation
IF 64-Bit Mode
THEN
#UD;
ELSE
IF OperandSize = 32 (* Instruction = POPAD *)
THEN
EDI := Pop();
ESI := Pop();
EBP := Pop();
Increment ESP by 4; (* Skip next 4 bytes of stack *)
EBX := Pop();
EDX := Pop();
ECX := Pop();
EAX := Pop();
ELSE (* OperandSize = 16, instruction = POPA *)
DI := Pop();
SI := Pop();
BP := Pop();
Increment ESP by 2; (* Skip next 2 bytes of stack *)
BX := Pop();
DX := Pop();
CX := Pop();
AX := Pop();
FI;
FI;
POPA/POPAD-Pop All General-Purpose Registers
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Flags Affected
None.
Protected Mode Exceptions
#SS(0)
If the starting or ending stack address is not within the stack segment.
#PF(fault-code)
If a page fault occurs.
#AC(0)
If an unaligned memory reference is made while the current privilege level is 3 and alignment
checking is enabled.
#UD
If the LOCK prefix is used.
Real-Address Mode Exceptions
#SS
If the starting or ending stack address is not within the stack segment.
#UD
If the LOCK prefix is used.
Virtual-8086 Mode Exceptions
#SS(0)
If the starting or ending stack address is not within the stack segment.
#PF(fault-code)
If a page fault occurs.
#AC(0)
If an unaligned memory reference is made while alignment checking is enabled.
#UD
If the LOCK prefix is used.
Compatibility Mode Exceptions
Same as for protected mode exceptions.
64-Bit Mode Exceptions
#UD
If in 64-bit mode.
POPA/POPAD-Pop All General-Purpose Registers
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POPCNT-Return the Count of Number of Bits Set to 1
Opcode
Instruction
Op/
64-Bit
Compat/
Description
En
Mode
Leg Mode
F3 0F B8 /r
POPCNT r16, r/m16
RM
Valid
Valid
POPCNT on r/m16
F3 0F B8 /r
POPCNT r32, r/m32
RM
Valid
Valid
POPCNT on r/m32
F3 REX.W 0F B8 /r
POPCNT r64, r/m64
RM
Valid
N.E.
POPCNT on r/m64
Instruction Operand Encoding
Op/En
Operand 1
Operand 2
Operand 3
Operand 4
RM
ModRM:reg (w)
ModRM:r/m (r)
N/A
N/A
Description
This instruction calculates the number of bits set to 1 in the second operand (source) and returns the count in the
first operand (a destination register).
Operation
Count = 0;
For (i=0; i < OperandSize; i++)
{
IF (SRC[ i] = 1) // i’th bit
THEN Count++; FI;
}
DEST := Count;
Flags Affected
OF, SF, ZF, AF, CF, PF are all cleared. ZF is set if SRC = 0, otherwise ZF is cleared.
Intel C/C++ Compiler Intrinsic Equivalent
POPCNT int _mm_popcnt_u32(unsigned int a);
POPCNT int64_t _mm_popcnt_u64(unsigned __int64 a);
Protected Mode Exceptions
#GP(0)
If a memory operand effective address is outside the CS, DS, ES, FS or GS segments.
#SS(0)
If a memory operand effective address is outside the SS segment limit.
#PF (fault-code)
For a page fault.
#AC(0)
If an unaligned memory reference is made while the current privilege level is 3 and alignment
checking is enabled.
#UD
If CPUID.01H:ECX.POPCNT[23] = 0.
If LOCK prefix is used.
Real-Address Mode Exceptions
#GP(0)
If any part of the operand lies outside of the effective address space from 0 to 0FFFFH.
#SS(0)
If a memory operand effective address is outside the SS segment limit.
#UD
If CPUID.01H:ECX.POPCNT[23] = 0.
If LOCK prefix is used.
POPCNT-Return the Count of Number of Bits Set to 1
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Virtual 8086 Mode Exceptions
#GP(0)
If any part of the operand lies outside of the effective address space from 0 to 0FFFFH.
#SS(0)
If a memory operand effective address is outside the SS segment limit.
#PF (fault-code)
For a page fault.
#AC(0)
If an unaligned memory reference is made while alignment checking is enabled.
#UD
If CPUID.01H:ECX.POPCNT[23] = 0.
If LOCK prefix is used.
Compatibility Mode Exceptions
Same exceptions as in Protected Mode.
64-Bit Mode Exceptions
#GP(0)
If the memory address is in a non-canonical form.
#SS(0)
If a memory address referencing the SS segment is in a non-canonical form.
#PF (fault-code)
For a page fault.
#AC(0)
If alignment checking is enabled and an unaligned memory reference is made while the
current privilege level is 3.
#UD
If CPUID.01H:ECX.POPCNT[23] = 0.
If LOCK prefix is used.
POPCNT-Return the Count of Number of Bits Set to 1
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POPF/POPFD/POPFQ-Pop Stack Into EFLAGS Register
Opcode
Instruction
Op/
64-Bit
Compat/
Description
En
Mode
Leg Mode
9D
POPF
ZO
Valid
Valid
Pop top of stack into lower 16 bits of EFLAGS.
9D
POPFD
ZO
N.E.
Valid
Pop top of stack into EFLAGS.
9D
POPFQ
ZO
Valid
N.E.
Pop top of stack and zero-extend into RFLAGS.
Instruction Operand Encoding
Op/En
Operand 1
Operand 2
Operand 3
Operand 4
ZO
N/A
N/A
N/A
N/A
Description
Pops a doubleword (POPFD) from the top of the stack (if the current operand-size attribute is 32) and stores the
value in the EFLAGS register, or pops a word from the top of the stack (if the operand-size attribute is 16) and
stores it in the lower 16 bits of the EFLAGS register (that is, the FLAGS register). These instructions reverse the
operation of the PUSHF/PUSHFD/PUSHFQ instructions.
The POPF (pop flags) and POPFD (pop flags double) mnemonics reference the same opcode. The POPF instruction
is intended for use when the operand-size attribute is 16; the POPFD instruction is intended for use when the
operand-size attribute is 32. Some assemblers may force the operand size to 16 for POPF and to 32 for POPFD.
Others may treat the mnemonics as synonyms (POPF/POPFD) and use the setting of the operand-size attribute to
determine the size of values to pop from the stack.
The effect of POPF/POPFD on the EFLAGS register changes, depending on the mode of operation. See Table 4-20
and the key below for details.
When operating in protected, compatibility, or 64-bit mode at privilege level 0 (or in real-address mode, the equiv-
alent to privilege level 0), all non-reserved flags in the EFLAGS register except RF1, VIP, VIF, and VM may be modi-
fied. VIP, VIF, and VM remain unaffected.
When operating in protected, compatibility, or 64-bit mode with a privilege level greater than 0, but less than or
equal to IOPL, all flags can be modified except the IOPL field and RF, IF, VIP, VIF, and VM; these remain unaffected.
The AC and ID flags can only be modified if the operand-size attribute is 32. The interrupt flag (IF) is altered only
when executing at a level at least as privileged as the IOPL. If a POPF/POPFD instruction is executed with insuffi-
cient privilege, an exception does not occur but privileged bits do not change.
When operating in virtual-8086 mode (EFLAGS.VM = 1) without the virtual-8086 mode extensions (CR4.VME = 0),
the POPF/POPFD instructions can be used only if IOPL = 3; otherwise, a general-protection exception (#GP)
occurs. If the virtual-8086 mode extensions are enabled (CR4.VME = 1), POPF (but not POPFD) can be executed in
virtual-8086 mode with IOPL < 3.
(The protected-mode virtual-interrupt feature - enabled by setting CR4.PVI - affects the CLI and STI instructions
in the same manner as the virtual-8086 mode extensions. POPF, however, is not affected by CR4.PVI.)
In 64-bit mode, the mnemonic assigned is POPFQ (note that the 32-bit operand is not encodable). POPFQ pops 64
bits from the stack. Reserved bits of RFLAGS (including the upper 32 bits of RFLAGS) are not affected.
See Chapter 3 of the Intel® 64 and IA-32 Architectures Software Developer’s Manual, Volume 1, for more informa-
tion about the EFLAGS registers.
1. RF is always zero after the execution of POPF. This is because POPF, like all instructions, clears RF as it begins to execute.
POPF/POPFD/POPFQ-Pop Stack Into EFLAGS Register
Vol. 2B
4-407
Table 4-20. Effect of POPF/POPFD on the EFLAGS Register
Flags
Operand
Notes
Mode
CPL
IOPL
21
20
19
18
17
16
14
13:12
11
10
9
8
7
6
4
2
0
Size
ID
VIP
VIF
AC
VM
RF
NT
IOPL
OF
DF
IF
TF
SF
ZF
AF
PF
CF
Real-Address
16
0
0-3
N
N
N
N
N
0
S
S
S
S
S
S
S
S
S
S
S
Mode
32
0
0-3
S
N
N
S
N
0
S
S
S
S
S
S
S
S
S
S
S
(CR0.PE = 0)
16
0
0-3
N
N
N
N
N
0
S
S
S
S
S
S
S
S
S
S
S
Protected,
Compatibility,
16
1-3
<CPL
N
N
N
N
N
0
S
N
S
S
N
S
S
S
S
S
S
and 64-Bit
16
1-3
≥CPL
N
N
N
N
N
0
S
N
S
S
S
S
S
S
S
S
S
Modes
32, 64
0
0-3
S
N
N
S
N
0
S
S
S
S
S
S
S
S
S
S
S
(CR0.PE = 1
32, 64
1-3
<CPL
S
N
N
S
N
0
S
N
S
S
N
S
S
S
S
S
S
EFLAGS.VM = 0)
32, 64
1-3
≥CPL
S
N
N
S
N
0
S
N
S
S
S
S
S
S
S
S
S
1
16
3
0-2
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
Virtual-8086
(CR0.PE = 1
16
3
3
N
N
N
N
N
0
S
N
S
S
S
S
S
S
S
S
S
EFLAGS.VM = 1
1
32
3
0-2
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
CR4.VME = 0)
32
3
3
S
N
N
S
N
0
S
N
S
S
S
S
S
S
S
S
S
2,3
16
3
0-2
N/
N/
SV/
N/
N/
0/
S/
N/X
S/
S/
N/
S/
S/
S/
S/
S/
S/
VME
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
(CR0.PE = 1
16
3
3
N
N
N
N
N
0
S
N
S
S
S
S
S
S
S
S
S
EFLAGS.VM = 1
1
CR4.VME = 1)
32
3
0-2
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
32
3
3
S
N
N
S
N
0
S
N
S
S
S
S
S
S
S
S
S
NOTES:
1. #GP fault - no flag update
2. #GP fault with no flag update if VIP=1 in EFLAGS register and IF=1 in FLAGS value on stack
3. #GP fault with no flag update if TF=1 in FLAGS value on stack
Key
S
Updated from stack
SV
Updated from IF (bit 9) in FLAGS value on stack
N
No change in value
X
No EFLAGS update
0
Value is cleared
Operation
IF EFLAGS.VM = 0 (* Not in Virtual-8086 Mode *)
THEN IF CPL = 0 OR CR0.PE = 0
THEN
IF OperandSize = 32;
THEN
EFLAGS := Pop(); (* 32-bit pop *)
(* All non-reserved flags except RF, VIP, VIF, and VM can be modified;
VIP, VIF, VM, and all reserved bits are unaffected. RF is cleared. *)
ELSE IF (Operandsize = 64)
RFLAGS = Pop(); (* 64-bit pop *)
(* All non-reserved flags except RF, VIP, VIF, and VM can be modified;
VIP, VIF, VM, and all reserved bits are unaffected. RF is cleared. *)
POPF/POPFD/POPFQ-Pop Stack Into EFLAGS Register
Vol. 2B
4-408
ELSE (* OperandSize = 16 *)
EFLAGS[15:0] := Pop(); (* 16-bit pop *)
(* All non-reserved flags can be modified. *)
FI;
ELSE (* CPL > 0 *)
IF OperandSize = 32
THEN
IF CPL > IOPL
THEN
EFLAGS := Pop(); (* 32-bit pop *)
(* All non-reserved bits except IF, IOPL, VIP, VIF, VM, and RF can be modified;
IF, IOPL, VIP, VIF, VM, and all reserved bits are unaffected; RF is cleared. *)
ELSE
EFLAGS := Pop(); (* 32-bit pop *)
(* All non-reserved bits except IOPL, VIP, VIF, VM, and RF can be modified;
IOPL, VIP, VIF, VM, and all reserved bits are unaffected; RF is cleared. *)
FI;
ELSE IF (Operandsize = 64)
IF CPL > IOPL
THEN
RFLAGS := Pop(); (* 64-bit pop *)
(* All non-reserved bits except IF, IOPL, VIP, VIF, VM, and RF can be modified;
IF, IOPL, VIP, VIF, VM, and all reserved bits are unaffected; RF is cleared. *)
ELSE
RFLAGS := Pop(); (* 64-bit pop *)
(* All non-reserved bits except IOPL, VIP, VIF, VM, and RF can be modified;
IOPL, VIP, VIF, VM, and all reserved bits are unaffected; RF is cleared. *)
FI;
ELSE (* OperandSize = 16 *)
EFLAGS[15:0] := Pop(); (* 16-bit pop *)
(* All non-reserved bits except IOPL can be modified; IOPL and all
reserved bits are unaffected. *)
FI;
FI;
ELSE (* In virtual-8086 mode *)
IF IOPL = 3
THEN
IF OperandSize = 32
THEN
EFLAGS := Pop();
(* All non-reserved bits except IOPL, VIP, VIF, VM, and RF can be modified;
VIP, VIF, VM, IOPL, and all reserved bits are unaffected. RF is cleared. *)
ELSE
EFLAGS[15:0] := Pop(); FI;
(* All non-reserved bits except IOPL can be modified; IOPL and all reserved bits are unaffected. *)
FI;
ELSE (* IOPL < 3 *)
IF (Operandsize = 32) OR (CR4.VME = 0)
THEN #GP(0); (* Trap to virtual-8086 monitor. *)
ELSE (* Operandsize = 16 and CR4.VME = 1 *)
tempFLAGS := Pop();
IF (EFLAGS.VIP = 1 AND tempFLAGS[9] = 1) OR tempFLAGS[8] = 1
THEN #GP(0);
ELSE
POPF/POPFD/POPFQ-Pop Stack Into EFLAGS Register
Vol. 2B
4-409
EFLAGS.VIF := tempFLAGS[9];
EFLAGS[15:0] := tempFLAGS;
(* All non-reserved bits except IOPL and IF can be modified;
IOPL, IF, and all reserved bits are unaffected. *)
FI;
FI;
FI;
FI;
Flags Affected
All flags may be affected; see the Operation section for details.
Protected Mode Exceptions
#SS(0)
If the top of stack is not within the stack segment.
#PF(fault-code)
If a page fault occurs.
#AC(0)
If an unaligned memory reference is made while CPL = 3 and alignment checking is enabled.
#UD
If the LOCK prefix is used.
Real-Address Mode Exceptions
#SS
If the top of stack is not within the stack segment.
#UD
If the LOCK prefix is used.
Virtual-8086 Mode Exceptions
#GP(0)
If IOPL < 3 and VME is not enabled.
If IOPL < 3 and the 32-bit operand size is used.
If IOPL < 3, EFLAGS.VIP = 1, and bit 9 (IF) is set in the FLAGS value on the stack.
If IOPL < 3 and bit 8 (TF) is set in the FLAGS value on the stack.
If an attempt is made to execute the POPF/POPFD instruction with an operand-size override
prefix.
#SS(0)
If the top of stack is not within the stack segment.
#PF(fault-code)
If a page fault occurs.
#AC(0)
If an unaligned memory reference is made while alignment checking is enabled.
#UD
If the LOCK prefix is used.
Compatibility Mode Exceptions
Same as for protected mode exceptions.
64-Bit Mode Exceptions
#SS(0)
If the stack address is in a non-canonical form.
#PF(fault-code)
If a page fault occurs.
#AC(0)
If alignment checking is enabled and an unaligned memory reference is made while the
current privilege level is 3.
#UD
If the LOCK prefix is used.
POPF/POPFD/POPFQ-Pop Stack Into EFLAGS Register
Vol. 2B
4-410
POR-Bitwise Logical OR
Opcode/
Op/
64/32 bit
CPUID Feature
Description
Instruction
En
Mode
Flag
Support
NP 0F EB /r1
A
V/V
MMX
Bitwise OR of mm/m64 and mm.
POR mm, mm/m64
66 0F EB /r
A
V/V
SSE2
Bitwise OR of xmm2/m128 and xmm1.
POR xmm1, xmm2/m128
VEX.128.66.0F.WIG EB /r
B
V/V
AVX
Bitwise OR of xmm2/m128 and xmm3.
VPOR xmm1, xmm2, xmm3/m128
VEX.256.66.0F.WIG EB /r
B
V/V
AVX2
Bitwise OR of ymm2/m256 and ymm3.
VPOR ymm1, ymm2, ymm3/m256
EVEX.128.66.0F.W0 EB /r
C
V/V
(AVX512VL AND
Bitwise OR of packed doubleword integers in
VPORD xmm1 {k1}{z}, xmm2,
AVX512F) OR
xmm2 and xmm3/m128/m32bcst using
xmm3/m128/m32bcst
AVX10.1
writemask k1.
EVEX.256.66.0F.W0 EB /r
C
V/V
(AVX512VL AND
Bitwise OR of packed doubleword integers in
VPORD ymm1 {k1}{z}, ymm2,
AVX512F) OR
ymm2 and ymm3/m256/m32bcst using
ymm3/m256/m32bcst
AVX10.1
writemask k1.
EVEX.512.66.0F.W0 EB /r
C
V/V
AVX512F
Bitwise OR of packed doubleword integers in
VPORD zmm1 {k1}{z}, zmm2,
OR AVX10.1
zmm2 and zmm3/m512/m32bcst using
zmm3/m512/m32bcst
writemask k1.
EVEX.128.66.0F.W1 EB /r
C
V/V
(AVX512VL AND
Bitwise OR of packed quadword integers in
VPORQ xmm1 {k1}{z}, xmm2,
AVX512F) OR
xmm2 and xmm3/m128/m64bcst using
xmm3/m128/m64bcst
AVX10.1
writemask k1.
EVEX.256.66.0F.W1 EB /r
C
V/V
(AVX512VL AND
Bitwise OR of packed quadword integers in
VPORQ ymm1 {k1}{z}, ymm2,
AVX512F) OR
ymm2 and ymm3/m256/m64bcst using
ymm3/m256/m64bcst
AVX10.1
writemask k1.
EVEX.512.66.0F.W1 EB /r
C
V/V
AVX512F
Bitwise OR of packed quadword integers in
VPORQ zmm1 {k1}{z}, zmm2,
OR AVX10.1
zmm2 and zmm3/m512/m64bcst using
zmm3/m512/m64bcst
writemask k1.
NOTES:
1. See note in Section 2.5, “Intel® AVX and Intel® SSE Instruction Exception Classification,” in the Intel® 64 and IA-32 Architectures Soft-
ware Developer’s Manual, Volume 2A, and Section 25.25.3, “Exception Conditions of Legacy SIMD Instructions Operating on MMX
Registers,” in the Intel® 64 and IA-32 Architectures Software Developer’s Manual, Volume 3B.
Instruction Operand Encoding
Op/En
Tuple Type
Operand 1
Operand 2
Operand 3
Operand 4
A
N/A
ModRM:reg (r, w)
ModRM:r/m (r)
N/A
N/A
B
N/A
ModRM:reg (w)
VEX.vvvv (r)
ModRM:r/m (r)
N/A
C
Full
ModRM:reg (w)
EVEX.vvvv (r)
ModRM:r/m (r)
N/A
Description
Performs a bitwise logical OR operation on the source operand (second operand) and the destination operand (first
operand) and stores the result in the destination operand. Each bit of the result is set to 1 if either or both of the
corresponding bits of the first and second operands are 1; otherwise, it is set to 0.
In 64-bit mode and not encoded with VEX/EVEX, using a REX prefix in the form of REX.R permits this instruction to
access additional registers (XMM8-XMM15).
POR-Bitwise Logical OR
Vol. 2B
4-411
Legacy SSE version: The source operand can be an MMX technology register or a 64-bit memory location. The
destination operand is an MMX technology register.
128-bit Legacy SSE version: The second source operand is an XMM register or a 128-bit memory location. The first
source and destination operands can be XMM registers. Bits (MAXVL-1:128) of the corresponding YMM destination
register remain unchanged.
VEX.128 encoded version: The second source operand is an XMM register or a 128-bit memory location. The first
source and destination operands can be XMM registers. Bits (MAXVL-1:128) of the destination YMM register are
zeroed.
VEX.256 encoded version: The second source operand is an YMM register or a 256-bit memory location. The first
source and destination operands can be YMM registers.
EVEX encoded version: The first source operand is a ZMM/YMM/XMM register. The second source operand can be a
ZMM/YMM/XMM register, a 512/256/128-bit memory location or a 512/256/128-bit vector broadcasted from a
32/64-bit memory location. The destination operand is a ZMM/YMM/XMM register conditionally updated with write-
mask k1 at 32/64-bit granularity.
Operation
POR (64-bit Operand)
DEST := DEST OR SRC
POR (128-bit Legacy SSE Version)
DEST := DEST OR SRC
DEST[MAXVL-1:128] (Unmodified)
VPOR (VEX.128 Encoded Version)
DEST := SRC1 OR SRC2
DEST[MAXVL-1:128] := 0
VPOR (VEX.256 Encoded Version)
DEST := SRC1 OR SRC2
DEST[MAXVL-1:256] := 0
VPORD (EVEX Encoded Versions)
(KL, VL) = (4, 128), (8, 256), (16, 512)
FOR j := 0 TO KL-1
i := j * 32
IF k1[j] OR *no writemask* THEN
IF (EVEX.b = 1) AND (SRC2 *is memory*)
THEN DEST[i+31:i] := SRC1[i+31:i] BITWISE OR SRC2[31:0]
ELSE DEST[i+31:i] := SRC1[i+31:i] BITWISE OR SRC2[i+31:i]
FI;
ELSE
IF *merging-masking*
; merging-masking
*DEST[i+31:i] remains unchanged*
ELSE
; zeroing-masking
DEST[i+31:i] := 0
FI;
FI;
ENDFOR;
DEST[MAXVL-1:VL] := 0
POR-Bitwise Logical OR
Vol. 2B
4-412
Intel C/C++ Compiler Intrinsic Equivalent
VPORD __m512i _mm512_or_epi32(__m512i a, __m512i b);
VPORD __m512i _mm512_mask_or_epi32(__m512i s, __mmask16 k, __m512i a, __m512i b);
VPORD __m512i _mm512_maskz_or_epi32( __mmask16 k, __m512i a, __m512i b);
VPORD __m256i _mm256_or_epi32(__m256i a, __m256i b);
VPORD __m256i _mm256_mask_or_epi32(__m256i s, __mmask8 k, __m256i a, __m256i b,);
VPORD __m256i _mm256_maskz_or_epi32( __mmask8 k, __m256i a, __m256i b);
VPORD __m128i _mm_or_epi32(__m128i a, __m128i b);
VPORD __m128i _mm_mask_or_epi32(__m128i s, __mmask8 k, __m128i a, __m128i b);
VPORD __m128i _mm_maskz_or_epi32( __mmask8 k, __m128i a, __m128i b);
VPORQ __m512i _mm512_or_epi64(__m512i a, __m512i b);
VPORQ __m512i _mm512_mask_or_epi64(__m512i s, __mmask8 k, __m512i a, __m512i b);
VPORQ __m512i _mm512_maskz_or_epi64(__mmask8 k, __m512i a, __m512i b);
VPORQ __m256i _mm256_or_epi64(__m256i a, int imm);
VPORQ __m256i _mm256_mask_or_epi64(__m256i s, __mmask8 k, __m256i a, __m256i b);
VPORQ __m256i _mm256_maskz_or_epi64( __mmask8 k, __m256i a, __m256i b);
VPORQ __m128i _mm_or_epi64(__m128i a, __m128i b);
VPORQ __m128i _mm_mask_or_epi64(__m128i s, __mmask8 k, __m128i a, __m128i b);
VPORQ __m128i _mm_maskz_or_epi64( __mmask8 k, __m128i a, __m128i b);
POR __m64 _mm_or_si64(__m64 m1, __m64 m2)
(V)POR __m128i _mm_or_si128(__m128i m1, __m128i m2)
VPOR __m256i _mm256_or_si256 ( __m256i a, __m256i b)
Flags Affected
None.
SIMD Floating-Point Exceptions
None.
Other Exceptions
Non-EVEX-encoded instruction, see Table 2-21, “Type 4 Class Exception Conditions.”
EVEX-encoded instruction, see Table 2-51, “Type E4 Class Exception Conditions.”
POR-Bitwise Logical OR
Vol. 2B
4-413
PREFETCHh-Prefetch Data Into Caches
Opcode/
Op/
64/32 Bit
Description
Instruction
En
Mode
Support
0F 18 /1
M
V/V
Move data from m8 closer to the processor using T0 hint.
PREFETCHT0 m8
0F 18 /2
M
V/V
Move data from m8 closer to the processor using T1 hint.
PREFETCHT1 m8
0F 18 /3
M
V/V
Move data from m8 closer to the processor using T2 hint.
PREFETCHT2 m8
0F 18 /0
M
V/V
Move data from m8 closer to the processor using NTA hint.
PREFETCHNTA m8
0F 18 /7
M
V/I
Move code from relative address closer to the processor using IT0 hint.
PREFETCHIT0 m8
0F 18 /6
M
V/I
Move code from relative address closer to the processor using IT1 hint.
PREFETCHIT1 m8
Instruction Operand Encoding
Op/En
Operand 1
Operand 2
Operand 3
Operand 4
M
ModRM:r/m (r)
N/A
N/A
N/A
Description
Fetches the line of data or code (instructions’ bytes) from memory that contains the byte specified with the source
operand to a location in the cache hierarchy specified by a locality hint:
• T0 (temporal data)-prefetch data into all levels of the cache hierarchy.
• T1 (temporal data with respect to first level cache misses)-prefetch data into level 2 cache and higher.
• T2 (temporal data with respect to second level cache misses)-prefetch data into level 3 cache and higher, or
an implementation-specific choice.
• NTA (non-temporal data with respect to all cache levels)-prefetch data into non-temporal cache structure and
into a location close to the processor, minimizing cache pollution.
• IT0 (temporal code)-prefetch code into all levels of the cache hierarchy.
• IT1 (temporal code with respect to first level cache misses)-prefetch code into all but the first-level of the
cache hierarchy.
The source operand is a byte memory location. (The locality hints are encoded into the machine level instruction
using bits 3 through 5 of the ModR/M byte.) Some locality hints may prefetch only for RIP-relative memory
addresses; see additional details below. The address to prefetch is NextRIP + 32-bit displacement, where NextRIP
is the first byte of the instruction that follows the prefetch instruction itself.
If the line selected is already present in the cache hierarchy at a level closer to the processor, no data movement
occurs. Prefetches from uncacheable or WC memory are ignored.
The PREFETCHh instruction is merely a hint and does not affect program behavior. If executed, this instruction
moves data closer to the processor in anticipation of future use.
The implementation of prefetch locality hints is implementation-dependent, and can be overloaded or ignored by a
processor implementation. The amount of data or code lines prefetched is also processor implementation-depen-
dent. It will, however, be a minimum of 32 bytes. Additional details of the implementation-dependent locality hints
are described in Section 7.4 of Intel® 64 and IA-32 Architectures Optimization Reference Manual.
It should be noted that processors are free to speculatively fetch and cache data from system memory regions that
are assigned a memory-type that permits speculative reads (that is, the WB, WC, and WT memory types). A
PREFETCHh-Prefetch Data Into Caches
Vol. 2B
4-414
PREFETCHh instruction is considered a hint to this speculative behavior. Because this speculative fetching can occur
at any time and is not tied to instruction execution, a PREFETCHh instruction is not ordered with respect to the
fence instructions (MFENCE, SFENCE, and LFENCE) or locked memory references. A PREFETCHh instruction is also
unordered with respect to CLFLUSH and CLFLUSHOPT instructions, other PREFETCHh instructions, or any other
general instruction. It is ordered with respect to serializing instructions such as CPUID, WRMSR, OUT, and MOV CR.
PREFETCHIT0/1 can be used in 64-bit mode with RIP-relative addressing; they remain NOPs otherwise. For optimal
performance, the addresses used with these instructions should be the starting byte of a real instruction.
PREFETCHIT0/1 instructions are enumerated by CPUID.07H.01H:EDX.PREFETCHI[14].The encodings remain NOPs
in processors that do not enumerate these instructions.
Operation
FETCH (m8);
Intel C/C++ Compiler Intrinsic Equivalent
void _mm_prefetch(char *p, int i)
The argument “*p” gives the address of the byte (and corresponding cache line) to be prefetched. The value “i” gives a constant
(_MM_HINT_T0, _MM_HINT_T1, _MM_HINT_T2, _MM_HINT_NTA, _MM_HINT_IT0, or _MM_HINT_IT1) that specifies the type of
prefetch operation to be performed.
Numeric Exceptions
None.
Exceptions (All Operating Modes)
#UD
If the LOCK prefix is used.
PREFETCHh-Prefetch Data Into Caches
Vol. 2B
4-415
PREFETCHW-Prefetch Data Into Caches in Anticipation of a Write
Opcode/
Op/
64/32 bit
CPUID
Description
Instruction
En
Mode
Feature Flag
Support
0F 0D /1
M
V/V
PREFETCHW
Move data from m8 closer to the processor in anticipation of a
PREFETCHW m8
write.
Instruction Operand Encoding
Op/En
Operand 1
Operand 2
Operand 3
Operand 4
M
ModRM:r/m (r)
N/A
N/A
N/A
Description
Fetches the cache line of data from memory that contains the byte specified with the source operand to a location
in the 1st or 2nd level cache and invalidates other cached instances of the line.
The source operand is a byte memory location. If the line selected is already present in the lowest level cache and
is already in an exclusively owned state, no data movement occurs. Prefetches from non-writeback memory are
ignored.
The PREFETCHW instruction is merely a hint and does not affect program behavior. If executed, this instruction
moves data closer to the processor and invalidates other cached copies in anticipation of the line being written to
in the future.
The characteristic of prefetch locality hints is implementation-dependent, and can be overloaded or ignored by a
processor implementation. The amount of data prefetched is also processor implementation-dependent. It will,
however, be a minimum of 32 bytes. Additional details of the implementation-dependent locality hints are
described in Section 7.4 of Intel® 64 and IA-32 Architectures Optimization Reference Manual.
It should be noted that processors are free to speculatively fetch and cache data with exclusive ownership from
system memory regions that permit such accesses (that is, the WB memory type). A PREFETCHW instruction is
considered a hint to this speculative behavior. Because this speculative fetching can occur at any time and is not
tied to instruction execution, a PREFETCHW instruction is not ordered with respect to the fence instructions
(MFENCE, SFENCE, and LFENCE) or locked memory references. A PREFETCHW instruction is also unordered with
respect to CLFLUSH and CLFLUSHOPT instructions, other PREFETCHW instructions, or any other general instruction
It is ordered with respect to serializing instructions such as CPUID, WRMSR, OUT, and MOV CR.
This instruction's operation is the same in non-64-bit modes and 64-bit mode.
Operation
FETCH_WITH_EXCLUSIVE_OWNERSHIP (m8);
Flags Affected
None.
C/C++ Compiler Intrinsic Equivalent
void _m_prefetchw( void * );
Protected Mode Exceptions
#UD
If the LOCK prefix is used.
Real-Address Mode Exceptions
#UD
If the LOCK prefix is used.
PREFETCHW-Prefetch Data Into Caches in Anticipation of a Write
Vol. 2B
4-416
Virtual-8086 Mode Exceptions
#UD
If the LOCK prefix is used.
Compatibility Mode Exceptions
#UD
If the LOCK prefix is used.
64-Bit Mode Exceptions
#UD
If the LOCK prefix is used.
PREFETCHW-Prefetch Data Into Caches in Anticipation of a Write
Vol. 2B
4-417
PSADBW-Compute Sum of Absolute Differences
Opcode/
Op/
64/32 bit
CPUID Feature
Description
Instruction
En
Mode
Flag
Support
NP 0F F6 /r1
A
V/V
SSE
Computes the absolute differences of the packed
unsigned byte integers from mm2 /m64 and
PSADBW mm1, mm2/m64
mm1; differences are then summed to produce an
unsigned word integer result.
66 0F F6 /r
A
V/V
SSE2
Computes the absolute differences of the packed
unsigned byte integers from xmm2 /m128 and
PSADBW xmm1, xmm2/m128
xmm1; the 8 low differences and 8 high
differences are then summed separately to
produce two unsigned word integer results.
VEX.128.66.0F.WIG F6 /r
B
V/V
AVX
Computes the absolute differences of the packed
unsigned byte integers from xmm3 /m128 and
VPSADBW xmm1, xmm2, xmm3/m128
xmm2; the 8 low differences and 8 high
differences are then summed separately to
produce two unsigned word integer results.
VEX.256.66.0F.WIG F6 /r
B
V/V
AVX2
Computes the absolute differences of the packed
unsigned byte integers from ymm3 /m256 and
VPSADBW ymm1, ymm2, ymm3/m256
ymm2; then each consecutive 8 differences are
summed separately to produce four unsigned
word integer results.
EVEX.128.66.0F.WIG F6 /r
C
V/V
(AVX512VL AND
Computes the absolute differences of the packed
VPSADBW xmm1, xmm2, xmm3/m128
AVX512BW) OR
unsigned byte integers from xmm3 /m128 and
AVX10.1
xmm2; then each consecutive 8 differences are
summed separately to produce two unsigned
word integer results.
EVEX.256.66.0F.WIG F6 /r
C
V/V
(AVX512VL AND
Computes the absolute differences of the packed
VPSADBW ymm1, ymm2, ymm3/m256
AVX512BW) OR
unsigned byte integers from ymm3 /m256 and
AVX10.1
ymm2; then each consecutive 8 differences are
summed separately to produce four unsigned
word integer results.
EVEX.512.66.0F.WIG F6 /r
C
V/V
AVX512BW
Computes the absolute differences of the packed
VPSADBW zmm1, zmm2, zmm3/m512
OR AVX10.1
unsigned byte integers from zmm3 /m512 and
zmm2; then each consecutive 8 differences are
summed separately to produce eight unsigned
word integer results.
NOTES:
1. See note in Section 2.5, “Intel® AVX and Intel® SSE Instruction Exception Classification,” in the Intel® 64 and IA-32 Architectures Soft-
ware Developer’s Manual, Volume 2A, and Section 25.25.3, “Exception Conditions of Legacy SIMD Instructions Operating on MMX
Registers,” in the Intel® 64 and IA-32 Architectures Software Developer’s Manual, Volume 3B.
Instruction Operand Encoding
Op/En
Tuple Type
Operand 1
Operand 2
Operand 3
Operand 4
A
N/A
ModRM:reg (r, w)
ModRM:r/m (r)
N/A
N/A
B
N/A
ModRM:reg (w)
VEX.vvvv (r)
ModRM:r/m (r)
N/A
C
Full Mem
ModRM:reg (w)
EVEX.vvvv
ModRM:r/m (r)
N/A
PSADBW-Compute Sum of Absolute Differences
Vol. 2B
4-418
Description
Computes the absolute value of the difference of 8 unsigned byte integers from the source operand (second
operand) and from the destination operand (first operand). These 8 differences are then summed to produce an
unsigned word integer result that is stored in the destination operand. Figure 4-14 shows the operation of the
PSADBW instruction when using 64-bit operands.
When operating on 64-bit operands, the word integer result is stored in the low word of the destination operand,
and the remaining bytes in the destination operand are cleared to all 0s.
When operating on 128-bit operands, two packed results are computed. Here, the 8 low-order bytes of the source
and destination operands are operated on to produce a word result that is stored in the low word of the destination
operand, and the 8 high-order bytes are operated on to produce a word result that is stored in bits 64 through 79
of the destination operand. The remaining bytes of the destination operand are cleared.
For 256-bit version, the third group of 8 differences are summed to produce an unsigned word in bits[143:128] of
the destination register and the fourth group of 8 differences are summed to produce an unsigned word in
bits[207:192] of the destination register. The remaining words of the destination are set to 0.
For 512-bit version, the fifth group result is stored in bits [271:256] of the destination. The result from the sixth
group is stored in bits [335:320]. The results for the seventh and eighth group are stored respectively in bits
[399:384] and bits [463:447], respectively. The remaining bits in the destination are set to 0.
In 64-bit mode and not encoded by VEX/EVEX prefix, using a REX prefix in the form of REX.R permits this instruc-
tion to access additional registers (XMM8-XMM15).
Legacy SSE version: The source operand can be an MMX technology register or a 64-bit memory location. The
destination operand is an MMX technology register.
128-bit Legacy SSE version: The first source operand and destination register are XMM registers. The second
source operand is an XMM register or a 128-bit memory location. Bits (MAXVL-1:128) of the corresponding ZMM
destination register remain unchanged.
VEX.128 and EVEX.128 encoded versions: The first source operand and destination register are XMM registers. The
second source operand is an XMM register or a 128-bit memory location. Bits (MAXVL-1:128) of the corresponding
ZMM register are zeroed.
VEX.256 and EVEX.256 encoded versions: The first source operand and destination register are YMM registers. The
second source operand is an YMM register or a 256-bit memory location. Bits (MAXVL-1:256) of the corresponding
ZMM register are zeroed.
EVEX.512 encoded version: The first source operand and destination register are ZMM registers. The second
source operand is a ZMM register or a 512-bit memory location.
SRC
X7
X6
X5
X4
X3
X2
X1
X0
DEST
Y7
Y6
Y5
Y4
Y3
Y2
Y1
Y0
TEMP
ABS(X7:Y7)
ABS(X6:Y6)
ABS(X5:Y5)
ABS(X4:Y4)
ABS(X3:Y3)
ABS(X2:Y2)
ABS(X1:Y1)
ABS(X0:Y0)
DEST
00H
00H
00H
00H
00H
00H
SUM(TEMP7...TEMP0)
Figure 4-14. PSADBW Instruction Operation Using 64-bit Operands
PSADBW-Compute Sum of Absolute Differences
Vol. 2B
4-419
Operation
VPSADBW (EVEX Encoded Versions)
VL = 128, 256, 512
TEMP0 := ABS(SRC1[7:0] - SRC2[7:0])
(* Repeat operation for bytes 1 through 15 *)
TEMP15 := ABS(SRC1[127:120] - SRC2[127:120])
DEST[15:0] := SUM(TEMP0:TEMP7)
DEST[63:16] := 000000000000H
DEST[79:64] := SUM(TEMP8:TEMP15)
DEST[127:80] := 00000000000H
IF VL >= 256
(* Repeat operation for bytes 16 through 31*)
TEMP31 := ABS(SRC1[255:248] - SRC2[255:248])
DEST[143:128] := SUM(TEMP16:TEMP23)
DEST[191:144] := 000000000000H
DEST[207:192] := SUM(TEMP24:TEMP31)
DEST[223:208] := 00000000000H
FI;
IF VL >= 512
(* Repeat operation for bytes 32 through 63*)
TEMP63 := ABS(SRC1[511:504] - SRC2[511:504])
DEST[271:256] := SUM(TEMP0:TEMP7)
DEST[319:272] := 000000000000H
DEST[335:320] := SUM(TEMP8:TEMP15)
DEST[383:336] := 00000000000H
DEST[399:384] := SUM(TEMP16:TEMP23)
DEST[447:400] := 000000000000H
DEST[463:448] := SUM(TEMP24:TEMP31)
DEST[511:464] := 00000000000H
FI;
DEST[MAXVL-1:VL] := 0
VPSADBW (VEX.256 Encoded Version)
TEMP0 := ABS(SRC1[7:0] - SRC2[7:0])
(* Repeat operation for bytes 2 through 30*)
TEMP31 := ABS(SRC1[255:248] - SRC2[255:248])
DEST[15:0] := SUM(TEMP0:TEMP7)
DEST[63:16] := 000000000000H
DEST[79:64] := SUM(TEMP8:TEMP15)
DEST[127:80] := 00000000000H
DEST[143:128] := SUM(TEMP16:TEMP23)
DEST[191:144] := 000000000000H
DEST[207:192] := SUM(TEMP24:TEMP31)
DEST[223:208] := 00000000000H
DEST[MAXVL-1:256] := 0
PSADBW-Compute Sum of Absolute Differences
Vol. 2B
4-420
VPSADBW (VEX.128 Encoded Version)
TEMP0 := ABS(SRC1[7:0] - SRC2[7:0])
(* Repeat operation for bytes 2 through 14 *)
TEMP15 := ABS(SRC1[127:120] - SRC2[127:120])
DEST[15:0] := SUM(TEMP0:TEMP7)
DEST[63:16] := 000000000000H
DEST[79:64] := SUM(TEMP8:TEMP15)
DEST[127:80] := 00000000000H
DEST[MAXVL-1:128] := 0
PSADBW (128-bit Legacy SSE Version)
TEMP0 := ABS(DEST[7:0] - SRC[7:0])
(* Repeat operation for bytes 2 through 14 *)
TEMP15 := ABS(DEST[127:120] - SRC[127:120])
DEST[15:0] := SUM(TEMP0:TEMP7)
DEST[63:16] := 000000000000H
DEST[79:64] := SUM(TEMP8:TEMP15)
DEST[127:80] := 00000000000
DEST[MAXVL-1:128] (Unmodified)
PSADBW (64-bit Operand)
TEMP0 := ABS(DEST[7:0] - SRC[7:0])
(* Repeat operation for bytes 2 through 6 *)
TEMP7 := ABS(DEST[63:56] - SRC[63:56])
DEST[15:0] := SUM(TEMP0:TEMP7)
DEST[63:16] := 000000000000H
Intel C/C++ Compiler Intrinsic Equivalent
VPSADBW __m512i _mm512_sad_epu8( __m512i a, __m512i b)
PSADBW __m64 _mm_sad_pu8(__m64 a,__m64 b)
(V)PSADBW __m128i _mm_sad_epu8(__m128i a, __m128i b)
VPSADBW __m256i _mm256_sad_epu8( __m256i a, __m256i b)
Flags Affected
None.
SIMD Floating-Point Exceptions
None.
Other Exceptions
Non-EVEX-encoded instruction, see Table 2-21, “Type 4 Class Exception Conditions.”
EVEX-encoded instruction, see Exceptions Type E4NF.nb in Table 2-52, “Type E4NF Class Exception Conditions.”
PSADBW-Compute Sum of Absolute Differences
Vol. 2B
4-421
PSHUFB-Packed Shuffle Bytes
Opcode/
Op/
64/32 bit
CPUID Feature
Description
Instruction
En
Mode
Flag
Support
NP 0F 38 00 /r1
A
V/V
SSSE3
Shuffle bytes in mm1 according to contents of
mm2/m64.
PSHUFB mm1, mm2/m64
66 0F 38 00 /r
A
V/V
SSSE3
Shuffle bytes in xmm1 according to contents of
xmm2/m128.
PSHUFB xmm1, xmm2/m128
VEX.128.66.0F38.WIG 00 /r
B
V/V
AVX
Shuffle bytes from xmm2 into xmm1 according
VPSHUFB xmm1, xmm2, xmm3/m128
to contents of xmm3/m128.
VEX.256.66.0F38.WIG 00 /r
B
V/V
AVX2
Shuffle bytes from ymm2 into ymm1 according
to contents of ymm3/m256.
VPSHUFB ymm1, ymm2, ymm3/m256
EVEX.128.66.0F38.WIG 00 /r
C
V/V
(AVX512VL AND
Shuffle bytes from xmm2 into xmm1 according
VPSHUFB xmm1 {k1}{z}, xmm2, xmm3/m128
AVX512BW) OR
to contents of xmm3/m128 under write mask
AVX10.1
k1.
EVEX.256.66.0F38.WIG 00 /r
C
V/V
(AVX512VL AND
Shuffle bytes from ymm2 into ymm1 according
VPSHUFB ymm1 {k1}{z}, ymm2, ymm3/m256
AVX512BW) OR
to contents of ymm3/m256 under write mask
AVX10.1
k1.
EVEX.512.66.0F38.WIG 00 /r
C
V/V
AVX512BW
Shuffle bytes from zmm2 into zmm1 according
VPSHUFB zmm1 {k1}{z}, zmm2, zmm3/m512
OR AVX10.1
to contents of zmm3/m512 under write mask
k1.
NOTES:
1. See note in Section 2.5, “Intel® AVX and Intel® SSE Instruction Exception Classification,” in the Intel® 64 and IA-32 Architectures Soft-
ware Developer’s Manual, Volume 2A, and Section 25.25.3, “Exception Conditions of Legacy SIMD Instructions Operating on MMX
Registers,” in the Intel® 64 and IA-32 Architectures Software Developer’s Manual, Volume 3B.
Instruction Operand Encoding
Op/En
Tuple Type
Operand 1
Operand 2
Operand 3
Operand 4
A
N/A
ModRM:reg (r, w)
ModRM:r/m (r)
N/A
N/A
B
N/A
ModRM:reg (w)
VEX.vvvv (r)
ModRM:r/m (r)
N/A
C
Full Mem
ModRM:reg (w)
EVEX.vvvv (r)
ModRM:r/m (r)
N/A
Description
PSHUFB (with no VEX or EVEX prefix) performs an in-place shuffle of bytes in the destination operand (the first
operand) according to the shuffle control mask in the source operand (the second operand). The instruction
permutes the data in the destination operand, leaving the shuffle mask unaffected. If the most significant bit
(bit[7]) of each byte of the shuffle control mask is set, then constant zero is written in the result byte. Each byte in
the shuffle control mask forms an index to permute the corresponding byte in the destination operand. The value
of each index is the least significant 3 bits (64-bit operation) or 4 bits (128-bit operation) of the shuffle control
byte. See Figure 4-15 for an example for 64-bit operation.
The 128-bit forms of PSHUFB leave bits MAXVL-1:128 of the destination register unchanged. A 128-bit memory
operand must be aligned on a 16-byte boundary or a general-protection exception (#GP) will be generated. In 64-
bit mode, the REX prefix can be used to access XMM8-XMM15.
The following items apply to VPSHUFB, encoded with a VEX or EVEX prefix:
• Each of these forms uses shuffle control bytes in its second source operand to select which bytes in the first
source operand to copy to the destination operand.
PSHUFB-Packed Shuffle Bytes
Vol. 2B
4-422
• These forms operate in one, two, or four 16-byte “lanes.” As with the 128-bit form of PSHUFB (above), the low
4 bits of each shuffle control byte determines which of 16 bytes in a source lane is copied to the appropriate
byte in the corresponding destination lane.
• The 128-bit and 256-bit versions of these forms zero upper bits in the destination register beyond the
instruction’s operand size.
• The EVEX-encoded versions update their destination conditionally with writemask k1.
Operation
PSHUFB (with 64-bit MMX operands)
TEMP := DEST
FOR destpos := 0 TO 7
shufbyte := SRC.byte[destpos];
IF shufbyte & 80H = 80H
THEN DEST.byte[destpos] := 0;
ELSE
srcpos := shufbyte & 07H;
DEST.byte[destpos] := TEMP.byte[srcpos];
FI;
PSHUFB (with 128-bit SSE operands)
TEMP := DEST;
FOR destpos := 0 TO 15
shufbyte := SRC.byte[destpos];
IF shufbyte & 80H = 80H
THEN DEST.byte[destpos] := 0;
ELSE
srcpos := shufbyte & 0FH;
DEST.byte[destpos] := TEMP.byte[srcpos];
FI;
VPSHUFB (VEX.128 encoded version)
FOR destpos := 0 TO 15
shufbyte := SRC2.byte[destpos];
IF shufbyte & 80H = 80H
THEN DEST.byte[destpos] := 0;
ELSE
srcpos := shufbyte & 0FH;
DEST.byte[destpos] := SRC1.byte[srcpos];
FI;
DEST[MAXVL-1:128] := 0;
VPSHUFB (VEX.256 encoded version)
FOR lane := 0 to 1
FOR lanepos := 0 TO 15
destpos := 16 * lane + lanepos;
shufbyte := SRC2.byte[destpos];
IF shufbyte & 80H = 80H
THEN DEST.byte[destpos] := 0;
ELSE
srcpos := 16 * lane + (shufbyte & 0FH);
DEST.byte[destpos] := SRC1.byte[srcpos];
FI;
DEST[MAXVL-1:256] := 0;
PSHUFB-Packed Shuffle Bytes
Vol. 2B
4-423
VPSHUFB (EVEX encoded versions)
// VL is 128, 256, or 512, depending on instruction encoding
// no masking if EVEX.aaa = 0; zeroing if EVEX.z = 1
FOR lane := 0 to VL/128 - 1
FOR lanepos := 0 TO 15
destpos := 16 * lane + lanepos;
IF no masking OR k[destpos] = 1
// using selected bit from k register
THEN
shufbyte := SRC2.byte[destpos];
IF shufbyte & 80H = 80H
THEN DEST.byte[destpos] := 0;
ELSE
srcpos := 16 * lane + (shufbyte & 0FH);
DEST.byte[destpos] := SRC1.byte[srcpos];
FI;
ELSE IF zeroing
// if not zeroing, DEST.byte[destpos] is unchanged
THEN DEST.byte[destpos] := 0;
FI;
DEST[MAXVL-1:VL] := 0;
MM2
07H
07H
FFH
80H
01H
00H
00H
00H
MM1
04H
01H
07H
03H
02H
02H
FFH
01H
MM1
04H
04H
00H
00H
FFH
01H
01H
01H
Figure 4-15. PSHUFB with 64-Bit Operands
Intel C/C++ Compiler Intrinsic Equivalent
VPSHUFB __m512i _mm512_shuffle_epi8(__m512i a, __m512i b);
VPSHUFB __m512i _mm512_mask_shuffle_epi8(__m512i s, __mmask64 k, __m512i a, __m512i b);
VPSHUFB __m512i _mm512_maskz_shuffle_epi8( __mmask64 k, __m512i a, __m512i b);
VPSHUFB __m256i _mm256_mask_shuffle_epi8(__m256i s, __mmask32 k, __m256i a, __m256i b);
VPSHUFB __m256i _mm256_maskz_shuffle_epi8( __mmask32 k, __m256i a, __m256i b);
VPSHUFB __m128i _mm_mask_shuffle_epi8(__m128i s, __mmask16 k, __m128i a, __m128i b);
VPSHUFB __m128i _mm_maskz_shuffle_epi8( __mmask16 k, __m128i a, __m128i b);
PSHUFB: __m64 _mm_shuffle_pi8 (__m64 a, __m64 b)
(V)PSHUFB: __m128i _mm_shuffle_epi8 (__m128i a, __m128i b)
VPSHUFB:__m256i _mm256_shuffle_epi8(__m256i a, __m256i b)
SIMD Floating-Point Exceptions
None.
PSHUFB-Packed Shuffle Bytes
Vol. 2B
4-424
Other Exceptions
Non-EVEX-encoded instruction, see Table 2-21, “Type 4 Class Exception Conditions.”
EVEX-encoded instruction, see Exceptions Type E4NF.nb in Table 2-52, “Type E4NF Class Exception Conditions.”
PSHUFB-Packed Shuffle Bytes
Vol. 2B
4-425
PSHUFD-Shuffle Packed Doublewords
Opcode/
Op/
64/32 bit
CPUID Feature
Description
Instruction
En
Mode
Flag
Support
66 0F 70 /r ib
A
V/V
SSE2
Shuffle the doublewords in xmm2/m128 based on
the encoding in imm8 and store the result in xmm1.
PSHUFD xmm1, xmm2/m128, imm8
VEX.128.66.0F.WIG 70 /r ib
A
V/V
AVX
Shuffle the doublewords in xmm2/m128 based on
the encoding in imm8 and store the result in xmm1.
VPSHUFD xmm1, xmm2/m128, imm8
VEX.256.66.0F.WIG 70 /r ib
A
V/V
AVX2
Shuffle the doublewords in ymm2/m256 based on
the encoding in imm8 and store the result in ymm1.
VPSHUFD ymm1, ymm2/m256, imm8
EVEX.128.66.0F.W0 70 /r ib
B
V/V
(AVX512VL AND
Shuffle the doublewords in xmm2/m128/m32bcst
VPSHUFD xmm1 {k1}{z},
AVX512F) OR
based on the encoding in imm8 and store the result
xmm2/m128/m32bcst, imm8
AVX10.1
in xmm1 using writemask k1.
EVEX.256.66.0F.W0 70 /r ib
B
V/V
(AVX512VL AND
Shuffle the doublewords in ymm2/m256/m32bcst
VPSHUFD ymm1 {k1}{z},
AVX512F) OR
based on the encoding in imm8 and store the result
ymm2/m256/m32bcst, imm8
AVX10.1
in ymm1 using writemask k1.
EVEX.512.66.0F.W0 70 /r ib
B
V/V
AVX512F
Shuffle the doublewords in zmm2/m512/m32bcst
VPSHUFD zmm1 {k1}{z},
OR AVX10.1
based on the encoding in imm8 and store the result
zmm2/m512/m32bcst, imm8
in zmm1 using writemask k1.
Instruction Operand Encoding
Op/En
Tuple Type
Operand 1
Operand 2
Operand 3
Operand 4
A
N/A
ModRM:reg (w)
ModRM:r/m (r)
imm8
N/A
B
Full
ModRM:reg (w)
ModRM:r/m (r)
imm8
N/A
Description
Copies doublewords from source operand (second operand) and inserts them in the destination operand (first
operand) at the locations selected with the order operand (third operand). Figure 4-16 shows the operation of the
256-bit VPSHUFD instruction and the encoding of the order operand. Each 2-bit field in the order operand selects
the contents of one doubleword location within a 128-bit lane and copy to the target element in the destination
operand. For example, bits 0 and 1 of the order operand targets the first doubleword element in the low and high
128-bit lane of the destination operand for 256-bit VPSHUFD. The encoded value of bits 1:0 of the order operand
(see the field encoding in Figure 4-16) determines which doubleword element (from the respective 128-bit lane) of
the source operand will be copied to doubleword 0 of the destination operand.
For 128-bit operation, only the low 128-bit lane are operative. The source operand can be an XMM register or a
128-bit memory location. The destination operand is an XMM register. The order operand is an 8-bit immediate.
Note that this instruction permits a doubleword in the source operand to be copied to more than one doubleword
location in the destination operand.
PSHUFD-Shuffle Packed Doublewords
Vol. 2B
4-426
SRC
X7
X6
X5
X4
X3
X2
X1
X0
DEST
Y7
Y6
Y5
Y4
Y3
Y2
Y1
Y0
Encoding
00B - X4
Encoding
00B - X0
of Fields in
01B - X5
ORDER
of Fields in
01B - X1
ORDER
10B - X6
ORDER
10B - X2
Operand
11B - X7
7
6 5
4 3
2
1
0
Operand
11B - X3
Figure 4-16. 256-bit VPSHUFD Instruction Operation
The source operand can be an XMM register or a 128-bit memory location. The destination operand is an XMM
register. The order operand is an 8-bit immediate. Note that this instruction permits a doubleword in the source
operand to be copied to more than one doubleword location in the destination operand.
In 64-bit mode and not encoded in VEX/EVEX, using REX.R permits this instruction to access XMM8-XMM15.
128-bit Legacy SSE version: Bits (MAXVL-1:128) of the corresponding YMM destination register remain
unchanged.
VEX.128 encoded version: The source operand can be an XMM register or a 128-bit memory location. The destina-
tion operand is an XMM register. Bits (MAXVL-1:128) of the corresponding ZMM register are zeroed.
VEX.256 encoded version: The source operand can be an YMM register or a 256-bit memory location. The destina-
tion operand is an YMM register. Bits (MAXVL-1:256) of the corresponding ZMM register are zeroed. Bits (255-
1:128) of the destination stores the shuffled results of the upper 16 bytes of the source operand using the imme-
diate byte as the order operand.
EVEX encoded version: The source operand can be an ZMM/YMM/XMM register, a 512/256/128-bit memory loca-
tion, or a 512/256/128-bit vector broadcasted from a 32-bit memory location. The destination operand is a
ZMM/YMM/XMM register updated according to the writemask.
Each 128-bit lane of the destination stores the shuffled results of the respective lane of the source operand using
the immediate byte as the order operand.
Note: EVEX.vvvv and VEX.vvvv are reserved and must be 1111b otherwise instructions will #UD.
Operation
PSHUFD (128-bit Legacy SSE Version)
DEST[31:0] := (SRC >> (ORDER[1:0] * 32))[31:0];
DEST[63:32] := (SRC >> (ORDER[3:2] * 32))[31:0];
DEST[95:64] := (SRC >> (ORDER[5:4] * 32))[31:0];
DEST[127:96] := (SRC >> (ORDER[7:6] * 32))[31:0];
DEST[MAXVL-1:128] (Unmodified)
VPSHUFD (VEX.128 Encoded Version)
DEST[31:0] := (SRC >> (ORDER[1:0] * 32))[31:0];
DEST[63:32] := (SRC >> (ORDER[3:2] * 32))[31:0];
DEST[95:64] := (SRC >> (ORDER[5:4] * 32))[31:0];
DEST[127:96] := (SRC >> (ORDER[7:6] * 32))[31:0];
DEST[MAXVL-1:128] := 0
PSHUFD-Shuffle Packed Doublewords
Vol. 2B
4-427
VPSHUFD (VEX.256 Encoded Version)
DEST[31:0] := (SRC[127:0] >> (ORDER[1:0] * 32))[31:0];
DEST[63:32] := (SRC[127:0] >> (ORDER[3:2] * 32))[31:0];
DEST[95:64] := (SRC[127:0] >> (ORDER[5:4] * 32))[31:0];
DEST[127:96] := (SRC[127:0] >> (ORDER[7:6] * 32))[31:0];
DEST[159:128] := (SRC[255:128] >> (ORDER[1:0] * 32))[31:0];
DEST[191:160] := (SRC[255:128] >> (ORDER[3:2] * 32))[31:0];
DEST[223:192] := (SRC[255:128] >> (ORDER[5:4] * 32))[31:0];
DEST[255:224] := (SRC[255:128] >> (ORDER[7:6] * 32))[31:0];
DEST[MAXVL-1:256] := 0
VPSHUFD (EVEX Encoded Versions)
(KL, VL) = (4, 128), (8, 256), (16, 512)
FOR j := 0 TO KL-1
i := j * 32
IF (EVEX.b = 1) AND (SRC *is memory*)
THEN TMP_SRC[i+31:i] := SRC[31:0]
ELSE TMP_SRC[i+31:i] := SRC[i+31:i]
FI;
ENDFOR;
IF VL >= 128
TMP_DEST[31:0] := (TMP_SRC[127:0] >> (ORDER[1:0] * 32))[31:0];
TMP_DEST[63:32] := (TMP_SRC[127:0] >> (ORDER[3:2] * 32))[31:0];
TMP_DEST[95:64] := (TMP_SRC[127:0] >> (ORDER[5:4] * 32))[31:0];
TMP_DEST[127:96] := (TMP_SRC[127:0] >> (ORDER[7:6] * 32))[31:0];
FI;
IF VL >= 256
TMP_DEST[159:128] := (TMP_SRC[255:128] >> (ORDER[1:0] * 32))[31:0];
TMP_DEST[191:160] := (TMP_SRC[255:128] >> (ORDER[3:2] * 32))[31:0];
TMP_DEST[223:192] := (TMP_SRC[255:128] >> (ORDER[5:4] * 32))[31:0];
TMP_DEST[255:224] := (TMP_SRC[255:128] >> (ORDER[7:6] * 32))[31:0];
FI;
IF VL >= 512
TMP_DEST[287:256] := (TMP_SRC[383:256] >> (ORDER[1:0] * 32))[31:0];
TMP_DEST[319:288] := (TMP_SRC[383:256] >> (ORDER[3:2] * 32))[31:0];
TMP_DEST[351:320] := (TMP_SRC[383:256] >> (ORDER[5:4] * 32))[31:0];
TMP_DEST[383:352] := (TMP_SRC[383:256] >> (ORDER[7:6] * 32))[31:0];
TMP_DEST[415:384] := (TMP_SRC[511:384] >> (ORDER[1:0] * 32))[31:0];
TMP_DEST[447:416] := (TMP_SRC[511:384] >> (ORDER[3:2] * 32))[31:0];
TMP_DEST[479:448] := (TMP_SRC[511:384] >> (ORDER[5:4] * 32))[31:0];
TMP_DEST[511:480] := (TMP_SRC[511:384] >> (ORDER[7:6] * 32))[31:0];
FI;
FOR j := 0 TO KL-1
i := j * 32
IF k1[j] OR *no writemask*
THEN DEST[i+31:i] := TMP_DEST[i+31:i]
ELSE
IF *merging-masking*
; merging-masking
THEN *DEST[i+31:i] remains unchanged*
ELSE *zeroing-masking*
; zeroing-masking
DEST[i+31:i] := 0
FI
FI;
ENDFOR
PSHUFD-Shuffle Packed Doublewords
Vol. 2B
4-428
DEST[MAXVL-1:VL] := 0
Intel C/C++ Compiler Intrinsic Equivalent
VPSHUFD __m512i _mm512_shuffle_epi32(__m512i a, int n );
VPSHUFD __m512i _mm512_mask_shuffle_epi32(__m512i s, __mmask16 k, __m512i a, int n );
VPSHUFD __m512i _mm512_maskz_shuffle_epi32( __mmask16 k, __m512i a, int n );
VPSHUFD __m256i _mm256_mask_shuffle_epi32(__m256i s, __mmask8 k, __m256i a, int n );
VPSHUFD __m256i _mm256_maskz_shuffle_epi32( __mmask8 k, __m256i a, int n );
VPSHUFD __m128i _mm_mask_shuffle_epi32(__m128i s, __mmask8 k, __m128i a, int n );
VPSHUFD __m128i _mm_maskz_shuffle_epi32( __mmask8 k, __m128i a, int n );
(V)PSHUFD __m128i _mm_shuffle_epi32(__m128i a, int n)
VPSHUFD __m256i _mm256_shuffle_epi32(__m256i a, const int n)
Flags Affected
None.
SIMD Floating-Point Exceptions
None.
Other Exceptions
Non-EVEX-encoded instruction, see Table 2-21, “Type 4 Class Exception Conditions.”
EVEX-encoded instruction, see Table 2-52, “Type E4NF Class Exception Conditions.”
Additionally:
#UD
If VEX.vvvv ≠ 1111B or EVEX.vvvv ≠ 1111B.
PSHUFD-Shuffle Packed Doublewords
Vol. 2B
4-429
PSHUFHW-Shuffle Packed High Words
Opcode/
Op/
64/32 bit
CPUID Feature
Description
Instruction
En
Mode
Flag
Support
F3 0F 70 /r ib
A
V/V
SSE2
Shuffle the high words in xmm2/m128 based
on the encoding in imm8 and store the result in
PSHUFHW xmm1, xmm2/m128, imm8
xmm1.
VEX.128.F3.0F.WIG 70 /r ib
A
V/V
AVX
Shuffle the high words in xmm2/m128 based
on the encoding in imm8 and store the result in
VPSHUFHW xmm1, xmm2/m128, imm8
xmm1.
VEX.256.F3.0F.WIG 70 /r ib
A
V/V
AVX2
Shuffle the high words in ymm2/m256 based
on the encoding in imm8 and store the result in
VPSHUFHW ymm1, ymm2/m256, imm8
ymm1.
EVEX.128.F3.0F.WIG 70 /r ib
B
V/V
(AVX512VL AND
Shuffle the high words in xmm2/m128 based
VPSHUFHW xmm1 {k1}{z}, xmm2/m128,
AVX512BW) OR
on the encoding in imm8 and store the result in
imm8
AVX10.1
xmm1 under write mask k1.
EVEX.256.F3.0F.WIG 70 /r ib
B
V/V
(AVX512VL AND
Shuffle the high words in ymm2/m256 based
VPSHUFHW ymm1 {k1}{z}, ymm2/m256,
AVX512BW) OR
on the encoding in imm8 and store the result in
imm8
AVX10.1
ymm1 under write mask k1.
EVEX.512.F3.0F.WIG 70 /r ib
B
V/V
AVX512BW
Shuffle the high words in zmm2/m512 based
VPSHUFHW zmm1 {k1}{z}, zmm2/m512,
OR AVX10.1
on the encoding in imm8 and store the result in
imm8
zmm1 under write mask k1.
Instruction Operand Encoding
Op/En
Tuple Type
Operand 1
Operand 2
Operand 3
Operand 4
A
N/A
ModRM:reg (w)
ModRM:r/m (r)
imm8
N/A
B
Full Mem
ModRM:reg (w)
ModRM:r/m (r)
imm8
N/A
Description
Copies words from the high quadword of a 128-bit lane of the source operand and inserts them in the high quad-
word of the destination operand at word locations (of the respective lane) selected with the immediate operand.
This 256-bit operation is similar to the in-lane operation used by the 256-bit VPSHUFD instruction, which is illus-
trated in Figure 4-16. For 128-bit operation, only the low 128-bit lane is operative. Each 2-bit field in the immediate
operand selects the contents of one word location in the high quadword of the destination operand. The binary
encodings of the immediate operand fields select words (0, 1, 2 or 3, 4) from the high quadword of the source
operand to be copied to the destination operand. The low quadword of the source operand is copied to the low
quadword of the destination operand, for each 128-bit lane.
Note that this instruction permits a word in the high quadword of the source operand to be copied to more than one
word location in the high quadword of the destination operand.
In 64-bit mode and not encoded with VEX/EVEX, using a REX prefix in the form of REX.R permits this instruction to
access additional registers (XMM8-XMM15).
128-bit Legacy SSE version: The destination operand is an XMM register. The source operand can be an XMM
register or a 128-bit memory location. Bits (MAXVL-1:128) of the corresponding YMM destination register remain
unchanged.
VEX.128 encoded version: The destination operand is an XMM register. The source operand can be an XMM register
or a 128-bit memory location. Bits (MAXVL-1:128) of the destination YMM register are zeroed. VEX.vvvv is
reserved and must be 1111b, VEX.L must be 0, otherwise the instruction will #UD.
VEX.256 encoded version: The destination operand is an YMM register. The source operand can be an YMM register
or a 256-bit memory location.
PSHUFHW-Shuffle Packed High Words
Vol. 2B
4-430
EVEX encoded version: The destination operand is a ZMM/YMM/XMM registers. The source operand can be a
ZMM/YMM/XMM register, a 512/256/128-bit memory location. The destination is updated according to the write-
mask.
Note: In VEX encoded versions, VEX.vvvv is reserved and must be 1111b otherwise instructions will #UD.
Operation
PSHUFHW (128-bit Legacy SSE Version)
DEST[63:0] := SRC[63:0]
DEST[79:64] := (SRC >> (imm[1:0] *16))[79:64]
DEST[95:80] := (SRC >> (imm[3:2] * 16))[79:64]
DEST[111:96] := (SRC >> (imm[5:4] * 16))[79:64]
DEST[127:112] := (SRC >> (imm[7:6] * 16))[79:64]
DEST[MAXVL-1:128] (Unmodified)
VPSHUFHW (VEX.128 Encoded Version)
DEST[63:0] := SRC1[63:0]
DEST[79:64] := (SRC1 >> (imm[1:0] *16))[79:64]
DEST[95:80] := (SRC1 >> (imm[3:2] * 16))[79:64]
DEST[111:96] := (SRC1 >> (imm[5:4] * 16))[79:64]
DEST[127:112] := (SRC1 >> (imm[7:6] * 16))[79:64]
DEST[MAXVL-1:128] := 0
VPSHUFHW (VEX.256 Encoded Version)
DEST[63:0] := SRC1[63:0]
DEST[79:64] := (SRC1 >> (imm[1:0] *16))[79:64]
DEST[95:80] := (SRC1 >> (imm[3:2] * 16))[79:64]
DEST[111:96] := (SRC1 >> (imm[5:4] * 16))[79:64]
DEST[127:112] := (SRC1 >> (imm[7:6] * 16))[79:64]
DEST[191:128] := SRC1[191:128]
DEST[207192] := (SRC1 >> (imm[1:0] *16))[207:192]
DEST[223:208] := (SRC1 >> (imm[3:2] * 16))[207:192]
DEST[239:224] := (SRC1 >> (imm[5:4] * 16))[207:192]
DEST[255:240] := (SRC1 >> (imm[7:6] * 16))[207:192]
DEST[MAXVL-1:256] := 0
VPSHUFHW (EVEX Encoded Versions)
(KL, VL) = (8, 128), (16, 256), (32, 512)
IF VL >= 128
TMP_DEST[63:0] := SRC1[63:0]
TMP_DEST[79:64] := (SRC1 >> (imm[1:0] *16))[79:64]
TMP_DEST[95:80] := (SRC1 >> (imm[3:2] * 16))[79:64]
TMP_DEST[111:96] := (SRC1 >> (imm[5:4] * 16))[79:64]
TMP_DEST[127:112] := (SRC1 >> (imm[7:6] * 16))[79:64]
FI;
IF VL >= 256
TMP_DEST[191:128] := SRC1[191:128]
TMP_DEST[207:192] := (SRC1 >> (imm[1:0] *16))[207:192]
TMP_DEST[223:208] := (SRC1 >> (imm[3:2] * 16))[207:192]
TMP_DEST[239:224] := (SRC1 >> (imm[5:4] * 16))[207:192]
TMP_DEST[255:240] := (SRC1 >> (imm[7:6] * 16))[207:192]
FI;
IF VL >= 512
TMP_DEST[319:256] := SRC1[319:256]
TMP_DEST[335:320] := (SRC1 >> (imm[1:0] *16))[335:320]
PSHUFHW-Shuffle Packed High Words
Vol. 2B
4-431
TMP_DEST[351:336] := (SRC1 >> (imm[3:2] * 16))[335:320]
TMP_DEST[367:352] := (SRC1 >> (imm[5:4] * 16))[335:320]
TMP_DEST[383:368] := (SRC1 >> (imm[7:6] * 16))[335:320]
TMP_DEST[447:384] := SRC1[447:384]
TMP_DEST[463:448] := (SRC1 >> (imm[1:0] *16))[463:448]
TMP_DEST[479:464] := (SRC1 >> (imm[3:2] * 16))[463:448]
TMP_DEST[495:480] := (SRC1 >> (imm[5:4] * 16))[463:448]
TMP_DEST[511:496] := (SRC1 >> (imm[7:6] * 16))[463:448]
FI;
FOR j := 0 TO KL-1
i := j * 16
IF k1[j] OR *no writemask*
THEN DEST[i+15:i] := TMP_DEST[i+15:i];
ELSE
IF *merging-masking*
; merging-masking
THEN *DEST[i+15:i] remains unchanged*
ELSE *zeroing-masking*
; zeroing-masking
DEST[i+15:i] := 0
FI
FI;
ENDFOR
DEST[MAXVL-1:VL] := 0
Intel C/C++ Compiler Intrinsic Equivalent
VPSHUFHW __m512i _mm512_shufflehi_epi16(__m512i a, int n);
VPSHUFHW __m512i _mm512_mask_shufflehi_epi16(__m512i s, __mmask16 k, __m512i a, int n );
VPSHUFHW __m512i _mm512_maskz_shufflehi_epi16( __mmask16 k, __m512i a, int n );
VPSHUFHW __m256i _mm256_mask_shufflehi_epi16(__m256i s, __mmask8 k, __m256i a, int n );
VPSHUFHW __m256i _mm256_maskz_shufflehi_epi16( __mmask8 k, __m256i a, int n );
VPSHUFHW __m128i _mm_mask_shufflehi_epi16(__m128i s, __mmask8 k, __m128i a, int n );
VPSHUFHW __m128i _mm_maskz_shufflehi_epi16( __mmask8 k, __m128i a, int n );
(V)PSHUFHW __m128i _mm_shufflehi_epi16(__m128i a, int n)
VPSHUFHW __m256i _mm256_shufflehi_epi16(__m256i a, const int n)
Flags Affected
None.
SIMD Floating-Point Exceptions
None.
Other Exceptions
Non-EVEX-encoded instruction, see Table 2-21, “Type 4 Class Exception Conditions.”
EVEX-encoded instruction, see Exceptions Type E4NF.nb in Table 2-52, “Type E4NF Class Exception Conditions.”
Additionally:
#UD
If VEX.vvvv != 1111B, or EVEX.vvvv != 1111B.
PSHUFHW-Shuffle Packed High Words
Vol. 2B
4-432
PSHUFLW-Shuffle Packed Low Words
Opcode/
Op/
64/32 bit
CPUID Feature
Description
Instruction
En
Mode
Flag
Support
F2 0F 70 /r ib
A
V/V
SSE2
Shuffle the low words in xmm2/m128 based on
the encoding in imm8 and store the result in
PSHUFLW xmm1, xmm2/m128, imm8
xmm1.
VEX.128.F2.0F.WIG 70 /r ib
A
V/V
AVX
Shuffle the low words in xmm2/m128 based on
the encoding in imm8 and store the result in
VPSHUFLW xmm1, xmm2/m128, imm8
xmm1.
VEX.256.F2.0F.WIG 70 /r ib
A
V/V
AVX2
Shuffle the low words in ymm2/m256 based on
the encoding in imm8 and store the result in
VPSHUFLW ymm1, ymm2/m256, imm8
ymm1.
EVEX.128.F2.0F.WIG 70 /r ib
B
V/V
(AVX512VL AND
Shuffle the low words in xmm2/m128 based on
VPSHUFLW xmm1 {k1}{z}, xmm2/m128,
AVX512BW) OR
the encoding in imm8 and store the result in
imm8
AVX10.1
xmm1 under write mask k1.
EVEX.256.F2.0F.WIG 70 /r ib
B
V/V
(AVX512VL AND
Shuffle the low words in ymm2/m256 based on
VPSHUFLW ymm1 {k1}{z}, ymm2/m256,
AVX512BW) OR
the encoding in imm8 and store the result in
imm8
AVX10.1
ymm1 under write mask k1.
EVEX.512.F2.0F.WIG 70 /r ib
B
V/V
AVX512BW
Shuffle the low words in zmm2/m512 based on
VPSHUFLW zmm1 {k1}{z}, zmm2/m512,
OR AVX10.1
the encoding in imm8 and store the result in
imm8
zmm1 under write mask k1.
Instruction Operand Encoding
Op/En
Tuple Type
Operand 1
Operand 2
Operand 3
Operand 4
A
N/A
ModRM:reg (w)
ModRM:r/m (r)
imm8
N/A
B
Full Mem
ModRM:reg (w)
ModRM:r/m (r)
imm8
N/A
Description
Copies words from the low quadword of a 128-bit lane of the source operand and inserts them in the low quadword
of the destination operand at word locations (of the respective lane) selected with the immediate operand. The
256-bit operation is similar to the in-lane operation used by the 256-bit VPSHUFD instruction, which is illustrated
in Figure 4-16. For 128-bit operation, only the low 128-bit lane is operative. Each 2-bit field in the immediate
operand selects the contents of one word location in the low quadword of the destination operand. The binary
encodings of the immediate operand fields select words (0, 1, 2 or 3) from the low quadword of the source operand
to be copied to the destination operand. The high quadword of the source operand is copied to the high quadword
of the destination operand, for each 128-bit lane.
Note that this instruction permits a word in the low quadword of the source operand to be copied to more than one
word location in the low quadword of the destination operand.
In 64-bit mode and not encoded with VEX/EVEX, using a REX prefix in the form of REX.R permits this instruction to
access additional registers (XMM8-XMM15).
128-bit Legacy SSE version: The destination operand is an XMM register. The source operand can be an XMM
register or a 128-bit memory location. Bits (MAXVL-1:128) of the corresponding YMM destination register remain
unchanged.
VEX.128 encoded version: The destination operand is an XMM register. The source operand can be an XMM register
or a 128-bit memory location. Bits (MAXVL-1:128) of the destination YMM register are zeroed.
VEX.256 encoded version: The destination operand is an YMM register. The source operand can be an YMM register
or a 256-bit memory location.
EVEX encoded version: The destination operand is a ZMM/YMM/XMM registers. The source operand can be a
ZMM/YMM/XMM register, a 512/256/128-bit memory location. The destination is updated according to the write-
mask.
PSHUFLW-Shuffle Packed Low Words
Vol. 2B
4-433
Note: In VEX encoded versions, VEX.vvvv is reserved and must be 1111b otherwise instructions will #UD.
Operation
PSHUFLW (128-bit Legacy SSE Version)
DEST[15:0] := (SRC >> (imm[1:0] *16))[15:0]
DEST[31:16] := (SRC >> (imm[3:2] * 16))[15:0]
DEST[47:32] := (SRC >> (imm[5:4] * 16))[15:0]
DEST[63:48] := (SRC >> (imm[7:6] * 16))[15:0]
DEST[127:64] := SRC[127:64]
DEST[MAXVL-1:128] (Unmodified)
VPSHUFLW (VEX.128 Encoded Version)
DEST[15:0] := (SRC1 >> (imm[1:0] *16))[15:0]
DEST[31:16] := (SRC1 >> (imm[3:2] * 16))[15:0]
DEST[47:32] := (SRC1 >> (imm[5:4] * 16))[15:0]
DEST[63:48] := (SRC1 >> (imm[7:6] * 16))[15:0]
DEST[127:64] := SRC[127:64]
DEST[MAXVL-1:128] := 0
VPSHUFLW (VEX.256 Encoded Version)
DEST[15:0] := (SRC1 >> (imm[1:0] *16))[15:0]
DEST[31:16] := (SRC1 >> (imm[3:2] * 16))[15:0]
DEST[47:32] := (SRC1 >> (imm[5:4] * 16))[15:0]
DEST[63:48] := (SRC1 >> (imm[7:6] * 16))[15:0]
DEST[127:64] := SRC1[127:64]
DEST[143:128] := (SRC1 >> (imm[1:0] *16))[143:128]
DEST[159:144] := (SRC1 >> (imm[3:2] * 16))[143:128]
DEST[175:160] := (SRC1 >> (imm[5:4] * 16))[143:128]
DEST[191:176] := (SRC1 >> (imm[7:6] * 16))[143:128]
DEST[255:192] := SRC1[255:192]
DEST[MAXVL-1:256] := 0
VPSHUFLW (EVEX.U1.512 Encoded Version)
(KL, VL) = (8, 128), (16, 256), (32, 512)
IF VL >= 128
TMP_DEST[15:0] := (SRC1 >> (imm[1:0] *16))[15:0]
TMP_DEST[31:16] := (SRC1 >> (imm[3:2] * 16))[15:0]
TMP_DEST[47:32] := (SRC1 >> (imm[5:4] * 16))[15:0]
TMP_DEST[63:48] := (SRC1 >> (imm[7:6] * 16))[15:0]
TMP_DEST[127:64] := SRC1[127:64]
FI;
IF VL >= 256
TMP_DEST[143:128] := (SRC1 >> (imm[1:0] *16))[143:128]
TMP_DEST[159:144] := (SRC1 >> (imm[3:2] * 16))[143:128]
TMP_DEST[175:160] := (SRC1 >> (imm[5:4] * 16))[143:128]
TMP_DEST[191:176] := (SRC1 >> (imm[7:6] * 16))[143:128]
TMP_DEST[255:192] := SRC1[255:192]
FI;
IF VL >= 512
TMP_DEST[271:256] := (SRC1 >> (imm[1:0] *16))[271:256]
TMP_DEST[287:272] := (SRC1 >> (imm[3:2] * 16))[271:256]
TMP_DEST[303:288] := (SRC1 >> (imm[5:4] * 16))[271:256]
TMP_DEST[319:304] := (SRC1 >> (imm[7:6] * 16))[271:256]
TMP_DEST[383:320] := SRC1[383:320]
PSHUFLW-Shuffle Packed Low Words
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4-434
TMP_DEST[399:384] := (SRC1 >> (imm[1:0] *16))[399:384]
TMP_DEST[415:400] := (SRC1 >> (imm[3:2] * 16))[399:384]
TMP_DEST[431:416] := (SRC1 >> (imm[5:4] * 16))[399:384]
TMP_DEST[447:432] := (SRC1 >> (imm[7:6] * 16))[399:384]
TMP_DEST[511:448] := SRC1[511:448]
FI;
FOR j := 0 TO KL-1
i := j * 16
IF k1[j] OR *no writemask*
THEN DEST[i+15:i] := TMP_DEST[i+15:i];
ELSE
IF *merging-masking*
; merging-masking
THEN *DEST[i+15:i] remains unchanged*
ELSE *zeroing-masking*
; zeroing-masking
DEST[i+15:i] := 0
FI
FI;
ENDFOR
DEST[MAXVL-1:VL] := 0
Intel C/C++ Compiler Intrinsic Equivalent
VPSHUFLW __m512i _mm512_shufflelo_epi16(__m512i a, int n);
VPSHUFLW __m512i _mm512_mask_shufflelo_epi16(__m512i s, __mmask16 k, __m512i a, int n );
VPSHUFLW __m512i _mm512_maskz_shufflelo_epi16( __mmask16 k, __m512i a, int n );
VPSHUFLW __m256i _mm256_mask_shufflelo_epi16(__m256i s, __mmask8 k, __m256i a, int n );
VPSHUFLW __m256i _mm256_maskz_shufflelo_epi16( __mmask8 k, __m256i a, int n );
VPSHUFLW __m128i _mm_mask_shufflelo_epi16(__m128i s, __mmask8 k, __m128i a, int n );
VPSHUFLW __m128i _mm_maskz_shufflelo_epi16( __mmask8 k, __m128i a, int n );
(V)PSHUFLW:__m128i _mm_shufflelo_epi16(__m128i a, int n)
VPSHUFLW:__m256i _mm256_shufflelo_epi16(__m256i a, const int n)
Flags Affected
None.
SIMD Floating-Point Exceptions
None.
Other Exceptions
Non-EVEX-encoded instruction, see Table 2-21, “Type 4 Class Exception Conditions.”
EVEX-encoded instruction, see Exceptions Type E4NF.nb in Table 2-52, “Type E4NF Class Exception Conditions.”
Additionally:
#UD
If VEX.vvvv != 1111B, or EVEX.vvvv != 1111B.
PSHUFLW-Shuffle Packed Low Words
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PSHUFW-Shuffle Packed Words
Opcode/
Op/
64-Bit
Compat/
Description
Instruction
En
Mode
Leg Mode
NP 0F 70 /r ib
RMI
Valid
Valid
Shuffle the words in mm2/m64 based on the
encoding in imm8 and store the result in mm1.
PSHUFW mm1, mm2/m64, imm8
Instruction Operand Encoding
Op/En
Operand 1
Operand 2
Operand 3
Operand 4
RMI
ModRM:reg (w)
ModRM:r/m (r)
imm8
N/A
Description
Copies words from the source operand (second operand) and inserts them in the destination operand (first
operand) at word locations selected with the order operand (third operand). This operation is similar to the opera-
tion used by the PSHUFD instruction, which is illustrated in Figure 4-16. For the PSHUFW instruction, each 2-bit
field in the order operand selects the contents of one word location in the destination operand. The encodings of
the order operand fields select words from the source operand to be copied to the destination operand.
The source operand can be an MMX technology register or a 64-bit memory location. The destination operand is an
MMX technology register. The order operand is an 8-bit immediate. Note that this instruction permits a word in the
source operand to be copied to more than one word location in the destination operand.
In 64-bit mode, using a REX prefix in the form of REX.R permits this instruction to access additional registers
(XMM8-XMM15).
Operation
DEST[15:0] := (SRC >> (ORDER[1:0] * 16))[15:0];
DEST[31:16] := (SRC >> (ORDER[3:2] * 16))[15:0];
DEST[47:32] := (SRC >> (ORDER[5:4] * 16))[15:0];
DEST[63:48] := (SRC >> (ORDER[7:6] * 16))[15:0];
Intel C/C++ Compiler Intrinsic Equivalent
PSHUFW __m64 _mm_shuffle_pi16(__m64 a, int n)
Flags Affected
None.
Numeric Exceptions
None.
Other Exceptions
See Section 25.25.3, “Exception Conditions of Legacy SIMD Instructions Operating on MMX Registers” in the Intel®
64 and IA-32 Architectures Software Developer’s Manual, Volume 3B.
PSHUFW-Shuffle Packed Words
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PSIGNB/PSIGNW/PSIGND-Packed SIGN
Opcode/
Op/
64/32 bit
CPUID
Description
Instruction
En
Mode
Feature
Support
Flag
NP 0F 38 08 /r1
RM
V/V
SSSE3
Negate/zero/preserve packed byte integers in
PSIGNB mm1, mm2/m64
mm1 depending on the corresponding sign in
mm2/m64.
66 0F 38 08 /r
RM
V/V
SSSE3
Negate/zero/preserve packed byte integers in
xmm1 depending on the corresponding sign in
PSIGNB xmm1, xmm2/m128
xmm2/m128.
NP 0F 38 09 /r1
RM
V/V
SSSE3
Negate/zero/preserve packed word integers
in mm1 depending on the corresponding sign
PSIGNW mm1, mm2/m64
in mm2/m128.
66 0F 38 09 /r
RM
V/V
SSSE3
Negate/zero/preserve packed word integers
in xmm1 depending on the corresponding sign
PSIGNW xmm1, xmm2/m128
in xmm2/m128.
NP 0F 38 0A /r1
RM
V/V
SSSE3
Negate/zero/preserve packed doubleword
integers in mm1 depending on the
PSIGND mm1, mm2/m64
corresponding sign in mm2/m128.
66 0F 38 0A /r
RM
V/V
SSSE3
Negate/zero/preserve packed doubleword
integers in xmm1 depending on the
PSIGND xmm1, xmm2/m128
corresponding sign in xmm2/m128.
VEX.128.66.0F38.WIG 08 /r
RVM
V/V
AVX
Negate/zero/preserve packed byte integers in
xmm2 depending on the corresponding sign in
VPSIGNB xmm1, xmm2, xmm3/m128
xmm3/m128.
VEX.128.66.0F38.WIG 09 /r
RVM
V/V
AVX
Negate/zero/preserve packed word integers
in xmm2 depending on the corresponding sign
VPSIGNW xmm1, xmm2, xmm3/m128
in xmm3/m128.
VEX.128.66.0F38.WIG 0A /r
RVM
V/V
AVX
Negate/zero/preserve packed doubleword
integers in xmm2 depending on the
VPSIGND xmm1, xmm2, xmm3/m128
corresponding sign in xmm3/m128.
VEX.256.66.0F38.WIG 08 /r
RVM
V/V
AVX2
Negate packed byte integers in ymm2 if the
corresponding sign in ymm3/m256 is less
VPSIGNB ymm1, ymm2, ymm3/m256
than zero.
VEX.256.66.0F38.WIG 09 /r
RVM
V/V
AVX2
Negate packed 16-bit integers in ymm2 if the
corresponding sign in ymm3/m256 is less
VPSIGNW ymm1, ymm2, ymm3/m256
than zero.
VEX.256.66.0F38.WIG 0A /r
RVM
V/V
AVX2
Negate packed doubleword integers in ymm2
if the corresponding sign in ymm3/m256 is
VPSIGND ymm1, ymm2, ymm3/m256
less than zero.
NOTES:
1. See note in Section 2.5, “Intel® AVX and Intel® SSE Instruction Exception Classification,” in the Intel® 64 and IA-32 Architectures Soft-
ware Developer’s Manual, Volume 2A, and Section 25.25.3, “Exception Conditions of Legacy SIMD Instructions Operating on MMX
Registers,” in the Intel® 64 and IA-32 Architectures Software Developer’s Manual, Volume 3B.
Instruction Operand Encoding
Op/En
Operand 1
Operand 2
Operand 3
Operand 4
RM
ModRM:reg (r, w)
ModRM:r/m (r)
N/A
N/A
RVM
ModRM:reg (w)
VEX.vvvv (r)
ModRM:r/m (r)
N/A
PSIGNB/PSIGNW/PSIGND-Packed SIGN
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Description
(V)PSIGNB/(V)PSIGNW/(V)PSIGND negates each data element of the destination operand (the first operand) if the
signed integer value of the corresponding data element in the source operand (the second operand) is less than
zero. If the signed integer value of a data element in the source operand is positive, the corresponding data
element in the destination operand is unchanged. If a data element in the source operand is zero, the corre-
sponding data element in the destination operand is set to zero.
(V)PSIGNB operates on signed bytes. (V)PSIGNW operates on 16-bit signed words. (V)PSIGND operates on signed
32-bit integers.
Legacy SSE instructions: Both operands can be MMX registers. In 64-bit mode, use the REX prefix to access addi-
tional registers.
128-bit Legacy SSE version: The first source and destination operands are XMM registers. The second source
operand is an XMM register or a 128-bit memory location. Bits (MAXVL-1:128) of the corresponding YMM destina-
tion register remain unchanged.
VEX.128 encoded version: The first source and destination operands are XMM registers. The second source
operand is an XMM register or a 128-bit memory location. Bits (MAXVL-1:128) of the destination YMM register are
zeroed. VEX.L must be 0, otherwise instructions will #UD.
VEX.256 encoded version: The first source and destination operands are YMM registers. The second source
operand is an YMM register or a 256-bit memory location.
Operation
def byte_sign(control, input_val):
if control<0:
return negate(input_val)
elif control==0:
return 0
return input_val
def word_sign(control, input_val):
if control<0:
return negate(input_val)
elif control==0:
return 0
return input_val
def dword_sign(control, input_val):
if control<0:
return negate(input_val)
elif control==0:
return 0
return input_val
PSIGNB srcdest, src
// MMX 64-bit Operands
VL=64
KL := VL/8
for i in 0...KL-1:
srcdest.byte[i] := byte_sign(src.byte[i], srcdest.byte[i])
PSIGNW srcdest, src
// MMX 64-bit Operands
VL=64
KL := VL/16
FOR i in 0...KL-1:
srcdest.word[i] := word_sign(src.word[i], srcdest.word[i])
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PSIGND srcdest, src
// MMX 64-bit Operands
VL=64
KL := VL/32
FOR i in 0...KL-1:
srcdest.dword[i] := dword_sign(src.dword[i], srcdest.dword[i])
PSIGNB srcdest, src
// SSE 128-bit Operands
VL=128
KL := VL/8
FOR i in 0...KL-1:
srcdest.byte[i] := byte_sign(src.byte[i], srcdest.byte[i])
PSIGNW srcdest, src
// SSE 128-bit Operands
VL=128
KL := VL/16
FOR i in 0...KL-1:
srcdest.word[i] := word_sign(src.word[i], srcdest.word[i])
PSIGND srcdest, src
// SSE 128-bit Operands
VL=128
KL := VL/32
FOR i in 0...KL-1:
srcdest.dword[i] := dword_sign(src.dword[i], srcdest.dword[i])
VPSIGNB dest, src1, src2
// AVX 128-bit or 256-bit Operands
VL=(128,256)
KL := VL/8
FOR i in 0...KL-1:
dest.byte[i] := byte_sign(src2.byte[i], src1.byte[i])
DEST[MAXVL-1:VL] := 0
VPSIGNW dest, src1, src2
// AVX 128-bit or 256-bit Operands
VL=(128,256)
KL := VL/16
FOR i in 0...KL-1:
dest.word[i] := word_sign(src2.word[i], src1.word[i])
DEST[MAXVL-1:VL] := 0
VPSIGND dest, src1, src2
// AVX 128-bit or 256-bit Operands
VL=(128,256)
KL := VL/32
FOR i in 0...KL-1:
dest.dword[i] := dword_sign(src2.dword[i], src1.dword[i])
DEST[MAXVL-1:VL] := 0
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