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MACHINE-CHECK ARCHITECTURE

27 26

2423

1615

12 11

Count

Reserved

MCG_LMCE_P[27]

MCG_ELOG_P[26]

MCG_EMC_P[25]

MCG_SER_P[24]

MCG_EXT_CNT[23:16]

MCG_TES_P[11]

MCG_CMCI_P[10]

MCG_EXT_P[9]

MCG_CTL_P[8]

Figure 16-2. IA32_MCG_CAP Register

Where:

•

Count field, bits 7:0 — Indicates the number of hardware unit error-reporting banks available in a particular

processor implementation.

•

MCG_CTL_P (control MSR present) flag, bit 8 — Indicates that the processor implements the IA32_MC-

G_CTL MSR when set; this register is absent when clear.

•

MCG_EXT_P (extended MSRs present) flag, bit 9 — Indicates that the processor implements the extended

machine-check state registers found starting at MSR address 180H; these registers are absent when clear.

•

MCG_CMCI_P (Corrected MC error counting/signaling extension present) flag, bit 10 — Indicates

(when set) that extended state and associated MSRs necessary to support the reporting of an interrupt on a

corrected MC error event and/or count threshold of corrected MC errors, is present. When this bit is set, it does

not imply this feature is supported across all banks. Software should check the availability of the necessary

logic on a bank by bank basis when using this signaling capability (i.e., bit 30 settable in individual IA32_M-

Ci_CTL2 register).

•

MCG_TES_P (threshold-based error status present) flag, bit 11 — Indicates (when set) that bits 56:53

of the IA32_MCi_STATUS MSR are part of the architectural space. Bits 56:55 are reserved, and bits 54:53 are

used to report threshold-based error status. Note that when MCG_TES_P is not set, bits 56:53 of the IA32_M-

Ci_STATUS MSR are model-specific.

•

MCG_EXT_CNT, bits 23:16 — Indicates the number of extended machine-check state registers present. This

field is meaningful only when the MCG_EXT_P flag is set.

•

MCG_SER_P (software error recovery support present) flag, bit 24 — Indicates (when set) that the

processor supports software error recovery (see Section 16.6), and IA32_MCi_STATUS MSR bits 56:55 are

used to report the signaling of uncorrected recoverable errors and whether software must take recovery

actions for uncorrected errors. Note that when MCG_TES_P is not set, bits 56:53 of the IA32_MCi_STATUS MSR

are model-specific. If MCG_TES_P is set but MCG_SER_P is not set, bits 56:55 are reserved.

•

MCG_EMC_P (Enhanced Machine Check Capability) flag, bit 25 — Indicates (when set) that the

processor supports enhanced machine check capabilities for firmware first signaling.

•

MCG_ELOG_P (extended error logging) flag, bit 26 — Indicates (when set) that the processor allows

platform firmware to be invoked when an error is detected so that it may provide additional platform specific

information in an ACPI format “Generic Error Data Entry” that augments the data included in machine check

bank registers.

For additional information about extended error logging interface, see

https://cdrdv2.intel.com/v1/dl/getContent/671064.

•

MCG_LMCE_P (local machine check exception) flag, bit 27 — Indicates (when set) that the following

interfaces are present:

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— an extended state LMCE_S (located in bit 3 of IA32_MCG_STATUS), and

— the IA32_MCG_EXT_CTL MSR, necessary to support Local Machine Check Exception (LMCE).

A non-zero MCG_LMCE_P indicates that, when LMCE is enabled as described in Section 16.3.1.5, some machine

check errors may be delivered to only a single logical processor.

The effect of writing to the IA32_MCG_CAP MSR is undefined.

16.3.1.2 IA32_MCG_STATUS MSR

The IA32_MCG_STATUS MSR describes the current state of the processor after a machine-check exception has

occurred (see Figure 16-3).

Reserved

LMCE_S—Local machine check exception signaled

MCIP—Machine check in progress flag

EIPV—Error IP valid flag

RIPV—Restart IP valid flag

Figure 16-3. IA32_MCG_STATUS Register

Where:

• RIPV (restart IP valid) flag, bit 0 — Indicates (when set) that program execution can be restarted reliably

at the instruction pointed to by the instruction pointer pushed on the stack when the machine-check exception

is generated. When clear, the program cannot be reliably restarted at the pushed instruction pointer.

• EIPV (error IP valid) flag, bit 1 — Indicates (when set) that the instruction pointed to by the instruction

pointer pushed onto the stack when the machine-check exception is generated is directly associated with the

error. When this flag is cleared, the instruction pointed to may not be associated with the error.

• MCIP (machine check in progress) flag, bit 2 — Indicates (when set) that a machine-check exception was

generated. Software can set or clear this flag. The occurrence of a second Machine-Check Event while MCIP is

set will cause the processor to enter a shutdown state. For information on processor behavior in the shutdown

state, please refer to the description in Chapter 6, “Interrupt and Exception Handling”: “Interrupt 8—Double

Fault Exception (#DF)”.

• LMCE_S (local machine check exception signaled), bit 3 — Indicates (when set) that a local machine-

check exception was generated. This indicates that the current machine-check event was delivered to only this

logical processor.

Bits 63:04 in IA32_MCG_STATUS are reserved. An attempt to write to IA32_MCG_STATUS with any value other

than 0 would result in #GP.

16.3.1.3 IA32_MCG_CTL MSR

The IA32_MCG_CTL MSR is present if the capability flag MCG_CTL_P is set in the IA32_MCG_CAP MSR.

IA32_MCG_CTL controls the reporting of machine-check exceptions. If present, writing 1s to this register enables

machine-check features and writing all 0s disables machine-check features. All other values are undefined and/or

implementation specific.

16.3.1.4 IA32_MCG_EXT_CTL MSR

The IA32_MCG_EXT_CTL MSR is present if the capability flag MCG_LMCE_P is set in the IA32_MCG_CAP MSR.

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IA32_MCG_EXT_CTL.LMCE_EN (bit 0) allows the processor to signal some MCEs to only a single logical processor

in the system.

If MCG_LMCE_P is not set in IA32_MCG_CAP, or platform software has not enabled LMCE by setting IA32_FEA-

TURE_CONTROL.LMCE_ENABLED (bit 20), any attempt to write or read IA32_MCG_EXT_CTL will result in #GP.

The IA32_MCG_EXT_CTL MSR is cleared on RESET.

Figure 16-4 shows the layout of the IA32_MCG_EXT_CTL register

Reserved

LMCE_EN - system software control to enable/disable LMCE

Figure 16-4. IA32_MCG_EXT_CTL Register

where

• LMCE_EN (local machine check exception enable) flag, bit 0 - System software sets this to allow

hardware to signal some MCEs to only a single logical processor. System software can set LMCE_EN only if the

platform software has configured IA32_FEATURE_CONTROL as described in Section 16.3.1.5.

16.3.1.5 Enabling Local Machine Check

The intended usage of LMCE requires proper configuration by both platform software and system software. Plat-

form software can turn LMCE on by setting bit 20 (LMCE_ENABLED) in IA32_FEATURE_CONTROL MSR (MSR

address 3AH).

System software must ensure that both IA32_FEATURE_CONTROL.Lock (bit 0)and IA32_FEATURE_CON-

TROL.LMCE_ENABLED (bit 20) are set before attempting to set IA32_MCG_EXT_CTL.LMCE_EN (bit 0). When

system software has enabled LMCE, then hardware will determine if a particular error can be delivered only to a

single logical processor. Software should make no assumptions about the type of error that hardware can choose

to deliver as LMCE. The severity and override rules stay the same as described in Table 16-8 to determine the

recovery actions.

16.3.2 Error-Reporting Register Banks

Each error-reporting register bank can contain the IA32_MCi_CTL, IA32_MCi_STATUS, IA32_MCi_ADDR, and

IA32_MCi_MISC MSRs. The number of reporting banks is indicated by bits [7:0] of IA32_MCG_CAP MSR (address

0179H). The first error-reporting register (IA32_MC0_CTL) always starts at address 400H.

See Chapter 2, “Model-Specific Registers (MSRs),” in the Intel^® 64 and IA-32 Architectures Software Developer’s

Manual, Volume 4, for addresses of the error-reporting registers in the Pentium 4, Intel Atom, and Intel Xeon

processors; and for addresses of the error-reporting registers P6 family processors.

16.3.2.1 IA32_MCi_CTL MSRs

The IA32_MCi_CTL MSR controls signaling of #MC for errors produced by a particular hardware unit (or group of

hardware units). Each of the 64 flags (EEj) represents a potential error. Setting an EEj flag enables signaling #MC

of the associated error and clearing it disables signaling of the error. Error logging happens regardless of the setting

of these bits. The processor drops writes to bits that are not implemented. Figure 16-5 shows the bit fields of

IA32_MCi_CTL.

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MACHINE-CHECK ARCHITECTURE

62 61

3 2

EEj—Error reporting enable flag

(where j is 00 through 63)

Figure 16-5. IA32_MCi_CTL Register

NOTE

For P6 family processors, processors based on Intel Core microarchitecture (excluding those on

which CPUID reports DisplayFamily_DisplayModel as 06H_1AH and onward): the operating system

or executive software must not modify the contents of the IA32_MC0_CTL MSR. This MSR is

internally aliased to the EBL_CR_POWERON MSR and controls platform-specific error handling

features. System specific firmware (the BIOS) is responsible for the appropriate initialization of the

IA32_MC0_CTL MSR. P6 family processors only allow the writing of all 1s or all 0s to the IA32_M-

Ci_CTL MSR.

16.3.2.2 IA32_MCi_STATUS MSRS

Each IA32_MCi_STATUS MSR contains information related to a machine-check error if its VAL (valid) flag is set (see

Figure 16-6). Software is responsible for clearing IA32_MCi_STATUS MSRs by explicitly writing 0s to them; writing

1s to them causes a general-protection exception.

NOTE

Figure 16-6 depicts the IA32_MCi_STATUS MSR when IA32_MCG_CAP[24] = 1, IA32_MC-

G_CAP[11] = 1 and IA32_MCG_CAP[10] = 1. When IA32_MCG_CAP[24] = 0 and IA32_MC-

G_CAP[11] = 1, bits 56:55 is reserved and bits 54:53 for threshold-based error reporting. When

IA32_MCG_CAP[11] = 0, bits 56:53 are part of the “Other Information” field. The use of bits 54:53

for threshold-based error reporting began with Intel Core Duo processors, and is currently used for

cache memory. See Section 16.4, “Enhanced Cache Error reporting,” for more information. When

IA32_MCG_CAP[10] = 0, bits 52:38 are part of the “Other Information” field. The use of bits 52:38

for corrected MC error count is introduced with Intel 64 processor on which CPUID reports Display-

Family_DisplayModel as 06H_1AH.

Where:

• MCA (machine-check architecture) error code field, bits 15:0 — Specifies the machine-check archi-

tecture-defined error code for the machine-check error condition detected. The machine-check architecture-

defined error codes are guaranteed to be the same for all IA-32 processors that implement the machine-check

architecture. See Section 16.9, “Interpreting the MCA Error Codes,” and Chapter 17, “Interpreting Machine

Check Error Codes‚” for information on machine-check error codes.

• Model-specific error code field, bits 31:16 — Specifies the model-specific error code that uniquely

identifies the machine-check error condition detected. The model-specific error codes may differ among IA-32

processors for the same machine-check error condition. See Chapter 17, “Interpreting Machine Check Error

Codes‚” for information on model-specific error codes.

• Reserved, Error Status, and Other Information fields, bits 56:32 —

• If IA32_MCG_CAP.MCG_EMC_P[bit 25] is 0, bits 37:32 contain “Other Information” that is implemen-

tation-specific and is not part of the machine-check architecture.

• If IA32_MCG_CAP.MCG_EMC_P is 1, “Other Information” is in bits 36:32. If bit 37 is 0, system firmware

has not changed the contents of IA32_MCi_STATUS. If bit 37 is 1, system firmware may have edited the

contents of IA32_MCi_STATUS.

• If IA32_MCG_CAP.MCG_CMCI_P[bit 10] is 0, bits 52:38 also contain “Other Information” (in the same

sense as bits 37:32).

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6362616059585756555453 52

3837

32 31

1615

Corrected Error

Other

MSCOD Model

MCA Error Code

Count

Info

Specific Error Code

Firmware updated error status indicator (37)*

Threshold-based error status (54:53)**

AR — Recovery action required for UCR error (55)***

S — Signaling an uncorrected recoverable (UCR) error (56)***

PCC — Processor context corrupted (57)

ADDRV — MCi_ADDR register valid (58)

MISCV — MCi_MISC register valid (59)

EN — Error reporting enabled (60)

UC — Uncorrected error (61)

OVER — Error overflow (62)

VAL — MCi_STATUS register valid (63)

* When IA32_MCG_CAP[25] (MCG_EMC_P) is set, bit 37 is not part of “Other Information”.

** When IA32_MCG_CAP[11] (MCG_TES_P) is not set, these bits are model-specific

(part of “Other Information”).

*** When IA32_MCG_CAP[11] or IA32_MCG_CAP[24] are not set, these bits are reserved, or

model-specific (part of “Other Information”).

Figure 16-6. IA32_MCi_STATUS Register

•

If IA32_MCG_CAP[10] is 1, bits 52:38 are architectural (not model-specific). In this case, bits 52:38

reports the value of a 15 bit counter that increments each time a corrected error is observed by the MCA

recording bank. This count value will continue to increment until cleared by software. The most

significant bit, 52, is a sticky count overflow bit.

•

If IA32_MCG_CAP[11] is 0, bits 56:53 also contain “Other Information” (in the same sense).

•

If IA32_MCG_CAP[11] is 1, bits 56:53 are architectural (not model-specific). In this case, bits 56:53

have the following functionality:

•

If IA32_MCG_CAP[24] is 0, bits 56:55 are reserved.

•

If IA32_MCG_CAP[24] is 1, bits 56:55 are defined as follows:

•

S (Signaling) flag, bit 56 - Signals the reporting of UCR errors in this MC bank. See Section 16.6.2

for additional details.

•

AR (Action Required) flag, bit 55 - Indicates (when set) that MCA error code specific recovery

action must be performed by system software at the time this error was signaled. See Section

16.6.2 for additional details.

•

If the UC bit (Figure 16-6) is 1, bits 54:53 are undefined.

•

If the UC bit (Figure 16-6) is 0, bits 54:53 indicate the status of the hardware structure that

reported the threshold-based error. See Table 16-1.

Table 16-1. Bits 54:53 in IA32_MCi_STATUS MSRs when IA32_MCG_CAP[11] = 1 and UC = 0

Bits 54:53

Meaning

No tracking - No hardware status tracking is provided for the structure reporting this event.

Green - Status tracking is provided for the structure posting the event; the current status is green (below threshold).

For more information, see Section 16.4, “Enhanced Cache Error reporting.”

Yellow - Status tracking is provided for the structure posting the event; the current status is yellow (above threshold).

For more information, see Section 16.4, “Enhanced Cache Error reporting.”

Reserved

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MACHINE-CHECK ARCHITECTURE

•

PCC (processor context corrupt) flag, bit 57 — Indicates (when set) that the state of the processor might

have been corrupted by the error condition detected and that reliable restarting of the processor may not be

possible. When clear, this flag indicates that the error did not affect the processor’s state, and software may be

able to restart. When system software supports recovery, consult Section 16.10.4, “Machine-Check Software

Handler Guidelines for Error Recovery,” for additional rules that apply.

•

ADDRV (IA32_MCi_ADDR register valid) flag, bit 58 — Indicates (when set) that the IA32_MCi_ADDR

clear, this flag indicates that the IA32_MCi_ADDR register is either not implemented or does not contain the

address where the error occurred. Do not read these registers if they are not implemented in the processor.

•

MISCV (IA32_MCi_MISC register valid) flag, bit 59 — Indicates (when set) that the IA32_MCi_MISC

Ci_MISC register is either not implemented or does not contain additional information regarding the error. Do

not read these registers if they are not implemented in the processor.

•

EN (error enabled) flag, bit 60 — Indicates (when set) that the error was enabled by the associated EEj bit

of the IA32_MCi_CTL register.

•

UC (error uncorrected) flag, bit 61 — Indicates (when set) that the processor did not or was not able to

correct the error condition. When clear, this flag indicates that the processor was able to correct the error

condition.

•

OVER (machine check overflow) flag, bit 62 — Indicates (when set) that a machine-check error occurred

while the results of a previous error were still in the error-reporting register bank (that is, the VAL bit was

already set in the IA32_MCi_STATUS register). The processor sets the OVER flag and software is responsible for

clearing it. In general, enabled errors are written over disabled errors, and uncorrected errors are written over

corrected errors. Uncorrected errors are not written over previous valid uncorrected errors. When

MCG_CMCI_P is set, corrected errors may not set the OVER flag. Software can rely on corrected error count in

IA32_MCi_Status[52:38] to determine if any additional corrected errors may have occurred. For more infor-

mation, see Section 16.3.2.2.1, “Overwrite Rules for Machine Check Overflow.”

•

VAL (IA32_MCi_STATUS register valid) flag, bit 63 — Indicates (when set) that the information within the

IA32_MCi_STATUS register is valid. When this flag is set, the processor follows the rules given for the OVER flag

in the IA32_MCi_STATUS register when overwriting previously valid entries. The processor sets the VAL flag

and software is responsible for clearing it.

16.3.2.2.1 Overwrite Rules for Machine Check Overflow

Table 16-2 shows the overwrite rules for how to treat a second event if the cache has already posted an event to

the MC bank - that is, what to do if the valid bit for an MC bank already is set to 1. When more than one structure

posts events in a given bank, these rules specify whether a new event will overwrite a previous posting or not.

These rules define a priority for uncorrected (highest priority), yellow, and green/unmonitored (lowest priority)

status.

In Table 16-2, the values in the two left-most columns are IA32_MCi_STATUS[54:53].

Table 16-2. Overwrite Rules for Enabled Errors

First Event

Second Event

UC bit

Color

MCA Info

00/green

either

00/green

yellow

second error

yellow

00/green

yellow

first error

yellow

either

00/green/yellow

undefined

second

00/green/yellow

undefined

first

If a second event overwrites a previously posted event, the information (as guarded by individual valid bits) in the

MCi bank is entirely from the second event. Similarly, if a first event is retained, all of the information previously

posted for that event is retained. In general, when the logged error or the recent error is a corrected error, the

OVER bit (MCi_Status[62]) may be set to indicate an overflow. When MCG_CMCI_P is set in IA32_MCG_CAP,

system software should consult IA32_MCi_STATUS[52:38] to determine if additional corrected errors may have

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occurred. Software may re-read IA32_MCi_STATUS, IA32_MCi_ADDR, and IA32_MCi_MISC appropriately to

ensure data collected represent the last error logged.

After software polls a posting and clears the register, the valid bit is no longer set and therefore the meaning of the

rest of the bits, including the yellow/green/00 status field in bits 54:53, is undefined. The yellow/green indication

will only be posted for events associated with monitored structures - otherwise the unmonitored (00) code will be

posted in IA32_MCi_STATUS[54:53].

16.3.2.3 IA32_MCi_ADDR MSRs

The IA32_MCi_ADDR MSR contains the address of the code or data memory location that produced the machine-

check error if the ADDRV flag in the IA32_MCi_STATUS register is set (see Section 16-7, “IA32_MCi_ADDR MSR”).

The IA32_MCi_ADDR register is either not implemented or contains no address if the ADDRV flag in the IA32_M-

Ci_STATUS register is clear. When not implemented in the processor, all reads and writes to this MSR will cause a

general protection exception.

The address returned is an offset into a segment, linear address, or physical address. This depends on the error

encountered. When these registers are implemented, these registers can be cleared by explicitly writing 0s to

these registers. Writing 1s to these registers will cause a general-protection exception. See Figure 16-7.

Processor Without Support For Intel 64 Architecture

36 35

Reserved

Address

Processor With Support for Intel 64 Architecture

Address^*

* Useful bits in this field depend on the address methodology in use when the

the register state is saved.

Figure 16-7. IA32_MCi_ADDR MSR

16.3.2.4 IA32_MCi_MISC MSRs

The IA32_MCi_MISC MSR contains additional information describing the machine-check error if the MISCV flag in

the IA32_MCi_STATUS register is set. The IA32_MCi_MISC_MSR is either not implemented or does not contain

additional information if the MISCV flag in the IA32_MCi_STATUS register is clear.

When not implemented in the processor, all reads and writes to this MSR will cause a general protection exception.

When implemented in a processor, these registers can be cleared by explicitly writing all 0s to them; writing 1s to

them causes a general-protection exception to be generated. This register is not implemented in any of the error-

reporting register banks for the P6 or Intel Atom family processors.

If both MISCV and IA32_MCG_CAP[24] are set, the IA32_MCi_MISC_MSR is defined according to Figure 16-8 to

support software recovery of uncorrected errors (see Section 16.6).

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Model Specific Information

Address Mode

Recoverable Address LSB

Figure 16-8. UCR Support in IA32_MCi_MISC Register

• Recoverable Address LSB (bits 5:0): The lowest valid recoverable address bit. Indicates the position of the least

significant bit (LSB) of the recoverable error address. For example, if the processor logs bits [43:9] of the

address, the LSB sub-field in IA32_MCi_MISC is 01001b (9 decimal). For this example, bits [8:0] of the

recoverable error address in IA32_MCi_ADDR should be ignored.

• Address Mode (bits 8:6): Address mode for the address logged in IA32_MCi_ADDR. The supported address

modes are given in Table 16-3.

Table 16-3. Address Mode in IA32_MCi_MISC[8:6]

IA32_MCi_MISC[8:6] Encoding

Definition

000

Segment Offset

001

Linear Address

010

Physical Address

011

Memory Address

100 to 110

Reserved

111

Generic

• Model Specific Information (bits 63:9): Not architecturally defined.

16.3.2.4.2 IOMCA

Logging and Signaling of errors from PCI Express domain is governed by PCI Express Advanced Error Reporting

(AER) architecture. PCI Express architecture divides errors in two categories: Uncorrectable errors and Correctable

errors. Uncorrectable errors can further be classified as Fatal or Non-Fatal. Uncorrected IO errors are signaled to

the system software either as AER Message Signaled Interrupt (MSI) or via platform specific mechanisms such as

NMI. Generally, the signaling mechanism is controlled by BIOS and/or platform firmware. Certain processors

support an error handling mode, called IOMCA mode, where Uncorrected PCI Express errors are signaled in the

form of machine check exception and logged in machine check banks.

When a processor is in this mode, Uncorrected PCI Express errors are logged in the MCACOD field of the IA32_M-

Ci_STATUS register as Generic I/O error. The corresponding MCA error code is defined in Table 15-8. IA32_M-

Ci_Status [15:0] Simple Error Code Encoding. Machine check logging complements and does not replace AER

logging that occurs inside the PCI Express hierarchy. The PCI Express Root Complex and Endpoints continue to log

the error in accordance with PCI Express AER mechanism. In IOMCA mode, MCi_MISC register in the bank that

logged IOMCA can optionally contain information that link the Machine Check logs with the AER logs or proprietary

logs. In such a scenario, the machine check handler can utilize the contents of MCi_MISC to locate the next level of

error logs corresponding to the same error. Specifically, if MCi_Status.MISCV is 1 and MCACOD is 0x0E0B, MCi_-

MISC contains the PCI Express address of the Root Complex device containing the AER Logs. Software can consult

the header type and class code registers in the Root Complex device's PCIe Configuration space to determine what

type of device it is. This Root Complex device can either be a PCI Express Root Port, PCI Express Root Complex

Event Collector or a proprietary device.

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Errors that originate from PCI Express or Legacy Endpoints are logged in the corresponding Root Port in addition to

the generating device. If MISCV=1 and MCi_MISC contains the address of the Root Port or a Root Complex Event

collector, software can parse the AER logs to learn more about the error.

If MISCV=1 and MCi_MISC points to a device that is neither a Root Complex Event Collector not a Root Port, soft-

ware must consult the Vendor ID/Device ID and use device specific knowledge to locate and interpret the error log

registers. In some cases, the Root Complex device configuration space may not be accessible to the software and

both the Vendor and Device ID read as 0xFFFF.

• The format of MCi_MISC for IOMCA errors is shown in Table 16-4.

Table 16-4. Address Mode in IA32_MCi_MISC[8:6]

63:40

39:32

31:16

15:9

8:6

5:0

RSVD

PCI Express Segment

PCI Express

RSVD

ADDR MODE¹

RECOV ADDR LSB¹

number

Requestor ID

NOTES:

1. Not Applicable if ADDRV=0.

Refer to PCI Express Specification 3.0 for definition of PCI Express Requestor ID and AER architecture. Refer to PCI

Firmware Specification 3.0 for an explanation of PCI Ex-press Segment number and how software can access

configuration space of a PCI Ex-press device given the segment number and Requestor ID.

16.3.2.5 IA32_MCi_CTL2 MSRs

The IA32_MCi_CTL2 MSR provides the programming interface to use corrected MC error signaling capability that is

indicated by IA32_MCG_CAP[10] = 1. Software must check for the presence of IA32_MCi_CTL2 on a per-bank

basis.

When IA32_MCG_CAP[10] = 1, the IA32_MCi_CTL2 MSR for each bank exists, i.e., reads and writes to these MSR

are supported. However, signaling interface for corrected MC errors may not be supported in all banks.

The layout of IA32_MCi_CTL2 is shown in Figure 16-9.

3130

Reserved

CMCI_EN—Enable/disable CMCI

Corrected error count threshold

Figure 16-9. IA32_MCi_CTL2 Register

• Corrected error count threshold, bits 14:0 — Software must initialize this field. The value is compared with

the corrected error count field in IA32_MCi_STATUS, bits 38 through 52. An overflow event is signaled to the

CMCI LVT entry (see Table 11-1) in the APIC when the count value equals the threshold value. The new LVT

entry in the APIC is at 02F0H offset from the APIC_BASE. If CMCI interface is not supported for a particular

bank (but IA32_MCG_CAP[10] = 1), this field will always read 0.

• CMCI_EN (Corrected error interrupt enable/disable/indicator), bits 30 — Software sets this bit to

enable the generation of corrected machine-check error interrupt (CMCI). If CMCI interface is not supported for

a particular bank (but IA32_MCG_CAP[10] = 1), this bit is writeable but will always return 0 for that bank. This

bit also indicates CMCI is supported or not supported in the corresponding bank. See Section 16.5 for details of

software detection of CMCI facility.

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Some microarchitectural sub-systems that are the source of corrected MC errors may be shared by more than one

logical processors. Consequently, the facilities for reporting MC errors and controlling mechanisms may be shared

by more than one logical processors. For example, the IA32_MCi_CTL2 MSR is shared between logical processors

sharing a processor core. Software is responsible to program IA32_MCi_CTL2 MSR in a consistent manner with

CMCI delivery and usage.

After processor reset, IA32_MCi_CTL2 MSRs are zeroed.

16.3.2.6 IA32_MCG Extended Machine Check State MSRs

The Pentium 4 and Intel Xeon processors implement a variable number of extended machine-check state MSRs.

The MCG_EXT_P flag in the IA32_MCG_CAP MSR indicates the presence of these extended registers, and the

MCG_EXT_CNT field indicates the number of these registers actually implemented. See Section 16.3.1.1,

“IA32_MCG_CAP MSR.” Also see Table 16-5.

Table 16-5. Extended Machine Check State MSRs in Processors Without Support for Intel® 64 Architecture

MSR

Address

Description

IA32_MCG_EAX

180H

Contains state of the EAX register at the time of the machine-check error.

IA32_MCG_EBX

181H

Contains state of the EBX register at the time of the machine-check error.

IA32_MCG_ECX

182H

Contains state of the ECX register at the time of the machine-check error.

IA32_MCG_EDX

183H

Contains state of the EDX register at the time of the machine-check error.

IA32_MCG_ESI

184H

Contains state of the ESI register at the time of the machine-check error.

IA32_MCG_EDI

185H

Contains state of the EDI register at the time of the machine-check error.

IA32_MCG_EBP

186H

Contains state of the EBP register at the time of the machine-check error.

IA32_MCG_ESP

187H

Contains state of the ESP register at the time of the machine-check error.

IA32_MCG_EFLAGS

188H

Contains state of the EFLAGS register at the time of the machine-check error.

IA32_MCG_EIP

189H

Contains state of the EIP register at the time of the machine-check error.

IA32_MCG_MISC

18AH

When set, indicates that a page assist or page fault occurred during DS normal

operation.

In processors with support for Intel 64 architecture, 64-bit machine check state MSRs are aliased to the legacy

MSRs. In addition, there may be registers beyond IA32_MCG_MISC. These may include up to five reserved MSRs

(IA32_MCG_RESERVED[1:5]) and save-state MSRs for registers introduced in 64-bit mode. See Table 16-6.

Table 16-6. Extended Machine Check State MSRs In Processors With Support for Intel® 64 Architecture

MSR

Address

Description

IA32_MCG_RAX

180H

Contains state of the RAX register at the time of the machine-check error.

IA32_MCG_RBX

181H

Contains state of the RBX register at the time of the machine-check error.

IA32_MCG_RCX

182H

Contains state of the RCX register at the time of the machine-check error.

IA32_MCG_RDX

183H

Contains state of the RDX register at the time of the machine-check error.

IA32_MCG_RSI

184H

Contains state of the RSI register at the time of the machine-check error.

IA32_MCG_RDI

185H

Contains state of the RDI register at the time of the machine-check error.

IA32_MCG_RBP

186H

Contains state of the RBP register at the time of the machine-check error.

IA32_MCG_RSP

187H

Contains state of the RSP register at the time of the machine-check error.

IA32_MCG_RFLAGS

188H

Contains state of the RFLAGS register at the time of the machine-check error.

IA32_MCG_RIP

189H

Contains state of the RIP register at the time of the machine-check error.

IA32_MCG_MISC

18AH

When set, indicates that a page assist or page fault occurred during DS normal

operation.

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Table 16-6. Extended Machine Check State MSRs In Processors With Support for Intel® 64 Architecture (Contd.)

MSR

Address

Description

IA32_MCG_

18BH-

These registers, if present, are reserved.

RSERVED[1:5]

18FH

IA32_MCG_R8

190H

Contains state of the R8 register at the time of the machine-check error.

IA32_MCG_R9

191H

Contains state of the R9 register at the time of the machine-check error.

IA32_MCG_R10

192H

Contains state of the R10 register at the time of the machine-check error.

IA32_MCG_R11

193H

Contains state of the R11 register at the time of the machine-check error.

IA32_MCG_R12

194H

Contains state of the R12 register at the time of the machine-check error.

IA32_MCG_R13

195H

Contains state of the R13 register at the time of the machine-check error.

IA32_MCG_R14

196H

Contains state of the R14 register at the time of the machine-check error.

IA32_MCG_R15

197H

Contains state of the R15 register at the time of the machine-check error.

When a machine-check error is detected on a Pentium 4 or Intel Xeon processor, the processor saves the state of

the general-purpose registers, the R/EFLAGS register, and the R/EIP in these extended machine-check state MSRs.

This information can be used by a debugger to analyze the error.

These registers are read/write to zero registers. This means software can read them; but if software writes to

them, only all zeros is allowed. If software attempts to write a non-zero value into one of these registers, a general-

protection (#GP) exception is generated. These registers are cleared on a hardware reset (power-up or RESET),

but maintain their contents following a soft reset (INIT reset).

16.3.3 Mapping of the Pentium Processor Machine-Check Errors to the Machine-Check

Architecture

The Pentium processor reports machine-check errors using two registers: P5_MC_TYPE and P5_MC_ADDR. The

Pentium 4, Intel Xeon, Intel Atom, and P6 family processors map these registers to the IA32_MCi_STATUS and

IA32_MCi_ADDR in the error-reporting register bank. This bank reports on the same type of external bus errors

reported in P5_MC_TYPE and P5_MC_ADDR.

The information in these registers can then be accessed in two ways:

• By reading the IA32_MCi_STATUS and IA32_MCi_ADDR registers as part of a general machine-check exception

handler written for Pentium 4, Intel Atom and P6 family processors.

• By reading the P5_MC_TYPE and P5_MC_ADDR registers using the RDMSR instruction.

The second capability permits a machine-check exception handler written to run on a Pentium processor to be run

on a Pentium 4, Intel Xeon, Intel Atom, or P6 family processor. There is a limitation in that information returned by

the Pentium 4, Intel Xeon, Intel Atom, and P6 family processors is encoded differently than information returned

by the Pentium processor. To run a Pentium processor machine-check exception handler on a Pentium 4, Intel

Xeon, Intel Atom, or P6 family processor; the handler must be written to interpret P5_MC_TYPE encodings

correctly.

16.4

ENHANCED CACHE ERROR REPORTING

Starting with Intel Core Duo processors, cache error reporting was enhanced. In earlier Intel processors, cache

status was based on the number of correction events that occurred in a cache. In the new paradigm, called

“threshold-based error status”, cache status is based on the number of lines (ECC blocks) in a cache that incur

repeated corrections. The threshold is chosen by Intel, based on various factors. If a processor supports threshold-

based error status, it sets IA32_MCG_CAP[11] (MCG_TES_P) to 1; if not, to 0.

A processor that supports enhanced cache error reporting contains hardware that tracks the operating status of

certain caches and provides an indicator of their “health”. The hardware reports a “green” status when the number

of lines that incur repeated corrections is at or below a pre-defined threshold, and a “yellow” status when the

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number of affected lines exceeds the threshold. Yellow status means that the cache reporting the event is operating

correctly, but you should schedule the system for servicing within a few weeks.

Intel recommends that you rely on this mechanism for structures supported by threshold-base error reporting.

The CPU/system/platform response to a yellow event should be less severe than its response to an uncorrected

error. An uncorrected error means that a serious error has actually occurred, whereas the yellow condition is a

warning that the number of affected lines has exceeded the threshold but is not, in itself, a serious event: the error

was corrected and system state was not compromised.

The green/yellow status indicator is not a foolproof early warning for an uncorrected error resulting from the failure

of two bits in the same ECC block. Such a failure can occur and cause an uncorrected error before the yellow

threshold is reached. However, the chance of an uncorrected error increases as the number of affected lines

increases.

16.5

CORRECTED MACHINE CHECK ERROR INTERRUPT

Corrected machine-check error interrupt (CMCI) is an architectural enhancement to the machine-check architec-

ture. It provides capabilities beyond those of threshold-based error reporting (Section 16.4). With threshold-based

error reporting, software is limited to use periodic polling to query the status of hardware corrected MC errors.

CMCI provides a signaling mechanism to deliver a local interrupt based on threshold values that software can

program using the IA32_MCi_CTL2 MSRs.

CMCI is disabled by default. System software is required to enable CMCI for each IA32_MCi bank that support the

reporting of hardware corrected errors if IA32_MCG_CAP[10] = 1.

System software use IA32_MCi_CTL2 MSR to enable/disable the CMCI capability for each bank and program

threshold values into IA32_MCi_CTL2 MSR. CMCI is not affected by the CR4.MCE bit, and it is not affected by the

IA32_MCi_CTL MSRs.

To detect the existence of thresholding for a given bank, software writes only bits 14:0 with the threshold value. If

the bits persist, then thresholding is available (and CMCI is available). If the bits are all 0's, then no thresholding

exists. To detect that CMCI signaling exists, software writes a 1 to bit 30 of the MCi_CTL2 register. Upon subsequent

read, if bit 30 = 0, no CMCI is available for this bank and no corrected or UCNA errors will be reported on this bank.

If bit 30 = 1, then CMCI is available and enabled.

16.5.1 CMCI Local APIC Interface

The operation of CMCI is depicted in Figure 16-10.

Software write 1 to enable

31 30

MCi_CTL2

Error threshold

Count overflow threshold -> CMCI LVT in local APIC

APIC_BASE + 2F0H

MCi_STATUS

Error count

Figure 16-10. CMCI Behavior

CMCI interrupt delivery is configured by writing to the LVT CMCI register entry in the local APIC register space at

default address of APIC_BASE + 2F0H. A CMCI interrupt can be delivered to more than one logical processors if

multiple logical processors are affected by the associated MC errors. For example, if a corrected bit error in a cache

shared by two logical processors caused a CMCI, the interrupt will be delivered to both logical processors sharing

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that microarchitectural sub-system. Similarly, package level errors may cause CMCI to be delivered to all logical

processors within the package. However, system level errors will not be handled by CMCI.

See Section 11.5.1, “Local Vector Table,” for details regarding the LVT CMCI register.

16.5.2 System Software Recommendation for Managing CMCI and Machine Check Resources

System software must enable and manage CMCI, set up interrupt handlers to service CMCI interrupts delivered to

affected logical processors, program CMCI LVT entry, and query machine check banks that are shared by more

than one logical processors.

This section describes techniques system software can implement to manage CMCI initialization, service CMCI

interrupts in a efficient manner to minimize contentions to access shared MSR resources.

16.5.2.1 CMCI Initialization

Although a CMCI interrupt may be delivered to more than one logical processors depending on the nature of the

corrected MC error, only one instance of the interrupt service routine needs to perform the necessary service and

make queries to the machine-check banks. The following steps describes a technique that limits the amount of

work the system has to do in response to a CMCI.

•

To provide maximum flexibility, system software should define per-thread data structure for each logical

processor to allow equal-opportunity and efficient response to interrupt delivery. Specifically, the per-thread

data structure should include a set of per-bank fields to track which machine check bank it needs to access in

response to a delivered CMCI interrupt. The number of banks that needs to be tracked is determined by

IA32_MCG_CAP[7:0].

•

Initialization of per-thread data structure. The initialization of per-thread data structure must be done serially

on each logical processor in the system. The sequencing order to start the per-thread initialization between

different logical processor is arbitrary. But it must observe the following specific detail to satisfy the shared

nature of specific MSR resources:

a. Each thread initializes its data structure to indicate that it does not own any MC bank registers.

b. Each thread examines IA32_MCi_CTL2[30] indicator for each bank to determine if another thread has

already claimed ownership of that bank.

• If IA32_MCi_CTL2[30] had been set by another thread. This thread can not own bank i and should

proceed to step b. and examine the next machine check bank until all of the machine check banks are

exhausted.

• If IA32_MCi_CTL2[30] = 0, proceed to step c.

c. Check whether writing a 1 into IA32_MCi_CTL2[30] can return with 1 on a subsequent read to determine

this bank can support CMCI.

• If IA32_MCi_CTL2[30] = 0, this bank does not support CMCI. This thread can not own bank i and should

proceed to step b. and examine the next machine check bank until all of the machine check banks are

exhausted.

• If IA32_MCi_CTL2[30] = 1, modify the per-thread data structure to indicate this thread claims

ownership to the MC bank; proceed to initialize the error threshold count (bits 15:0) of that bank as

described in Chapter 16, “CMCI Threshold Management”. Then proceed to step b. and examine the next

machine check bank until all of the machine check banks are exhausted.

•

After the thread has examined all of the machine check banks, it sees if it owns any MC banks to service CMCI.

If any bank has been claimed by this thread:

— Ensure that the CMCI interrupt handler has been set up as described in Chapter 16, “CMCI Interrupt

Handler”.

— Initialize the CMCI LVT entry, as described in Section 16.5.1, “CMCI Local APIC Interface.”

— Log and clear all of IA32_MCi_Status registers for the banks that this thread owns. This will allow new

errors to be logged.

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16.5.2.2 CMCI Threshold Management

The Corrected MC error threshold field, IA32_MCi_CTL2[14:0], is architecturally defined. Specifically, all these bits

are writable by software, but different processor implementations may choose to implement less than 15 bits as

threshold for the overflow comparison with IA32_MCi_STATUS[52:38]. The following describes techniques that

software can manage CMCI threshold to be compatible with changes in implementation characteristics:

• Software can set the initial threshold value to 1 by writing 1 to IA32_MCi_CTL2[14:0]. This will cause overflow

condition on every corrected MC error and generates a CMCI interrupt.

• To increase the threshold and reduce the frequency of CMCI servicing:

a. Find the maximum threshold value a given processor implementation supports. The steps are:

• Write 7FFFH to IA32_MCi_CTL2[14:0],

• Read back IA32_MCi_CTL2[14:0]; these 15 bits (14:0) contain the maximum threshold supported by

the processor.

b. Increase the threshold to a value below the maximum value discovered using step a.

16.5.2.3 CMCI Interrupt Handler

The following describes techniques system software may consider to implement a CMCI service routine:

• The service routine examines its private per-thread data structure to check which set of MC banks it has

ownership. If the thread does not have ownership of a given MC bank, proceed to the next MC bank. Ownership

is determined at initialization time which is described in Section 16.5.2.1.

If the thread had claimed ownership to an MC bank, this technique will allow each logical processors to handle

corrected MC errors independently and requires no synchronization to access shared MSR resources. Consult

Example 16-5 for guidelines on logging when processing CMCI.

16.6

RECOVERY OF UNCORRECTED RECOVERABLE (UCR) ERRORS

Recovery of uncorrected recoverable machine check errors is an enhancement in machine-check architecture. The

first processor that supports this feature is 45 nm Intel 64 processor on which CPUID reports DisplayFamily_Dis-

playModel as 06H_2EH; see the CPUID instruction in Chapter 3, “Instruction Set Reference, A-L‚” in the Intel^® 64

and IA-32 Architectures Software Developer’s Manual, Volume 2A. This allows system software to perform recovery

action on a certain class of uncorrected errors and continue execution.

16.6.1 Detection of Software Error Recovery Support

Software must use bit 24 of IA32_MCG_CAP (MCG_SER_P) to detect the presence of software error recovery

support (see Figure 16-2). When IA32_MCG_CAP[24] is set, this indicates that the processor supports software

error recovery. When this bit is clear, this indicates that there is no support for error recovery from the processor

and the primary responsibility of the machine check handler is logging the machine check error information and

shutting down the system.

The new class of architectural MCA errors from which system software can attempt recovery is called Uncorrected

Recoverable (UCR) Errors. UCR errors are uncorrected errors that have been detected and signaled but have not

corrupted the processor context. For certain UCR errors, this means that once system software has performed a

certain recovery action, it is possible to continue execution on this processor. UCR error reporting provides an error

containment mechanism for data poisoning. The machine check handler will use the error log information from the

error reporting registers to analyze and implement specific error recovery actions for UCR errors.

16.6.2 UCR Error Reporting and Logging

IA32_MCi_STATUS MSR is used for reporting UCR errors and existing corrected or uncorrected errors. The defini-

tions of IA32_MCi_STATUS, including bit fields to identify UCR errors, is shown in Figure 16-6. UCR errors can be

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signaled through either the corrected machine check interrupt (CMCI) or machine check exception (MCE) path

depending on the type of the UCR error.

When IA32_MCG_CAP[24] is set, a UCR error is indicated by the following bit settings in the IA32_MCi_STATUS

• Valid (bit 63) = 1

• UC (bit 61) = 1

• PCC (bit 57) = 0

Additional information from the IA32_MCi_MISC and the IA32_MCi_ADDR registers for the UCR error are available

when the ADDRV and the MISCV flags in the IA32_MCi_STATUS register are set (see Section 16.3.2.4). The MCA

error code field of the IA32_MCi_STATUS register indicates the type of UCR error. System software can interpret

the MCA error code field to analyze and identify the necessary recovery action for the given UCR error.

In addition, the IA32_MCi_STATUS register bit fields, bits 56:55, are defined (see Figure 16-6) to provide addi-

tional information to help system software to properly identify the necessary recovery action for the UCR error:

• S (Signaling) flag, bit 56 - Indicates (when set) that a machine check exception was generated for the UCR

error reported in this MC bank and system software needs to check the AR flag and the MCA error code fields in

the IA32_MCi_STATUS register to identify the necessary recovery action for this error. When the S flag in the

IA32_MCi_STATUS register is clear, this UCR error was not signaled via a machine check exception and instead

was reported as a corrected machine check (CMC). System software is not required to take any recovery action

when the S flag in the IA32_MCi_STATUS register is clear.

• AR (Action Required) flag, bit 55 - Indicates (when set) that MCA error code specific recovery action must be

performed by system software at the time this error was signaled. This recovery action must be completed

successfully before any additional work is scheduled for this processor. When the RIPV flag in the IA32_MC-

G_STATUS is clear, an alternative execution stream needs to be provided; when the MCA error code specific

recovery specific recovery action cannot be successfully completed, system software must shut down the

system. When the AR flag in the IA32_MCi_STATUS register is clear, system software may still take MCA error

code specific recovery action but this is optional; system software can safely resume program execution at the

instruction pointer saved on the stack from the machine check exception when the RIPV flag in the IA32_MC-

G_STATUS register is set.

Both the S and the AR flags in the IA32_MCi_STATUS register are defined to be sticky bits, which mean that once

set, the processor does not clear them. Only software and good power-on reset can clear the S and the AR-flags.

Both the S and the AR flags are only set when the processor reports the UCR errors (MCG_CAP[24] is set).

16.6.3 UCR Error Classification

With the S and AR flag encoding in the IA32_MCi_STATUS register, UCR errors can be classified as:

• Uncorrected no action required (UCNA) - is a UCR error that is not signaled via a machine check exception and,

instead, is reported to system software as a corrected machine check error. UCNA errors indicate that some

data in the system is corrupted, but the data has not been consumed and the processor state is valid and you

may continue execution on this processor. UCNA errors require no action from system software to continue

execution. A UCNA error is indicated with UC=1, PCC=0, S=0 and AR=0 in the IA32_MCi_STATUS register.

• Software recoverable action optional (SRAO) - a UCR error is signaled either via a machine check exception or

CMCI. System software recovery action is optional and not required to continue execution from this machine

check exception. SRAO errors indicate that some data in the system is corrupt, but the data has not been

consumed and the processor state is valid. SRAO errors provide the additional error information for system

software to perform a recovery action. An SRAO error when signaled as a machine check is indicated with

UC=1, PCC=0, S=1, EN=1 and AR=0 in the IA32_MCi_STATUS register. In cases when SRAO is signaled via

CMCI the error signature is indicated via UC=1, PCC=0, S=0. Recovery actions for SRAO errors are MCA error

code specific. The MISCV and the ADDRV flags in the IA32_MCi_STATUS register are set when the additional

error information is available from the IA32_MCi_MISC and the IA32_MCi_ADDR registers. System software

needs to inspect the MCA error code fields in the IA32_MCi_STATUS register to identify the specific recovery

action for a given SRAO error. If MISCV and ADDRV are not set, it is recommended that no system software

error recovery be performed however, system software can resume execution.

• Software recoverable action required (SRAR) - a UCR error that requires system software to take a recovery

action on this processor before scheduling another stream of execution on this processor. SRAR errors indicate

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that the error was detected and raised at the point of the consumption in the execution flow. An SRAR error is

indicated with UC=1, PCC=0, S=1, EN=1 and AR=1 in the IA32_MCi_STATUS register. Recovery actions are

MCA error code specific. The MISCV and the ADDRV flags in the IA32_MCi_STATUS register are set when the

additional error information is available from the IA32_MCi_MISC and the IA32_MCi_ADDR registers. System

software needs to inspect the MCA error code fields in the IA32_MCi_STATUS register to identify the specific

recovery action for a given SRAR error. If MISCV and ADDRV are not set, it is recommended that system

software shutdown the system.

Table 16-7 summarizes UCR, corrected, and uncorrected errors.

Table 16-7. MC Error Classifications

Type of Error¹

PCC

Signaling

Software Action

Example

Uncorrected Error (UC)

MCE

If EN=1, reset the system, else log

and OK to keep the system running.

SRAR

MCE

For known MCACOD, take specific

Cache to processor load

recovery action;

error.

For unknown MCACOD, must

bugcheck.

If OVER=1, reset system, else take

specific recovery action.

SRAO

x²

MCE/CMC

For known MCACOD, take specific

Patrol scrub and explicit

recovery action;

writeback poison errors.

For unknown MCACOD, OK to keep

the system running.

UCNA

CMC

Log the error and Ok to keep the

Poison detection error.

system running.

Corrected Error (CE)

CMC

Log the error and no corrective

ECC in caches and

action required.

memory.

NOTES:

1. SRAR, SRAO and UCNA errors are supported by the processor only when IA32_MCG_CAP[24] (MCG_SER_P) is set.

2. EN=1, S=1 when signaled via MCE. EN=x, S=0 when signaled via CMC.

16.6.4 UCR Error Overwrite Rules

In general, the overwrite rules are as follows:

• UCR errors will overwrite corrected errors.

• Uncorrected (PCC=1) errors overwrite UCR (PCC=0) errors.

• UCR errors are not written over previous UCR errors.

• Corrected errors do not write over previous UCR errors.

Regardless of whether the 1st error is retained or the 2nd error is overwritten over the 1st error, the OVER flag in

the IA32_MCi_STATUS register will be set to indicate an overflow condition. As the S flag and AR flag in the

IA32_MCi_STATUS register are defined to be sticky flags, a second event cannot clear these 2 flags once set,

however the MC bank information may be filled in for the 2nd error. The table below shows the overwrite rules and

how to treat a second error if the first event is already logged in a MC bank along with the resulting bit setting of

the UC, PCC, and AR flags in the IA32_MCi_STATUS register. As UCNA and SRA0 errors do not require recovery

action from system software to continue program execution, a system reset by system software is not required

unless the AR flag or PCC flag is set for the UCR overflow case (OVER=1, VAL=1, UC=1, PCC=0).

Table 16-8 lists overwrite rules for uncorrected errors, corrected errors, and uncorrected recoverable errors.

Table 16-8. Overwrite Rules for UC, CE, and UCR Errors

First Event

Second Event

PCC

MCA Bank

Reset System

UCR

0 if UCNA, else 1

1 if SRAR, else 0

second

yes, if AR=1

UCR

0 if UCNA, else 1

1 if SRAR, else 0

first

yes, if AR=1

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Table 16-8. Overwrite Rules for UC, CE, and UCR Errors

First Event

Second Event

PCC

MCA Bank

Reset System

UCNA

first

UCNA

SRAO

first

UCNA

SRAR

first

yes

SRAO

UCNA

first

SRAO

first

SRAO

SRAR

first

yes

SRAR

UCNA

first

yes

SRAR

SRAO

first

yes

SRAR

first

yes

UCR

undefined

second

yes

UCR

undefined

first

yes

16.7

MACHINE-CHECK AVAILABILITY

The machine-check architecture and machine-check exception (#MC) are model-specific features. Software can

execute the CPUID instruction to determine whether a processor implements these features. Following the execu-

tion of the CPUID instruction, the settings of the MCA flag (bit 14) and MCE flag (bit 7) in EDX indicate whether the

processor implements the machine-check architecture and machine-check exception.

16.8

MACHINE-CHECK INITIALIZATION

To use the processors machine-check architecture, software must initialize the processor to activate the machine-

check exception and the error-reporting mechanism.

Example 16-1 gives pseudocode for performing this initialization. This pseudocode checks for the existence of the

machine-check architecture and exception; it then enables machine-check exception and the error-reporting

Pentium processors.

Following power up or power cycling, IA32_MCi_STATUS registers are not guaranteed to have valid data until after

they are initially cleared to zero by software (as shown in the initialization pseudocode in Example 16-1).

Example 16-1. Machine-Check Initialization Pseudocode

Check CPUID Feature Flags for MCE and MCA support

IF CPU supports MCE

THEN

IF CPU supports MCA

THEN

IF (IA32_MCG_CAP.MCG_CTL_P = 1)

(* IA32_MCG_CTL register is present *)

THEN

IA32_MCG_CTL ← FFFFFFFFFFFFFFFFH;

(* enables all MCA features *)

IF (IA32_MCG_CAP.MCG_LMCE_P = 1 and IA32_FEATURE_CONTROL.LOCK = 1 and IA32_FEATURE_CONTROL.LMCE_ENABLED = 1)

(* IA32_MCG_EXT_CTL register is present and platform has enabled LMCE to permit system software to use LMCE *)

THEN

IA32_MCG_EXT_CTL ← IA32_MCG_EXT_CTL | 01H;

(* System software enables LMCE capability for hardware to signal MCE to a single logical processor*)

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(* Determine number of error-reporting banks supported *)

COUNT← IA32_MCG_CAP.Count;

MAX_BANK_NUMBER ← COUNT - 1;

IF (Processor Family is 6H and Processor EXTMODEL:MODEL is less than 1AH)

THEN

(* Enable logging of all errors except for MC0_CTL register *)

FOR error-reporting banks (1 through MAX_BANK_NUMBER)

IA32_MCi_CTL ← 0FFFFFFFFFFFFFFFFH;

ELSE

(* Enable logging of all errors including MC0_CTL register *)

FOR error-reporting banks (0 through MAX_BANK_NUMBER)

IA32_MCi_CTL ← 0FFFFFFFFFFFFFFFFH;

(* BIOS clears all errors only on power-on reset *)

IF (BIOS detects Power-on reset)

THEN

FOR error-reporting banks (0 through MAX_BANK_NUMBER)

IA32_MCi_STATUS ← 0;

ELSE

FOR error-reporting banks (0 through MAX_BANK_NUMBER)

(Optional for BIOS and OS) Log valid errors

(OS only) IA32_MCi_STATUS ← 0;

Setup the Machine Check Exception (#MC) handler for vector 18 in IDT

Set the MCE bit (bit 6) in CR4 register to enable Machine-Check Exceptions

16.9

INTERPRETING THE MCA ERROR CODES

When the processor detects a machine-check error condition, it writes a 16-bit error code to the MCA error code

field of one of the IA32_MCi_STATUS registers and sets the VAL (valid) flag in that register. The processor may also

write a 16-bit model-specific error code in the IA32_MCi_STATUS register depending on the implementation of the

machine-check architecture of the processor.

The MCA error codes are architecturally defined for Intel 64 and IA-32 processors. To determine the cause of a

machine-check exception, the machine-check exception handler must read the VAL flag for each IA32_M-

Ci_STATUS register. If the flag is set, the machine check-exception handler must then read the MCA error code field

of the register. It is the encoding of the MCA error code field [15:0] that determines the type of error being reported

and not the register bank reporting it.

There are two types of MCA error codes: simple error codes and compound error codes.

16.9.1 Simple Error Codes

Table 16-9 shows the simple error codes. These unique codes indicate global error information.

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Table 16-9. IA32_MCi_Status [15:0] Simple Error Code Encoding

Error Code

Binary Encoding

Meaning

No Error

0000 0000 0000 0000

No error has been reported to this bank of error-reporting

registers.

Unclassified

0000 0000 0000 0001

This error has not been classified into the MCA error classes.

Microcode ROM Parity Error

0000 0000 0000 0010

Parity error in internal microcode ROM

External Error

0000 0000 0000 0011

The BINIT# from another processor caused this processor to

enter machine check.¹

FRC Error

0000 0000 0000 0100

FRC (functional redundancy check) main/secondary error.

Internal Parity Error

0000 0000 0000 0101

Internal parity error.

SMM Handler Code Access

0000 0000 0000 0110

An attempt was made by the SMM Handler to execute

Violation

outside the ranges specified by SMRR.

Internal Timer Error

0000 0100 0000 0000

Internal timer error.

I/O Error

0000 1110 0000 1011

generic I/O error.

Internal Unclassified

0000 01xx xxxx xxxx

Internal unclassified errors. ²

NOTES:

1. BINIT# assertion will cause a machine check exception if the processor (or any processor on the same external bus) has BINIT#

observation enabled during power-on configuration (hardware strapping) and if machine check exceptions are enabled (by setting

CR4.MCE = 1).

2. At least one X must equal one. Internal unclassified errors have not been classified.

16.9.2 Compound Error Codes

Compound error codes describe errors related to the TLBs, memory, caches, bus and interconnect logic, and

internal timer. A set of sub-fields is common to all of compound errors. These sub-fields describe the type of

access, level in the cache hierarchy, and type of request. Table 16-10 shows the general form of the compound

error codes.

Table 16-10. IA32_MCi_Status [15:0] Compound Error Code Encoding

Type

Form

Interpretation

Generic Cache Hierarchy

000F 0000 0000 11LL

Generic cache hierarchy error

TLB Errors

000F 0000 0001 TTLL

{TT}TLB{LL}_ERR

Memory Controller Errors

000F 0000 1MMM CCCC

{MMM}_CHANNEL{CCCC}_ERR

Cache Hierarchy Errors

000F 0001 RRRR TTLL

{TT}CACHE{LL}_{RRRR}_ERR

Extended Memory Errors

000F 0010 1MMM CCCC

{MMM}_CHANNEL{CCCC}_ERR

Bus and Interconnect Errors

000F 1PPT RRRR IILL

BUS{LL}_{PP}_{RRRR}_{II}_{T}_ERR

The “Interpretation” column in the table indicates the name of a compound error. The name is constructed by

substituting mnemonics for the sub-field names given within curly braces. For example, the error code

ICACHEL1_RD_ERR is constructed from the form:

{TT}CACHE{LL}_{RRRR}_ERR,

where {TT} is replaced by I, {LL} is replaced by L1, and {RRRR} is replaced by RD.

For more information on the “Form” and “Interpretation” columns, see Section 16.9.2.1, “Correction Report

Filtering (F) Bit,” through Section 16.9.2.5, “Bus and Interconnect Errors.”

16.9.2.1 Correction Report Filtering (F) Bit

Starting with Intel Core Duo processors, bit 12 in the “Form” column in Table 16-10 is used to indicate that a partic-

ular posting to a log may be the last posting for corrections in that line/entry, at least for some time:

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•

0 in bit 12 indicates “normal” filtering (original P6/Pentium4/Atom/Xeon processor meaning).

•

1 in bit 12 indicates “corrected” filtering (filtering is activated for the line/entry in the posting). Filtering means

that some or all of the subsequent corrections to this entry (in this structure) will not be posted. The enhanced

error reporting introduced with the Intel Core Duo processors is based on tracking the lines affected by

repeated corrections (see Section 16.4, “Enhanced Cache Error reporting”). This capability is indicated by

IA32_MCG_CAP[11]. Only the first few correction events for a line are posted; subsequent redundant

correction events to the same line are not posted. Uncorrected events are always posted.

The behavior of error filtering after crossing the yellow threshold is model-specific. Filtering has meaning only for

corrected errors (UC=0 in IA32_MCi_STATUS MSR). System software must ignore filtering bit (12) for uncorrected

errors.

16.9.2.2 Transaction Type (TT) Sub-Field

The 2-bit TT sub-field (Table 16-11) indicates the type of transaction (data, instruction, or generic). The sub-field

applies to the TLB, cache, and interconnect error conditions. Note that interconnect error conditions are primarily

associated with P6 family and Pentium processors, which utilize an external APIC bus separate from the system

bus. The generic type is reported when the processor cannot determine the transaction type.

Table 16-11. Encoding for TT (Transaction Type) Sub-Field

Transaction Type

Mnemonic

Binary Encoding

Instruction

Data

Generic

16.9.2.3 Level (LL) Sub-Field

The 2-bit LL sub-field (see Table 16-12) indicates the level in the memory hierarchy where the error occurred (level

0, level 1, level 2, or generic). The LL sub-field also applies to the TLB, cache, and interconnect error conditions.

The Pentium 4, Intel Xeon, Intel Atom, and P6 family processors support two levels in the cache hierarchy and one

level in the TLBs. Again, the generic type is reported when the processor cannot determine the hierarchy level.

Table 16-12. Level Encoding for LL (Memory Hierarchy Level) Sub-Field

Hierarchy Level

Mnemonic

Binary Encoding

Level 0

Level 1

Level 2

Generic

16.9.2.4 Request (RRRR) Sub-Field

The 4-bit RRRR sub-field (see Table 16-13) indicates the type of action associated with the error. Actions include

read and write operations, prefetches, cache evictions, and snoops. Generic error is returned when the type of

error cannot be determined. Generic read and generic write are returned when the processor cannot determine the

type of instruction or data request that caused the error. Eviction and snoop requests apply only to the caches. All

of the other requests apply to TLBs, caches, and interconnects.

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Table 16-13. Encoding of Request (RRRR) Sub-Field

Request Type

Mnemonic

Binary Encoding

Generic Error

ERR

0000

Generic Read

0001

Generic Write

0010

Data Read

DRD

0011

Data Write

DWR

0100

Instruction Fetch

IRD

0101

Prefetch

PREFETCH

0110

Eviction

EVICT

0111

Snoop

SNOOP

1000

16.9.2.5 Bus and Interconnect Errors

The bus and interconnect errors are defined with the 2-bit PP (participation), 1-bit T (time-out), and 2-bit II

(memory or I/O) sub-fields, in addition to the LL and RRRR sub-fields (see Table 16-14). The bus error conditions

are implementation dependent and related to the type of bus implemented by the processor. Likewise, the inter-

connect error conditions are predicated on a specific implementation-dependent interconnect model that describes

the connections between the different levels of the storage hierarchy. The type of bus is implementation depen-

dent, and as such is not specified in this document. A bus or interconnect transaction consists of a request involving

an address and a response.

Table 16-14. Encodings of PP, T, and II Sub-Fields

Sub-Field

Transaction

Mnemonic

Binary Encoding

PP (Participation)

Local processor* originated request

SRC

Local processor* responded to request

RES

Local processor* observed error as third party

OBS

Generic

T (Time-out)

Request timed out

TIMEOUT

Request did not time out

NOTIMEOUT

II (Memory or I/O)

Memory Access

Reserved

I/O

Other transaction

NOTE:

* Local processor differentiates the processor reporting the error from other system components (including the APIC, other proces-

sors, etc.).

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16.9.2.6 Memory Controller and Extended Memory Errors

The memory controller errors are defined with the 3-bit MMM (memory transaction type), and 4-bit CCCC (channel)

sub-fields. The encodings for MMM and CCCC are defined in Table 16-15. Extended Memory errors use the same

encodings and are used to report errors in memory used as a cache.

Table 16-15. Encodings of MMM and CCCC Sub-Fields

Sub-Field

Transaction

Mnemonic

Binary Encoding

MMM

Generic undefined request

GEN

000

Memory read error

001

Memory write error

010

Address/Command Error

011

Memory Scrubbing Error

100

Reserved

101-111

CCCC

Channel number

CHN

0000-1110

Channel not specified

1111

Note that the CCCC channel number may be enumerated from zero separately by each memory controller on a

system. On a multi-socket system, or a system with multiple memory controllers per socket, it is necessary to also

consider which machine check bank logged the error. See Chapter 17 for details on specific implementations.

16.9.3 Architecturally Defined UCR Errors

Software recoverable compound error code are defined in this section.

16.9.3.1 Architecturally Defined SRAO Errors

The following two SRAO errors are architecturally defined.

• UCR Errors detected by memory controller scrubbing; and

• UCR Errors detected during L3 cache (L3) explicit writebacks.

The MCA error code encodings for these two architecturally-defined UCR errors corresponds to sub-classes of

compound MCA error codes (see Table 16-10). Their values and compound encoding format are given in Table

16-16.

Table 16-16. MCA Compound Error Code Encoding for SRAO Errors

Type

MCACOD Value

MCA Error Code Encoding¹

Memory Scrubbing

C0H - CFH

0000_0000_1100_CCCC

000F 0000 1MMM CCCC (Memory Controller Error), where

Memory subfield MMM = 100B (memory scrubbing)

Channel subfield CCCC = channel # or generic

L3 Explicit Writeback

17AH

0000_0001_0111_1010

000F 0001 RRRR TTLL (Cache Hierarchy Error) where

Request subfields RRRR = 0111B (Eviction)

Transaction Type subfields TT = 10B (Generic)

Level subfields LL = 10B

NOTES:

1. Note that for both of these errors the correction report filtering (F) bit (bit 12) of the MCA error must be ignored.

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Table 16-17 lists values of relevant bit fields of IA32_MCi_STATUS for architecturally defined SRAO errors.

Table 16-17. IA32_MCi_STATUS Values for SRAO Errors

SRAO Error

Valid

OVER

MISCV

ADDRV

PCC

MCACOD

Memory Scrubbing

x¹

C0H-CFH

L3 Explicit Writeback

x¹

17AH

NOTES:

1. When signaled as MCE, EN=1 and S=1. If error was signaled via CMC, then EN=x, and S=0.

For both the memory scrubbing and L3 explicit writeback errors, the ADDRV and MISCV flags in the IA32_M-

Ci_STATUS register are set to indicate that the offending physical address information is available from the

IA32_MCi_MISC and the IA32_MCi_ADDR registers. For the memory scrubbing and L3 explicit writeback errors,

the address mode in the IA32_MCi_MISC register should be set as physical address mode (010b) and the address

LSB information in the IA32_MCi_MISC register should indicate the lowest valid address bit in the address informa-

tion provided from the IA32_MCi_ADDR register.

MCE signal is broadcast to all logical processors as outlined in Section 16.10.4.1. If LMCE is supported and enabled,

some errors (not limited to UCR errors) may be delivered to only a single logical processor. System software should

consult IA32_MCG_STATUS.LMCE_S to determine if the MCE signaled is only to this logical processor.

IA32_MCi_STATUS banks can be shared by logical processors within a core or within the same package. So several

logical processors may find an SRAO error in the shared IA32_MCi_STATUS bank but other processors do not find

it in any of the IA32_MCi_STATUS banks. Table 16-18 shows the RIPV and EIPV flag indication in the IA32_MC-

G_STATUS register for the memory scrubbing and L3 explicit writeback errors on both the reporting and non-

reporting logical processors.

Table 16-18. IA32_MCG_STATUS Flag Indication for SRAO Errors

SRAO Type

Reporting Logical Processors

Non-reporting Logical Processors

RIPV

EIPV

RIPV

EIPV

Memory Scrubbing

L3 Explicit Writeback

16.9.3.2 Architecturally Defined SRAR Errors

The following two SRAR errors are architecturally defined.

• UCR Errors detected on data load; and

• UCR Errors detected on instruction fetch.

The MCA error code encodings for these two architecturally-defined UCR errors corresponds to sub-classes of

compound MCA error codes (see Table 16-10). Their values and compound encoding format are given in Table

16-19.

Table 16-19. MCA Compound Error Code Encoding for SRAR Errors

Type

MCACOD Value

MCA Error Code Encoding¹

Data Load

134H

0000_0001_0011_0100

000F 0001 RRRR TTLL (Cache Hierarchy Error), where

Request subfield RRRR = 0011B (Data Load)

Transaction Type subfield TT= 01B (Data)

Level subfield LL = 00B (Level 0)

Instruction Fetch

150H

0000_0001_0101_0000

000F 0001 RRRR TTLL (Cache Hierarchy Error), where

Request subfield RRRR = 0101B (Instruction Fetch)

Transaction Type subfield TT= 00B (Instruction)

Level subfield LL = 00B (Level 0)

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NOTES:

1. Note that for both of these errors the correction report filtering (F) bit (bit 12) of the MCA error must be ignored.

Table 16-20 lists values of relevant bit fields of IA32_MCi_STATUS for architecturally defined SRAR errors.

Table 16-20. IA32_MCi_STATUS Values for SRAR Errors

SRAR Error

Valid

OVER

MISCV

ADDRV

PCC

MCACOD

Data Load

134H

Instruction Fetch

150H

For both the data load and instruction fetch errors, the ADDRV and MISCV flags in the IA32_MCi_STATUS register

are set to indicate that the offending physical address information is available from the IA32_MCi_MISC and the

IA32_MCi_ADDR registers. For the data load and instruction fetch errors, the address mode in the IA32_MCi_MISC

MCE signal is broadcast to all logical processors on the system on which the UCR errors are supported, except when

the processor supports LMCE and LMCE is enabled by system software (see Section 16.3.1.5). The IA32_MC-

G_STATUS MSR allows system software to distinguish the affected logical processor of an SRAR error amongst

logical processors that observed SRAR via MCi_STATUS bank.

Table 16-21 shows the RIPV and EIPV flag indication in the IA32_MCG_STATUS register for the data load and

instruction fetch errors on both the reporting and non-reporting logical processors. The recoverable SRAR error

reported by a processor may be continuable, where the system software can interpret the context of continuable

as follows: the error was isolated, contained. If software can rectify the error condition in the current instruction

stream, the execution context on that logical processor can be continued without loss of information.

Table 16-21. IA32_MCG_STATUS Flag Indication for SRAR Errors

SRAR Type

Affected Logical Processor

Non-Affected Logical Processors

RIPV

EIPV

Continuable

RIPV

EIPV

Continuable

Recoverable-

Yes¹

continuable

Yes

Recoverable-not-

continuable

NOTES:

1. see the definition of the context of “continuable” above and additional detail below.

SRAR Error And Affected Logical Processors

The affected logical processor is the one that has detected and raised an SRAR error at the point of the consump-

tion in the execution flow. The affected logical processor should find the Data Load or the Instruction Fetch error

information in the IA32_MCi_STATUS register that is reporting the SRAR error.

Table 16-21 list the actionable scenarios that system software can respond to an SRAR error on an affected logical

processor according to RIPV and EIPV values:

• Recoverable-Continuable SRAR Error (RIPV=1, EIPV=1):

For Recoverable-Continuable SRAR errors, the affected logical processor should find that both the IA32_MC-

G_STATUS.RIPV and the IA32_MCG_STATUS.EIPV flags are set, indicating that system software may be able to

restart execution from the interrupted context if it is able to rectify the error condition. If system software

cannot rectify the error condition then it must treat the error as a recoverable error where restarting execution

with the interrupted context is not possible. Restarting without rectifying the error condition will result in most

cases with another SRAR error on the same instruction.

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• Recoverable-not-continuable SRAR Error (RIPV=0, EIPV=x):

For Recoverable-not-continuable errors, the affected logical processor should find that either

— IA32_MCG_STATUS.RIPV= 0, IA32_MCG_STATUS.EIPV=1, or

— IA32_MCG_STATUS.RIPV= 0, IA32_MCG_STATUS.EIPV=0.

In either case, this indicates that the error is detected at the instruction pointer saved on the stack for this

machine check exception and restarting execution with the interrupted context is not possible. System

software may take the following recovery actions for the affected logical processor:

• The current executing thread cannot be continued. System software must terminate the interrupted

stream of execution and provide a new stream of execution on return from the machine check handler

for the affected logical processor.

SRAR Error And Non-Affected Logical Processors

The logical processors that observed but not affected by an SRAR error should find that the RIPV flag in the

IA32_MCG_STATUS register is set and the EIPV flag in the IA32_MCG_STATUS register is cleared, indicating that it

is safe to restart the execution at the instruction saved on the stack for the machine check exception on these

processors after the recovery action is successfully taken by system software.

16.9.4 Multiple MCA Errors

When multiple MCA errors are detected within a certain detection window, the processor may aggregate the

reporting of these errors together as a single event, i.e., a single machine exception condition. If this occurs,

system software may find multiple MCA errors logged in different MC banks on one logical processor or find

multiple MCA errors logged across different processors for a single machine check broadcast event. In order to

handle multiple UCR errors reported from a single machine check event and possibly recover from multiple errors,

system software may consider the following:

• Whether it can recover from multiple errors is determined by the most severe error reported on the system. If

the most severe error is found to be an unrecoverable error (VAL=1, UC=1, PCC=1 and EN=1) after system

software examines the MC banks of all processors to which the MCA signal is broadcast, recovery from the

multiple errors is not possible and system software needs to reset the system.

• When multiple recoverable errors are reported and no other fatal condition (e.g., overflowed condition for SRAR

error) is found for the reported recoverable errors, it is possible for system software to recover from the

multiple recoverable errors by taking necessary recovery action for each individual recoverable error. However,

system software can no longer expect one to one relationship with the error information recorded in the

IA32_MCi_STATUS register and the states of the RIPV and EIPV flags in the IA32_MCG_STATUS register as the

states of the RIPV and the EIPV flags in the IA32_MCG_STATUS register may indicate the information for the

most severe error recorded on the processor. System software is required to use the RIPV flag indication in the

IA32_MCG_STATUS register to make a final decision of recoverability of the errors and find the restart-ability

requirement after examining each IA32_MCi_STATUS register error information in the MC banks.

In certain cases where system software observes more than one SRAR error logged for a single logical

processor, it can no longer rely on affected threads as specified in Table 15-20 above. System software is

recommended to reset the system if this condition is observed.

16.9.5 Machine-Check Error Codes Interpretation

Chapter 17, “Interpreting Machine Check Error Codes,” provides information on interpreting the MCA error code,

model-specific error code, and other information error code fields. For P6 family processors, information has been

included on decoding external bus errors. For Pentium 4 and Intel Xeon processors; information is included on

external bus, internal timer and cache hierarchy errors.

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16.10 GUIDELINES FOR WRITING MACHINE-CHECK SOFTWARE

The machine-check architecture and error logging can be used in three different ways:

• To detect machine errors during normal instruction execution, using the machine-check exception (#MC).

• To periodically check and log machine errors.

• To examine recoverable UCR errors, determine software recoverability and perform recovery actions via a

machine-check exception handler or a corrected machine-check interrupt handler.

To use the machine-check exception, the operating system or executive software must provide a machine-check

exception handler. This handler may need to be designed specifically for each family of processors.

A special program or utility is required to log machine errors.

Guidelines for writing a machine-check exception handler or a machine-error logging utility are given in the

following sections.

16.10.1 Machine-Check Exception Handler

The machine-check exception (#MC) corresponds to vector 18. To service machine-check exceptions, a trap gate

must be added to the IDT. The pointer in the trap gate must point to a machine-check exception handler. Two

approaches can be taken to designing the exception handler:

1. The handler can merely log all the machine status and error information, then call a debugger or shut down the

system.

2. The handler can analyze the reported error information and, in some cases, attempt to correct the error and

restart the processor.

For Pentium 4, Intel Xeon, Intel Atom, P6 family, and Pentium processors; virtually all machine-check conditions

cannot be corrected (they result in abort-type exceptions). The logging of status and error information is therefore

a baseline implementation requirement.

When IA32_MCG_CAP[24] is clear, consider the following when writing a machine-check exception handler:

•

To determine the nature of the error, the handler must read each of the error-reporting register banks. The

count field in the IA32_MCG_CAP register gives number of register banks. The first register of register bank 0

is at address 400H.

•

The VAL (valid) flag in each IA32_MCi_STATUS register indicates whether the error information in the register

is valid. If this flag is clear, the registers in that bank do not contain valid error information and do not need to

be checked.

•

To write a portable exception handler, only the MCA error code field in the IA32_MCi_STATUS register should be

checked. See Section 16.9, “Interpreting the MCA Error Codes,” for information that can be used to write an

algorithm to interpret this field.

•

Correctable errors are corrected automatically by the processor. The UC flag in each IA32_MCi_STATUS reg-

ister indicates whether the processor automatically corrected an error.

•

The RIPV, PCC, and OVER flags in each IA32_MCi_STATUS register indicate whether recovery from the error is

possible. If PCC or OVER are set, recovery is not possible. If RIPV is not set, program execution can not be

restarted reliably. When recovery is not possible, the handler typically records the error information and signals

an abort to the operating system.

•

The RIPV flag in the IA32_MCG_STATUS register indicates whether the program can be restarted at the

instruction indicated by the instruction pointer (the address of the instruction pushed on the stack when the

exception was generated). If this flag is clear, the processor may still be able to be restarted (for debugging

purposes) but not without loss of program continuity.

•

For unrecoverable errors, the EIPV flag in the IA32_MCG_STATUS register indicates whether the instruction

indicated by the instruction pointer pushed on the stack (when the exception was generated) is related to the

error. If the flag is clear, the pushed instruction may not be related to the error.

•

The MCIP flag in the IA32_MCG_STATUS register indicates whether a machine-check exception was generated.

Before returning from the machine-check exception handler, software should clear this flag so that it can be

used reliably by an error logging utility. The MCIP flag also detects recursion. The machine-check architecture

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does not support recursion. When the processor detects machine-check recursion, it enters the shutdown

state.

Example 16-2 gives typical steps carried out by a machine-check exception handler.

Example 16-2. Machine-Check Exception Handler Pseudocode

IF CPU supports MCE

THEN

IF CPU supports MCA

THEN

call errorlogging routine; (* returns restartability *)

FI;

ELSE (* Pentium(R) processor compatible *)

READ P5_MC_ADDR

READ P5_MC_TYPE;

report RESTARTABILITY to console;

FI;

IF error is not restartable

THEN

report RESTARTABILITY to console;

abort system;

FI;

CLEAR MCIP flag in IA32_MCG_STATUS;

16.10.2 Pentium Processor Machine-Check Exception Handling

Machine-check exception handler on P6 family, Intel Atom and later processor families, should follow the guidelines

described in Section 16.10.1 and Example 16-2 that check the processor’s support of MCA.

NOTE

On processors that support MCA (CPUID.1.EDX.MCA = 1) reading the P5_MC_TYPE and

P5_MC_ADDR registers may produce invalid data.

When machine-check exceptions are enabled for the Pentium processor (MCE flag is set in control register CR4),

the machine-check exception handler uses the RDMSR instruction to read the error type from the P5_MC_TYPE

16.10.3 Logging Correctable Machine-Check Errors

The error handling routine for servicing the machine-check exceptions is responsible for logging uncorrected

errors.

If a machine-check error is correctable, the processor does not generate a machine-check exception for it. To

detect correctable machine-check errors, a utility program must be written that reads each of the machine-check

error-reporting register banks and logs the results in an accounting file or data structure. This utility can be imple-

mented in either of the following ways.

• A system daemon that polls the register banks on an infrequent basis, such as hourly or daily.

• A user-initiated application that polls the register banks and records the exceptions. Here, the actual polling

service is provided by an operating-system driver or through the system call interface.

• An interrupt service routine servicing CMCI can read the MC banks and log the error. Please refer to Section

16.10.4.2 for guidelines on logging correctable machine checks.

Example 16-3 gives pseudocode for an error logging utility.

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Example 16-3. Machine-Check Error Logging Pseudocode

Assume that execution is restartable;

IF the processor supports MCA

THEN

FOR each bank of machine-check registers

READ IA32_MCi_STATUS;

IF VAL flag in IA32_MCi_STATUS = 1

THEN

IF ADDRV flag in IA32_MCi_STATUS = 1

THEN READ IA32_MCi_ADDR;

FI;

IF MISCV flag in IA32_MCi_STATUS = 1

THEN READ IA32_MCi_MISC;

FI;

IF MCIP flag in IA32_MCG_STATUS = 1

(* Machine-check exception is in progress *)

AND PCC flag in IA32_MCi_STATUS = 1

OR RIPV flag in IA32_MCG_STATUS = 0

(* execution is not restartable *)

THEN

RESTARTABILITY = FALSE;

return RESTARTABILITY to calling procedure;

FI;

Save time-stamp counter and processor ID;

Set IA32_MCi_STATUS to all 0s;

Execute serializing instruction (i.e., CPUID);

FI;

OD;

FI;

If the processor supports the machine-check architecture, the utility reads through the banks of error-reporting

registers looking for valid register entries. It then saves the values of the IA32_MCi_STATUS, IA32_MCi_ADDR,

IA32_MCi_MISC, and IA32_MCG_STATUS registers for each bank that is valid. The routine minimizes processing

time by recording the raw data into a system data structure or file, reducing the overhead associated with polling.

User utilities analyze the collected data in an off-line environment.

When the MCIP flag is set in the IA32_MCG_STATUS register, a machine-check exception is in progress and the

machine-check exception handler has called the exception logging routine.

Once the logging process has been completed the exception-handling routine must determine whether execution

can be restarted, which is usually possible when damage has not occurred (The PCC flag is clear, in the IA32_M-

Ci_STATUS register) and when the processor can guarantee that execution is restartable (the RIPV flag is set in the

IA32_MCG_STATUS register). If execution cannot be restarted, the system is not recoverable and the exception-

handling routine should signal the console appropriately before returning the error status to the Operating System

kernel for subsequent shutdown.

The machine-check architecture allows buffering of exceptions from a given error-reporting bank although the

Pentium 4, Intel Xeon, Intel Atom, and P6 family processors do not implement this feature. The error logging

routine should provide compatibility with future processors by reading each hardware error-reporting bank's

IA32_MCi_STATUS register and then writing 0s to clear the OVER and VAL flags in this register. The error logging

utility should re-read the IA32_MCi_STATUS register for the bank ensuring that the valid bit is clear. The processor

will write the next error into the register bank and set the VAL flags.

Additional information that should be stored by the exception-logging routine includes the processor’s time-stamp

counter value, which provides a mechanism to indicate the frequency of exceptions. A multiprocessing operating

system stores the identity of the processor node incurring the exception using a unique identifier, such as the

processor’s APIC ID (see Section 11.8, “Handling Interrupts”).

The basic algorithm given in Example 16-3 can be modified to provide more robust recovery techniques. For

example, software has the flexibility to attempt recovery using information unavailable to the hardware. Specifi-

cally, the machine-check exception handler can, after logging carefully analyze the error-reporting registers when

the error-logging routine reports an error that does not allow execution to be restarted. These recovery techniques

16-30

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MACHINE-CHECK ARCHITECTURE

can use external bus related model-specific information provided with the error report to localize the source of the

error within the system and determine the appropriate recovery strategy.

16.10.4 Machine-Check Software Handler Guidelines for Error Recovery

16.10.4.1 Machine-Check Exception Handler for Error Recovery

When writing a machine-check exception (MCE) handler to support software recovery from Uncorrected Recover-

able (UCR) errors, consider the following:

•

When IA32_MCG_CAP [24] is zero, there are no recoverable errors supported and all machine-check are fatal

exceptions. The logging of status and error information is therefore a baseline implementation requirement.

•

When IA32_MCG_CAP [24] is 1, certain uncorrected errors called uncorrected recoverable (UCR) errors may be

software recoverable. The handler can analyze the reported error information, and in some cases attempt to

recover from the uncorrected error and continue execution.

•

For processors on which CPUID reports DisplayFamily_DisplayModel as 06H_0EH and onward, an MCA signal is

broadcast to all logical processors in the system; see the CPUID instruction in Chapter 3, “Instruction Set

Reference, A-L‚” in the Intel^® 64 and IA-32 Architectures Software Developer’s Manual, Volume 2A. Due to the

potentially shared machine check MSR resources among the logical processors on the same package/core, the

MCE handler may be required to synchronize with the other processors that received a machine check error and

serialize access to the machine check registers when analyzing, logging, and clearing the information in the

machine check registers.

— On processors that indicate ability for local machine-check exception (MCG_LMCE_P), hardware can choose

to report the error to only a single logical processor if system software has enabled LMCE by setting

IA32_MCG_EXT_CTL[LMCE_EN] = 1 as outlined in Section 16.3.1.5.

•

The VAL (valid) flag in each IA32_MCi_STATUS register indicates whether the error information in the register

is valid. If this flag is clear, the registers in that bank do not contain valid error information and should not be

checked.

•

The MCE handler is primarily responsible for processing uncorrected errors. The UC flag in each IA32_M-

Ci_Status register indicates whether the reported error was corrected (UC=0) or uncorrected (UC=1). The MCE

handler can optionally log and clear the corrected errors in the MC banks if it can implement software algorithm

to avoid the undesired race conditions with the CMCI or CMC polling handler.

•

For uncorrectable errors, the EIPV flag in the IA32_MCG_STATUS register indicates (when set) that the

instruction pointed to by the instruction pointer pushed onto the stack when the machine-check exception is

generated is directly associated with the error. When this flag is cleared, the instruction pointed to may not be

associated with the error.

•

The MCIP flag in the IA32_MCG_STATUS register indicates whether a machine-check exception was generated.

When a machine check exception is generated, it is expected that the MCIP flag in the IA32_MCG_STATUS

piece of hardware signaling an interrupt with vector 18.

When IA32_MCG_CAP [24] is 1, the following rules can apply when writing a machine check exception (MCE)

handler to support software recovery:

• The PCC flag in each IA32_MCi_STATUS register indicates whether recovery from the error is possible for

uncorrected errors (UC=1). If the PCC flag is set for enabled uncorrected errors (UC=1 and EN=1), recovery is

not possible. When recovery is not possible, the MCE handler typically records the error information and signals

the operating system to reset the system.

• The RIPV flag in the IA32_MCG_STATUS register indicates whether restarting the program execution from the

instruction pointer saved on the stack for the machine check exception is possible. When the RIPV is set,

program execution can be restarted reliably when recovery is possible. If the RIPV flag is not set, program

execution cannot be restarted reliably. In this case the recovery algorithm may involve terminating the current

program execution and resuming an alternate thread of execution upon return from the machine check handler

when recovery is possible. When recovery is not possible, the MCE handler signals the operating system to

reset the system.

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MACHINE-CHECK ARCHITECTURE

•

When the EN flag is zero but the VAL and UC flags are one in the IA32_MCi_STATUS register, the reported

uncorrected error in this bank is not enabled. As uncorrected errors with the EN flag = 0 are not the source of

machine check exceptions, the MCE handler should log and clear non-enabled errors when the S bit is set and

should continue searching for enabled errors from the other IA32_MCi_STATUS registers. Note that when

IA32_MCG_CAP [24] is 0, any uncorrected error condition (VAL =1 and UC=1) including the one with the EN

flag cleared are fatal and the handler must signal the operating system to reset the system. For the errors that

do not generate machine check exceptions, the EN flag has no meaning.

•

When the VAL flag is one, the UC flag is one, the EN flag is one and the PCC flag is zero in the IA32_MCi_STATUS

the S flag and the AR flag to find the type of the UCR error for software recovery and determine if software error

recovery is possible.

•

When both the S and the AR flags are clear in the IA32_MCi_STATUS register for the UCR error (VAL=1, UC=1,

EN=x and PCC=0), the error in this bank is an uncorrected no-action required error (UCNA). UCNA errors are

uncorrected but do not require any OS recovery action to continue execution. These errors indicate that some

data in the system is corrupt, but that data has not been consumed and may not be consumed. If that data is

consumed a non-UCNA machine check exception will be generated. UCNA errors are signaled in the same way

as corrected machine check errors and the CMCI and CMC polling handler is primarily responsible for handling

UCNA errors. Like corrected errors, the MCA handler can optionally log and clear UCNA errors as long as it can

avoid the undesired race condition with the CMCI or CMC polling handler. As UCNA errors are not the source of

machine check exceptions, the MCA handler should continue searching for uncorrected or software recoverable

errors in all other MC banks.

•

When the S flag in the IA32_MCi_STATUS register is set for the UCR error ((VAL=1, UC=1, EN=1 and PCC=0),

the error in this bank is software recoverable and it was signaled through a machine-check exception. The AR

flag in the IA32_MCi_STATUS register further clarifies the type of the software recoverable errors.

•

When the AR flag in the IA32_MCi_STATUS register is clear for the software recoverable error (VAL=1, UC=1,

EN=1, PCC=0 and S=1), the error in this bank is a software recoverable action optional (SRAO) error. The MCE

handler and the operating system can analyze the IA32_MCi_STATUS [15:0] to implement MCA error code

specific optional recovery action, but this recovery action is optional. System software can resume the program

execution from the instruction pointer saved on the stack for the machine check exception when the RIPV flag

in the IA32_MCG_STATUS register is set.

•

Even if the OVER flag in the IA32_MCi_STATUS register is set for the SRAO error (VAL=1, UC=1, EN=1, PCC=0,

S=1 and AR=0), the MCE handler can take recovery action for the SRAO error logged in the IA32_MCi_STATUS

instruction pointer saved on the stack for the machine check exception is still possible for the overflowed SRAO

error if the RIPV flag in the IA32_MCG_STATUS is set.

•

When the AR flag in the IA32_MCi_STATUS register is set for the software recoverable error (VAL=1, UC=1,

EN=1, PCC=0 and S=1), the error in this bank is a software recoverable action required (SRAR) error. The MCE

handler and the operating system must take recovery action in order to continue execution after the machine-

check exception. The MCA handler and the operating system need to analyze the IA32_MCi_STATUS [15:0] to

determine the MCA error code specific recovery action. If no recovery action can be performed, the operating

system must reset the system.

•

When the OVER flag in the IA32_MCi_STATUS register is set for the SRAR error (VAL=1, UC=1, EN=1, PCC=0,

S=1 and AR=1), the MCE handler cannot take recovery action as the information of the SRAR error in the

IA32_MCi_STATUS register was potentially lost due to the overflow condition. Since the recovery action for

SRAR errors must be taken, the MCE handler must signal the operating system to reset the system.

•

When the MCE handler cannot find any uncorrected (VAL=1, UC=1 and EN=1) or any software recoverable

errors (VAL=1, UC=1, EN=1, PCC=0 and S=1) in any of the IA32_MCi banks of the processors, this is an

unexpected condition for the MCE handler and the handler should signal the operating system to reset the

system.

•

Before returning from the machine-check exception handler, software must clear the MCIP flag in the IA32_MC-

G_STATUS register. The MCIP flag is used to detect recursion. The machine-check architecture does not support

recursion. When the processor receives a machine check when MCIP is set, it automatically enters the

shutdown state.

Example 16-4 gives pseudocode for an MC exception handler that supports recovery of UCR.

16-32

Vol. 3B

MACHINE-CHECK ARCHITECTURE

Example 16-4. Machine-Check Error Handler Pseudocode Supporting UCR

MACHINE CHECK HANDLER: (* Called from INT 18 handler *)

NOERROR = TRUE;

ProcessorCount = 0;

IF CPU supports MCA

THEN

RESTARTABILITY = TRUE;

IF (Processor Family = 6 AND DisplayModel ≥ 0EH) OR (Processor Family > 6)

THEN

IF ( MCG_LMCE = 1)

MCA_BROADCAST = FALSE;

ELSE

MCA_BROADCAST = TRUE;

FI;

Acquire SpinLock;

ProcessorCount++; (* Allowing one logical processor at a time to examine machine check registers *)

CALL MCA ERROR PROCESSING; (* returns RESTARTABILITY and NOERROR *)

ELSE

MCA_BROADCAST = FALSE;

(* Implement a rendezvous mechanism with the other processors if necessary *)

CALL MCA ERROR PROCESSING;

FI;

ELSE (* Pentium(R) processor compatible *)

READ P5_MC_ADDR

READ P5_MC_TYPE;

RESTARTABILITY = FALSE;

FI;

IF NOERROR = TRUE

THEN

IF NOT (MCG_RIPV = 1 AND MCG_EIPV = 0)

THEN

RESTARTABILITY = FALSE;

FI;

IF RESTARTABILITY = FALSE

THEN

Report RESTARTABILITY to console;

Reset system;

FI;

IF MCA_BROADCAST = TRUE

THEN

IF ProcessorCount = MAX_PROCESSORS

AND NOERROR = TRUE

THEN

Report RESTARTABILITY to console;

Reset system;

FI;

Release SpinLock;

Wait till ProcessorCount = MAX_PROCESSRS on system;

(* implement a timeout and abort function if necessary *)

FI;

CLEAR IA32_MCG_STATUS;

RESUME Execution;

(* End of MACHINE CHECK HANDLER*)

MCA ERROR PROCESSING:

(* MCA Error Processing Routine called from MCA Handler *)

IF MCIP flag in IA32_MCG_STATUS = 0

THEN (* MCIP=0 upon MCA is unexpected *)

RESTARTABILITY = FALSE;

FI;

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16-33

MACHINE-CHECK ARCHITECTURE

FOR each bank of machine-check registers

CLEAR_MC_BANK = FALSE;

READ IA32_MCi_STATUS;

IF VAL Flag in IA32_MCi_STATUS = 1

THEN

IF UC Flag in IA32_MCi_STATUS = 1

THEN

IF Bit 24 in IA32_MCG_CAP = 0

THEN (* the processor does not support software error recovery *)

RESTARTABILITY = FALSE;

NOERROR = FALSE;

GOTO LOG MCA REGISTER;

FI;

(* the processor supports software error recovery *)

IF EN Flag in IA32_MCi_STATUS = 0 AND OVER Flag in IA32_MCi_STATUS=0

THEN (* It is a spurious MCA Log. Log and clear the register *)

CLEAR_MC_BANK = TRUE;

GOTO LOG MCA REGISTER;

FI;

IF PCC = 1 and EN = 1 in IA32_MCi_STATUS

THEN (* processor context might have been corrupted *)

RESTARTABILITY = FALSE;

ELSE (* It is a uncorrected recoverable (UCR) error *)

IF S Flag in IA32_MCi_STATUS = 0

THEN

IF AR Flag in IA32_MCi_STATUS = 0

THEN (* It is a uncorrected no action required (UCNA) error *)

GOTO CONTINUE; (* let CMCI and CMC polling handler to process *)

ELSE

RESTARTABILITY = FALSE; (* S=0, AR=1 is illegal *)

FI;

IF RESTARTABILITY = FALSE

THEN (* no need to take recovery action if RESTARTABILITY is already false *)

NOERROR = FALSE;

GOTO LOG MCA REGISTER;

FI;

(* S in IA32_MCi_STATUS = 1 *)

IF AR Flag in IA32_MCi_STATUS = 1

THEN (* It is a software recoverable and action required (SRAR) error *)

IF OVER Flag in IA32_MCi_STATUS = 1

THEN

RESTARTABILITY = FALSE;

NOERROR = FALSE;

GOTO LOG MCA REGISTER;

IF MCACOD Value in IA32_MCi_STATUS is recognized

AND Current Processor is an Affected Processor

THEN

Implement MCACOD specific recovery action;

CLEAR_MC_BANK = TRUE;

ELSE

RESTARTABILITY = FALSE;

FI;

ELSE (* It is a software recoverable and action optional (SRAO) error *)

IF OVER Flag in IA32_MCi_STATUS = 0 AND

MCACOD in IA32_MCi_STATUS is recognized

THEN

Implement MCACOD specific recovery action;

FI;

CLEAR_MC_BANK = TRUE;

FI; AR

FI; PCC

NOERROR = FALSE;

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MACHINE-CHECK ARCHITECTURE

GOTO LOG MCA REGISTER;

ELSE (* It is a corrected error; continue to the next IA32_MCi_STATUS *)

GOTO CONTINUE;

FI; UC

FI; VAL

LOG MCA REGISTER:

SAVE IA32_MCi_STATUS;

If MISCV in IA32_MCi_STATUS

THEN

SAVE IA32_MCi_MISC;

FI;

IF ADDRV in IA32_MCi_STATUS

THEN

SAVE IA32_MCi_ADDR;

FI;

IF CLEAR_MC_BANK = TRUE

THEN

SET all 0 to IA32_MCi_STATUS;

If MISCV in IA32_MCi_STATUS

THEN

SET all 0 to IA32_MCi_MISC;

FI;

IF ADDRV in IA32_MCi_STATUS

THEN

SET all 0 to IA32_MCi_ADDR;

FI;

CONTINUE:

OD;

( *END FOR *)

RETURN;

(* End of MCA ERROR PROCESSING*)

16.10.4.2 Corrected Machine-Check Handler for Error Recovery

When writing a corrected machine check handler, which is invoked as a result of CMCI or called from an OS CMC

Polling dispatcher, consider the following:

• The VAL (valid) flag in each IA32_MCi_STATUS register indicates whether the error information in the register

is valid. If this flag is clear, the registers in that bank does not contain valid error information and does not need

to be checked.

• The CMCI or CMC polling handler is responsible for logging and clearing corrected errors. The UC flag in each

IA32_MCi_Status register indicates whether the reported error was corrected (UC=0) or not (UC=1).

• When IA32_MCG_CAP [24] is one, the CMC handler is also responsible for logging and clearing uncorrected no-

action required (UCNA) errors. When the UC flag is one but the PCC, S, and AR flags are zero in the IA32_M-

Ci_STATUS register, the reported error in this bank is an uncorrected no-action required (UCNA) error. In cases

when SRAO error are signaled as UCNA error via CMCI, software can perform recovery for those errors

identified in Table 16-16.

• In addition to corrected errors and UCNA errors, the CMC handler optionally logs uncorrected (UC=1 and

PCC=1), software recoverable machine check errors (UC=1, PCC=0 and S=1), but should avoid clearing those

errors from the MC banks. Clearing these errors may result in accidentally removing these errors before these

errors are actually handled and processed by the MCE handler for attempted software error recovery.

Example 16-5 gives pseudocode for a CMCI handler with UCR support.

Vol. 3B

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CHAPTER 17

INTERPRETING MACHINE CHECK ERROR CODES

Encoding of the model-specific and other information fields is different across processor families. The differences

are documented in the following sections.

17.1

INCREMENTAL DECODING INFORMATION: PROCESSOR FAMILY 06H,

MACHINE ERROR CODES FOR MACHINE CHECK

This section provides information for interpreting additional model-specific fields for external bus errors relating to

processor family 06H. The references to processor family 06H refers to only IA-32 processors with CPUID signa-

tures listed in Table 17-1.

Table 17-1. CPUID DisplayFamily_DisplayModel Signatures for Processor Family 06H

DisplayFamily_DisplayModel

Processor Families/Processor Number Series

06_0EH

Intel® Core™ Duo processor, Intel® Core™ Solo processor

06_0DH

Intel Pentium M processor

06_09H

Intel Pentium M processor

06_7H, 06_08H, 06_0AH, 06_0BH

Intel Pentium III Xeon Processor, Intel Pentium III Processor

06_03H, 06_05H

Intel Pentium II Xeon Processor, Intel Pentium II Processor

06_01H

Intel Pentium Pro Processor

These errors are reported in the IA32_MCi_STATUS MSRs. They are reported architecturally as compound errors

with a general form of 0000 1PPT RRRR IILL in the MCA error code field. See Chapter 16 for information on the

interpretation of compound error codes. Incremental decoding information is listed in Table 17-2.

Table 17-2. Incremental Decoding Information: Processor Family 06H Machine Error Codes for Machine Check

Type

Bit No.

Bit Function

Bit Description

MCA Error

15:0

Codes¹

Model Specific

18:16

Reserved

Errors

24:19

Bus Queue Request

000000: BQ_DCU_READ_TYPE error.

Type

000010: BQ_IFU_DEMAND_TYPE error.

000011: BQ_IFU_DEMAND_NC_TYPE error.

000100: BQ_DCU_RFO_TYPE error.

000101: BQ_DCU_RFO_LOCK_TYPE error.

000110: BQ_DCU_ITOM_TYPE error.

001000: BQ_DCU_WB_TYPE error.

001010: BQ_DCU_WCEVICT_TYPE error.

001011: BQ_DCU_WCLINE_TYPE error.

001100: BQ_DCU_BTM_TYPE error.

Vol. 3B

17-1

INTERPRETING MACHINE CHECK ERROR CODES

Table 17-2. Incremental Decoding Information: Processor Family 06H Machine Error Codes for Machine Check

Type

Bit No.

Bit Function

Bit Description

001101: BQ_DCU_INTACK_TYPE error.

001110: BQ_DCU_INVALL2_TYPE error.

001111: BQ_DCU_FLUSHL2_TYPE error.

010000: BQ_DCU_PART_RD_TYPE error.

010010: BQ_DCU_PART_WR_TYPE error.

010100: BQ_DCU_SPEC_CYC_TYPE error.

011000: BQ_DCU_IO_RD_TYPE error.

011001: BQ_DCU_IO_WR_TYPE error.

011100: BQ_DCU_LOCK_RD_TYPE error.

011110: BQ_DCU_SPLOCK_RD_TYPE error.

011101: BQ_DCU_LOCK_WR_TYPE error.

27:25

Bus Queue Error Type

000: BQ_ERR_HARD_TYPE error.

001: BQ_ERR_DOUBLE_TYPE error.

010: BQ_ERR_AERR2_TYPE error.

100: BQ_ERR_SINGLE_TYPE error.

101: BQ_ERR_AERR1_TYPE error.

FRC Error

1 if FRC error active.

BERR

1 if BERR is driven.

Internal BINIT

1 if BINIT driven for this processor.

Reserved

Other

34:32

Reserved

Information

External BINIT

1 if BINIT is received from external bus.

Response Parity Error

This bit is asserted in IA32_MCi_STATUS if this component has received a parity

error on the RS[2:0]# pins for a response transaction. The RS signals are checked

by the RSP# external pin.

Bus BINIT

This bit is asserted in IA32_MCi_STATUS if this component has received a hard

error response on a split transaction one access that has needed to be split across

the 64-bit external bus interface into two accesses).

Timeout BINIT

This bit is asserted in IA32_MCi_STATUS if this component has experienced a ROB

time-out, which indicates that no micro-instruction has been retired for a

predetermined period of time.

A ROB time-out occurs when the 15-bit ROB time-out counter carries a 1 out of its

high order bit. ² The timer is cleared when a micro-instruction retires, an exception

is detected by the core processor, RESET is asserted, or when a ROB BINIT occurs.

The ROB time-out counter is prescaled by the 8-bit PIC timer which is a divide by

128 of the bus clock (the bus clock is 1:2, 1:3, 1:4 of the core clock³). When a carry

out of the 8-bit PIC timer occurs, the ROB counter counts up by one. While this bit is

asserted, it cannot be overwritten by another error.

41:39

Reserved

Hard Error

This bit is asserted in IA32_MCi_STATUS if this component has initiated a bus

transactions which has received a hard error response. While this bit is asserted, it

cannot be overwritten.

IERR

This bit is asserted in IA32_MCi_STATUS if this component has experienced a

failure that causes the IERR pin to be asserted. While this bit is asserted, it cannot

be overwritten.

17-2

Vol. 3B

INTERPRETING MACHINE CHECK ERROR CODES

Table 17-2. Incremental Decoding Information: Processor Family 06H Machine Error Codes for Machine Check

Type

Bit No.

Bit Function

Bit Description

AERR

This bit is asserted in IA32_MCi_STATUS if this component has initiated 2 failing

bus transactions which have failed due to Address Parity Errors AERR asserted).

While this bit is asserted, it cannot be overwritten.

UECC

The Uncorrectable ECC error bit is asserted in IA32_MCi_STATUS for uncorrected

ECC errors. While this bit is asserted, the ECC syndrome field will not be

overwritten.

CECC

The correctable ECC error bit is asserted in IA32_MCi_STATUS for corrected ECC

errors.

54:47

ECC Syndrome

The ECC syndrome field in IA32_MCi_STATUS contains the 8-bit ECC syndrome only

if the error was a correctable/uncorrectable ECC error and there wasn't a previous

valid ECC error syndrome logged in IA32_MCi_STATUS.

A previous valid ECC error in IA32_MCi_STATUS is indicated by

IA32_MCi_STATUS.bit45 uncorrectable error occurred) being asserted. After

processing an ECC error, machine check handling software should clear

IA32_MCi_STATUS.bit45 so that future ECC error syndromes can be logged.

56:55

Reserved

Status Register

63:57

Validity

Indicators¹

NOTES:

1. These fields are architecturally defined. Refer to Chapter 16, “Machine-Check Architecture,” for more information.

2. For processors with a CPUID signature of 06_0EH, a ROB time-out occurs when the 23-bit ROB time-out counter carries a 1 out of its

high order bit.

3. For processors with a CPUID signature of 6_06_60H and later, the PIC timer will count crystal clock cycles.

17.2

INCREMENTAL DECODING INFORMATION: INTEL® CORE™ 2 PROCESSOR

FAMILY, MACHINE ERROR CODES FOR MACHINE CHECK

Table 17-4 provides information for interpreting additional model-specific fields for external bus errors relating to

processors based on Intel^® Core™ microarchitecture, which implements the P4 bus specification. Table 17-3 lists

the CPUID signatures for Intel 64 processors that are covered by Table 17-4. These errors are reported in the

IA32_MCi_STATUS MSRs. They are reported architecturally as compound errors with a general form of

0000 1PPT RRRR IILL in the MCA error code field. See Chapter 16 for information on the interpretation of

compound error codes.

Table 17-3. CPUID DisplayFamily_DisplayModel Signatures for Processors Based on Intel® Core™ Microarchitecture

DisplayFamily_DisplayModel

Processor Families/Processor Number Series

06_1DH

Intel® Xeon® Processor 7400 series

06_17H

Intel® Xeon® Processor 5200, 5400 series, Intel® Core™ 2 Quad processor Q9650

06_0FH

Intel® Xeon® Processor 3000, 3200, 5100, 5300, 7300 series, Intel® Core™ 2 Quad, Intel® Core™ 2

Extreme, Intel® Core™ 2 Duo processors, Intel Pentium dual-core processors

Vol. 3B

17-3

INTERPRETING MACHINE CHECK ERROR CODES

Table 17-4. Incremental Bus Error Codes of Machine Check for Processors

Based on Intel® Core™ Microarchitecture

Type

Bit No.

Bit Function

Bit Description

MCA Error

15:0

Codes¹

Model Specific

18:16

Reserved

Errors

24:19

Bus Queue Request

‘000001: BQ_PREF_READ_TYPE error.

Type

000000: BQ_DCU_READ_TYPE error.

000010: BQ_IFU_DEMAND_TYPE error

000011: BQ_IFU_DEMAND_NC_TYPE error.

000100: BQ_DCU_RFO_TYPE error.

000101: BQ_DCU_RFO_LOCK_TYPE error.

000110: BQ_DCU_ITOM_TYPE error.

001000: BQ_DCU_WB_TYPE error.

001010: BQ_DCU_WCEVICT_TYPE error.

001011: BQ_DCU_WCLINE_TYPE error.

001100: BQ_DCU_BTM_TYPE error.

001101: BQ_DCU_INTACK_TYPE error.

001110: BQ_DCU_INVALL2_TYPE error.

001111: BQ_DCU_FLUSHL2_TYPE error.

010000: BQ_DCU_PART_RD_TYPE error.

010010: BQ_DCU_PART_WR_TYPE error.

010100: BQ_DCU_SPEC_CYC_TYPE error.

011000: BQ_DCU_IO_RD_TYPE error.

011001: BQ_DCU_IO_WR_TYPE error.

011100: BQ_DCU_LOCK_RD_TYPE error.

011110: BQ_DCU_SPLOCK_RD_TYPE error.

011101: BQ_DCU_LOCK_WR_TYPE error.

100100: BQ_L2_WI_RFO_TYPE error.

100110: BQ_L2_WI_ITOM_TYPE error.

27:25

Bus Queue Error Type

‘001: Address Parity Error.

‘010: Response Hard Error.

‘011: Response Parity Error.

MCE Driven

1 if MCE is driven.

MCE Observed

1 if MCE is observed.

Internal BINIT

1 if BINIT driven for this processor.

BINIT Observed

1 if BINIT is observed for this processor.

Other

33:32

Reserved

Information

PIC and FSB Data

Data Parity detected on either PIC or FSB access.

Parity

Reserved

Response Parity Error

This bit is asserted in IA32_MCi_STATUS if this component has received a parity

error on the RS[2:0]# pins for a response transaction. The RS signals are checked

by the RSP# external pin.

17-4

Vol. 3B

INTERPRETING MACHINE CHECK ERROR CODES

Table 17-4. Incremental Bus Error Codes of Machine Check for Processors

Based on Intel® Core™ Microarchitecture (Contd.)

Type

Bit No.

Bit Function

Bit Description

FSB Address Parity

Address parity error detected:

1: Address parity error detected.

0: No address parity error.

Timeout BINIT

This bit is asserted in IA32_MCi_STATUS if this component has experienced a ROB

time-out, which indicates that no micro-instruction has been retired for a

predetermined period of time.

A ROB time-out occurs when the 23-bit ROB time-out counter carries a 1 out of its

high order bit. The timer is cleared when a micro-instruction retires, an exception is

detected by the core processor, RESET is asserted, or when a ROB BINIT occurs.

The ROB time-out counter is prescaled by the 8-bit PIC timer which is a divide by

128 of the bus clock the bus clock is 1:2, 1:3, 1:4 of the core clock). When a carry

out of the 8-bit PIC timer occurs, the ROB counter counts up by one. While this bit is

asserted, it cannot be overwritten by another error.

41:39

Reserved

Hard Error

This bit is asserted in IA32_MCi_STATUS if this component has initiated a bus

transactions which has received a hard error response. While this bit is asserted, it

cannot be overwritten.

IERR

This bit is asserted in IA32_MCi_STATUS if this component has experienced a

failure that causes the IERR pin to be asserted. While this bit is asserted, it cannot

be overwritten.

Reserved

54:47

Reserved

56:55

Reserved

Reserved.

Status Register

63:57

Validity

Indicators¹

NOTES:

1. These fields are architecturally defined. Refer to Chapter 16, “Machine-Check Architecture,” for more information.

17.2.1 Model-Specific Machine Check Error Codes for Intel® Xeon® Processor 7400 Series

The Intel^® Xeon^® processor 7400 series has machine check register banks that generally follow the description of

Chapter 16 and Section 17.2. Additional error codes specific to the Intel Xeon processor 7400 series are described

in this section.

MC4_STATUS[63:0] is the main error logging for the processor’s L3 and front side bus errors for the Intel Xeon

processor 7400 series. It supports the L3 Errors, Bus and Interconnect Errors Compound Error Codes in the MCA

Error Code Field.

Vol. 3B

17-5

INTERPRETING MACHINE CHECK ERROR CODES

17.2.1.1 Processor Machine Check Status Register, Incremental MCA Error Code Definition

The Intel Xeon processor 7400 series uses compound MCA Error Codes for logging its Bus internal machine check

errors, L3 Errors, and Bus/Interconnect Errors. It defines incremental Machine Check error types

(IA32_MC6_STATUS[15:0]) beyond those defined in Chapter 16. Table 17-5 lists these incremental MCA error

code types that apply to IA32_MC6_STATUS. Error code details are specified in MC6_STATUS [31:16] (see

Section 17.2.2), the “Model Specific Error Code” field. The information in the “Other_Info” field

(MC4_STATUS[56:32]) is common to the three processor error types. It contains a correctable event count and

specifies the MC6_MISC register format.

Table 17-5. Incremental MCA Error Code Types for Intel® Xeon® Processor 7400

Processor MCA_Error_Code (MC6_STATUS[15:0])

Type

Error Code

Binary Encoding

Meaning

Internal Error

0000 0100 0000 0000

Internal Error Type Code.

Bus and

0000 100x 0000 1111

Not used but this encoding is reserved for compatibility with other MCA

Interconnect

implementations.

Error

0000 101x 0000 1111

Not used but this encoding is reserved for compatibility with other MCA

implementations.

0000 110x 0000 1111

Not used but this encoding is reserved for compatibility with other MCA

implementations.

0000 1110 0000 1111

Bus and Interconnection Error Type Code.

0000 1111 0000 1111

Not used but this encoding is reserved for compatibility with other MCA

implementations.

The Bold faced binary encodings are the only encodings used by the processor for MC4_STATUS[15:0].

17.2.2 Intel® Xeon® Processor 7400 Model Specific Error Code Field

17.2.2.1 Processor Model Specific Error Code Field, Type B: Bus and Interconnect Error Codes

The Model Specific Error Code field in MC6_STATUS (bits 31:16) is defined in Table 17-6.

Table 17-6. Type B: Bus and Interconnect Error Codes

Bit Number

Sub-Field Name

Description

FSB Request Parity

Parity error detected during FSB request phase.

19:17

Reserved

FSB Hard Fail Response

“Hard Failure“ response received for a local transaction.

FSB Response Parity

Parity error on FSB response field detected.

FSB Data Parity

FSB data parity error on inbound data detected.

31:23

Reserved

17-6

Vol. 3B

INTERPRETING MACHINE CHECK ERROR CODES

17.2.2.2 Processor Model Specific Error Code Field, Type C: Cache Bus Controller Error Codes

Table 17-7. Type C: Cache Bus Controller Error Codes

MC4_STATUS[31:16] (MSCE) Value

Error Description

0000_0000_0000_0001 0001H

Inclusion Error from Core 0.

0000_0000_0000_0010 0002H

Inclusion Error from Core 1.

0000_0000_0000_0011 0003H

Write Exclusive Error from Core 0.

0000_0000_0000_0100 0004H

Write Exclusive Error from Core 1.

0000_0000_0000_0101 0005H

Inclusion Error from FSB.

0000_0000_0000_0110 0006H

SNP Stall Error from FSB.

0000_0000_0000_0111 0007H

Write Stall Error from FSB.

0000_0000_0000_1000 0008H

FSB Arb Timeout Error.

0000_0000_0000_1010 000AH

Inclusion Error from Core 2.

0000_0000_0000_1011 000BH

Write Exclusive Error from Core 2.

0000_0010_0000_0000 0200H

Internal Timeout Error.

0000_0011_0000_0000 0300H

Internal Timeout Error.

0000_0100_0000_0000 0400H

Intel® Cache Safe Technology Queue Full Error or Disabled-ways-in-a-set overflow.

0000_0101_0000_0000 0500H

Quiet cycle Timeout Error (correctable).

1100_0000_0000_0010 C002H

Correctable ECC event on outgoing Core 0 data.

1100_0000_0000_0100 C004H

Correctable ECC event on outgoing Core 1 data.

1100_0000_0000_1000 C008H

Correctable ECC event on outgoing Core 2 data.

1110_0000_0000_0010 E002H

Uncorrectable ECC error on outgoing Core 0 data.

1110_0000_0000_0100 E004H

Uncorrectable ECC error on outgoing Core 1 data.

1110_0000_0000_1000 E008H

Uncorrectable ECC error on outgoing Core 2 data.

— All other encodings —

Reserved

17.3

INCREMENTAL DECODING INFORMATION: INTEL® XEON® PROCESSOR

3400, 3500, 5500 SERIES, MACHINE ERROR CODES FOR MACHINE CHECK

Table 17-8 through Table 17-12 provide information for interpreting additional model-specific fields for memory

controller errors relating to the Intel^® Xeon^® processor 3400, 3500, 5500 series with CPUID DisplayFamily_Dis-

playSignature 06_1AH, which supports Intel^® QuickPath Interconnect links. Incremental MC error codes related to

the Intel QPI links are reported in the register banks IA32_MC0 and IA32_MC1, incremental error codes for internal

machine check are reported in the register bank IA32_MC7, and incremental error codes for the memory controller

unit are reported in the register bank IA32_MC8.

Vol. 3B

17-7

INTERPRETING MACHINE CHECK ERROR CODES

17.3.1 Intel® QPI Machine Check Errors

Table 17-8. Intel® QPI Machine Check Error Codes for IA32_MC0_STATUS and IA32_MC1_STATUS

Type

Bit No.

Bit Function

Bit Description

MCA Error Codes¹

15:0

MCACOD

Bus error format: 1PPTRRRRIILL

Model Specific Errors

Header Parity

If 1, QPI Header had bad parity.

Data Parity

If 1, QPI Data packet had bad parity.

Retries Exceeded

If 1, the number of QPI retries was exceeded.

Received Poison

if 1, received a data packet that was marked as poisoned by the sender.

21:20

Reserved

Unsupported Message

If 1, QPI received a message encoding it does not support.

Unsupported Credit

If 1, QPI credit type is not supported.

Receive Flit Overrun

If 1, sender sent too many QPI flits to the receiver.

Received Failed Response

If 1, indicates that sender sent a failed response to receiver.

Receiver Clock Jitter

If 1, clock jitter detected in the internal QPI clocking.

56:27

Reserved

Status Register

63:57

Validity Indicators¹

NOTES:

1. These fields are architecturally defined. Refer to Chapter 16, “Machine-Check Architecture,” for more information.

Table 17-9. Intel® QPI Machine Check Error Codes for IA32_MC0_MISC and IA32_MC1_MISC

Type

Bit No.

Bit Function

Bit Description

Model Specific

7:0

QPI Opcode

Message class and opcode from the packet with the error.

Errors¹

13:8

RTID

QPI Request Transaction ID.

15:14

Reserved

18:16

RHNID

QPI Requestor/Home Node ID.

23:19

Reserved

IIB

QPI Interleave/Head Indication Bit.

NOTES:

1. Which of these fields are valid depends on the error type.

17-8

Vol. 3B

INTERPRETING MACHINE CHECK ERROR CODES

17.3.2 Internal Machine Check Errors

Table 17-10. Machine Check Error Codes for IA32_MC7_STATUS

Type

Bit No.

Bit Function

Bit Description

MCA Error Codes¹

15:0

MCACOD

Model Specific Errors

23:16

Reserved

31:24

Reserved, except for the

00H: No error.

following

03H: Reset firmware did not complete.

08H: Received an invalid CMPD.

0AH: Invalid Power Management Request.

0DH: Invalid S-state transition.

11H: VID controller does not match POC controller selected.

1AH: MSID from POC does not match CPU MSID.

56:32

Reserved

Status Register

63:57

Validity Indicators¹

NOTES:

1. These fields are architecturally defined. Refer to Chapter 16, “Machine-Check Architecture,” for more information.

17.3.3 Memory Controller Errors

Table 17-11. Incremental Memory Controller Error Codes of Machine Check for IA32_MC8_STATUS

Type

Bit No.

Bit Function

Bit Description

MCA Error Codes¹

15:0

MCACOD

Memory error format: 1MMMCCCC

Model Specific Errors

Read ECC Error

If 1, ECC occurred on a read.

RAS ECC Error

If 1, ECC occurred on a scrub.

Write Parity Error

If 1, bad parity on a write.

Redundancy Loss

if 1, error in half of redundant memory.

Reserved

Memory Range Error

If 1, memory access out of range.

RTID Out of Range

If 1, Internal ID invalid.

Address Parity Error

If 1, bad address parity.

Byte Enable Parity

If 1, bad enable parity.

Error

Other Information

37:25

Reserved

52:38

CORE_ERR_CNT

Corrected error count.

56:53

Reserved

Status Register Validity

63:57

Indicators¹

NOTES:

1. These fields are architecturally defined. Refer to Chapter 16, “Machine-Check Architecture,” for more information.

Vol. 3B

17-9

INTERPRETING MACHINE CHECK ERROR CODES

Table 17-12. Incremental Memory Controller Error Codes of Machine Check for IA32_MC8_MISC

Type

Bit No.

Bit Function

Bit Description

Model Specific

7:0

RTID

Transaction Tracker ID.

Errors¹

15:8

Reserved

17:16

DIMM

DIMM ID which received the error.

19:18

Channel

Channel ID which received the error.

31:20

Reserved

63:32

Syndrome

ECC Syndrome.

NOTES:

1. Which of these fields are valid depends on the error type.

17.4

INCREMENTAL DECODING INFORMATION: INTEL® XEON® PROCESSOR E5

FAMILY, MACHINE ERROR CODES FOR MACHINE CHECK

Table 17-13 through Table 17-15 provide information for interpreting additional model-specific fields for memory

controller errors relating to the Intel^® Xeon^® processor E5 Family with CPUID DisplayFamily_DisplaySignature

06_2DH, which supports Intel QuickPath Interconnect links. Incremental MC error codes related to the Intel QPI

links are reported in the register banks IA32_MC6 and IA32_MC7, incremental error codes for internal machine

check error from PCU controller are reported in the register bank IA32_MC4, and incremental error codes for the

memory controller unit are reported in the register banks IA32_MC8—IA32_MC11.

17.4.1 Internal Machine Check Errors

Table 17-13. Machine Check Error Codes for IA32_MC4_STATUS

Type

Bit No.

Bit Function

Bit Description

MCA Error Codes¹

15:0

MCACOD

Model Specific Errors

19:16

Reserved, except for the

0000b: No Error

following

0001b: Non_IMem_Sel

0010b: I_Parity_Error

0011b: Bad_OpCode

0100b: I_Stack_Underflow

0101b: I_Stack_Overflow

0110b: D_Stack_Underflow

0111b: D_Stack_Overflow

1000b: Non-DMem_Sel

1001b: D_Parity_Error

17-10

Vol. 3B

INTERPRETING MACHINE CHECK ERROR CODES

Table 17-13. Machine Check Error Codes for IA32_MC4_STATUS (Contd.)

Type

Bit No.

Bit Function

Bit Description

23:20

Reserved

31:24

Reserved, except for the

00H: No Error

following

0DH: MC_IMC_FORCE_SR_S3_TIMEOUT

0EH: MC_CPD_UNCPD_ST_TIMEOUT

0FH: MC_PKGS_SAFE_WP_TIMEOUT

43H: MC_PECI_MAILBOX_QUIESCE_TIMEOUT

5CH: MC_MORE_THAN_ONE_LT_AGENT

60H: MC_INVALID_PKGS_REQ_PCH

61H: MC_INVALID_PKGS_REQ_QPI

62H: MC_INVALID_PKGS_RES_QPI

63H: MC_INVALID_PKGC_RES_PCH

64H: MC_INVALID_PKG_STATE_CONFIG

70H: MC_WATCHDG_TIMEOUT_PKGC_SECONDARY

71H: MC_WATCHDG_TIMEOUT_PKGC_MAIN

72H: MC_WATCHDG_TIMEOUT_PKGS_MAIN

7AH: MC_HA_FAILSTS_CHANGE_DETECTED

81H: MC_RECOVERABLE_DIE_THERMAL_TOO_HOT

56:32

Reserved

Status Register

63:57

Validity Indicators

NOTES:

1. These fields are architecturally defined. Refer to Chapter 16, “Machine-Check Architecture,” for more information.

17.4.2 Intel® QPI Machine Check Errors

Table 17-14. Intel® QPI MC Error Codes for IA32_MC6_STATUS and IA32_MC7_STATUS

Type

Bit No.

Bit Function

Bit Description

MCA Error Codes¹

15:0

MCACOD

Bus error format: 1PPTRRRRIILL

Model Specific Errors

56:16

Reserved

Status Register

63:57

Validity Indicators¹

NOTES:

1. These fields are architecturally defined. Refer to Chapter 16, “Machine-Check Architecture,” for more information.

17.4.3 Integrated Memory Controller Machine Check Errors

MC error codes associated with integrated memory controllers are reported in the IA32_MC8_STATUS−

IA32_MC11_STATUS MSRs. The supported error codes follow the architectural MCACOD definition type

1MMMCCCC; see Chapter 16, “Machine-Check Architecture.” MSR_ERROR_CONTROL.[bit 1] can enable additional

information logging of the IMC. The additional error information logged by the IMC is stored in the IA32_M-

Ci_STATUS and IA32_MCi_MISC, where i = 8, 11.

Vol. 3B

17-11

INTERPRETING MACHINE CHECK ERROR CODES

Table 17-15. Intel IMC MC Error Codes for IA32_MCi_STATUS (i= 8, 11)

Type

Bit No.

Bit Function

Bit Description

MCA Error Codes¹

15:0

MCACOD

Bus error format: 1PPTRRRRIILL

Model Specific Errors

31:16

Reserved, except for the

001H: Address parity error.

following

002H: HA Wrt buffer Data parity error.

004H: HA Wrt byte enable parity error.

008H: Corrected patrol scrub error.

010H: Uncorrected patrol scrub error.

020H: Corrected spare error.

040H: Uncorrected spare error.

36:32

Other Info

When MSR_ERROR_CONTROL.[1] is set, allows the iMC to log first device

error when corrected error is detected during normal read.

Reserved

56:38

See Chapter 16, “Machine-Check Architecture.”

Status Register

63:57

Validity Indicators¹

NOTES:

1. These fields are architecturally defined. Refer to Chapter 16, “Machine-Check Architecture,” for more information.

Table 17-16. Intel IMC MC Error Codes for IA32_MCi_MISC (i= 8, 11)

Type

Bit No.

Bit Function

Bit Description

MCA Addr Info¹

8:0

See Chapter 16, “Machine-Check Architecture.”

Model Specific Errors

13:9

• When MSR_ERROR_CONTROL.[1] is set, allows the iMC to log second

device error when corrected error is detected during normal read.

• Otherwise, contains parity error if MCi_Status indicates HA_WB_Data

or HA_W_BE parity error.