Intel 64 and IA-32 Architectures. Software Developer’s Manual (Collection, 2023)

INSTRUCTION SET REFERENCE, M-U

UD-Undefined Instruction

Opcode

Instruction

Op/

64-Bit

Compat/

Description

Mode

Leg Mode

0F FF /r

UD0¹ r32, r/m32

Valid

Raise invalid opcode exception.

0F B9 /r

UD1 r32, r/m32

Valid

Raise invalid opcode exception.

0F 0B

UD2

Valid

Raise invalid opcode exception.

NOTES:

1. Some processors decode the UD0 instruction without a ModR/M byte. As a result, those processors would deliver an invalid-opcode

exception instead of a fault on instruction fetch when the instruction with a ModR/M byte (and any implied bytes) would cross a page

or segment boundary.

Instruction Operand Encoding

Op/En

Operand 1

Operand 2

Operand 3

Operand 4

N/A

ModRM:reg (r)

ModRM:r/m (r)

N/A

Description

Generates an invalid opcode exception. This instruction is provided for software testing to explicitly generate an

invalid opcode exception. The opcodes for this instruction are reserved for this purpose.

Other than raising the invalid opcode exception, this instruction has no effect on processor state or memory.

Even though it is the execution of the UD instruction that causes the invalid opcode exception, the instruction

pointer saved by delivery of the exception references the UD instruction (and not the following instruction).

This instruction’s operation is the same in non-64-bit modes and 64-bit mode.

Operation

#UD (* Generates invalid opcode exception *);

Flags Affected

None.

Exceptions (All Operating Modes)

#UD

Raises an invalid opcode exception in all operating modes.

UD-Undefined Instruction

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INSTRUCTION SET REFERENCE, M-U

UIRET-User-Interrupt Return

Opcode/

Op/

64/32 bit

CPUID Feature

Description

Instruction

Mode

Flag

Support

F3 0F 01 EC

V/I

UINTR

Return from handling a user interrupt.

UIRET

Instruction Operand Encoding

Op/En

Tuple

Operand 1

Operand 2

Operand 3

Operand 4

N/A

Description

UIRET returns from the handling of a user interrupt. It can be executed regardless of CPL.

Execution of UIRET inside a transactional region causes a transactional abort; the abort loads EAX as it would have

had it been due to an execution of IRET.

UIRET can be tracked by Architectural Last Branch Records (LBRs), Intel Processor Trace (Intel PT), and Perfor-

mance Monitoring. For both Intel PT and LBRs, UIRET is recorded in precisely the same manner as IRET. Hence for

LBRs, UIRETs fall into the OTHER_BRANCH category, which implies that IA32_LBR_CTL.OTHER_BRANCH[bit 22]

must be set to record user-interrupt delivery, and that the IA32_LBR_x_INFO.BR_TYPE field will indicate

OTHER_BRANCH for any recorded user interrupt. For Intel PT, control flow tracing must be enabled by setting

IA32_RTIT_CTL.BranchEn[bit 13].

UIRET will also increment performance counters for which counting BR_INST_RETIRED.FAR_BRANCH is enabled.

Operation

Pop tempRIP;

Pop tempRFLAGS; // see below for how this is used to load RFLAGS

Pop tempRSP;

IF tempRIP is not canonical in current paging mode

THEN #GP(0);

FI;

IF ShadowStackEnabled(CPL)

THEN

PopShadowStack SSRIP;

IF SSRIP ≠ tempRIP

THEN #CP (FAR-RET/IRET);

FI;

RIP := tempRIP;

// update in RFLAGS only CF, PF, AF, ZF, SF, TF, DF, OF, NT, RF, AC, and ID

RFLAGS := (RFLAGS & ~254DD5H) | (tempRFLAGS & 254DD5H);

RSP := tempRSP;

UIF := 1;

Clear any cache-line monitoring established by MONITOR or UMONITOR;

Flags Affected

See the Operation section.

Protected Mode Exceptions

#UD

The UIRET instruction is not recognized in protected mode.

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INSTRUCTION SET REFERENCE, M-U

Real-Address Mode Exceptions

#UD

The UIRET instruction is not recognized in real-address mode.

Virtual-8086 Mode Exceptions

#UD

The UIRET instruction is not recognized in virtual-8086 mode.

Compatibility Mode Exceptions

#UD

The UIRET instruction is not recognized in compatibility mode.

64-Bit Mode Exceptions

#GP(0)

If the return instruction pointer is non-canonical.

#SS(0)

If an attempt to pop a value off the stack causes a non-canonical address to be referenced.

#PF(fault-code)

If a page fault occurs.

#AC(0)

If alignment checking is enabled and an unaligned memory reference is made while the

current privilege level is 3.

#CP

If return instruction pointer from stack and shadow stack do not match.

#UD

If the LOCK prefix is used.

If executed inside an enclave.

If CR4.UINTR = 0.

If CPUID.07H.0H:EDX.UINTR[bit 5] = 0.

UIRET-User-Interrupt Return

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INSTRUCTION SET REFERENCE, M-U

UMONITOR-User Level Set Up Monitor Address

Opcode /

Op/

64/32 bit

CPUID

Description

Instruction

Mode

Feature

Support

Flag

F3 0F AE /6

V/V

WAITPKG

Sets up a linear address range to be monitored by

hardware and activates the monitor. The address range

UMONITOR r16/r32/r64

should be a write-back memory caching type. The

address is contained in r16/r32/r64.

Instruction Operand Encoding¹

Op/En

Tuple

Operand 1

Operand 2

Operand 3

Operand 4

N/A

ModRM:r/m (r)

N/A

Description

The UMONITOR instruction arms address monitoring hardware using an address specified in the source register

(the address range that the monitoring hardware checks for store operations can be determined by using the

CPUID monitor leaf function, EAX=05H). A store to an address within the specified address range triggers the

monitoring hardware. The state of monitor hardware is used by UMWAIT.

The content of the source register is an effective address. By default, the DS segment is used to create a linear

address that is monitored. Segment overrides can be used. The address range must use memory of the write-back

type. Only write-back memory is guaranteed to correctly trigger the monitoring hardware. Additional information

on determining what address range to use in order to prevent false wake-ups is described in Chapter 9, “Multiple-

Processor Management‚” of the Intel^®64 and IA-32 Architectures Software Developer’s Manual, Volume 3A.

The UMONITOR instruction is ordered as a load operation with respect to other memory transactions. The instruc-

tion is subject to the permission checking and faults associated with a byte load. Like a load, UMONITOR sets the

A-bit but not the D-bit in page tables.

UMONITOR and UMWAIT are available when CPUID.7.0:ECX.WAITPKG[bit 5] is enumerated as 1. UMONITOR and

UMWAIT may be executed at any privilege level. Except for the width of the source register, the instruction’s oper-

ation is the same in non-64-bit modes and in 64-bit mode.

UMONITOR does not interoperate with the legacy MWAIT instruction. If UMONITOR was executed prior to executing

MWAIT and following the most recent execution of the legacy MONITOR instruction, MWAIT will not enter an opti-

mized state. Execution will continue to the instruction following MWAIT.

The UMONITOR instruction causes a transactional abort when used inside a transactional region.

The width of the source register (16b, 32b or 64b) is determined by the effective addressing width, which is

affected in the standard way by the machine mode settings and 67 prefix.

Operation

UMONITOR sets up an address range for the monitor hardware using the content of source register as an effective

address and puts the monitor hardware in armed state. A store to the specified address range will trigger the

monitor hardware.

Intel C/C++ Compiler Intrinsic Equivalent

UMONITOR void _umonitor(void *address);

Numeric Exceptions

None.

1. The Mod field of the ModR/M byte must have value 11B.

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INSTRUCTION SET REFERENCE, M-U

Protected Mode Exceptions

#GP(0)

If the specified segment is not SS and the source register is outside the specified segment

limit.

If the specified segment register contains a NULL segment selector.

#SS(0)

If the specified segment is SS and the source register is outside the SS segment limit.

#PF(fault-code)

For a page fault.

#UD

If CPUID.7.0:ECX.WAITPKG[bit 5]=0.

Real Address Mode Exceptions

#GP

If the specified segment is not SS and the source register is outside of the effective address

space from 0 to FFFFH.

#SS

If the specified segment is SS and the source register is outside of the effective address space

from 0 to FFFFH.

#UD

If CPUID.7.0:ECX.WAITPKG[bit 5]=0.

Virtual 8086 Mode Exceptions

Same exceptions as in real address mode; additionally:

#PF(fault-code)

For a page fault.

Compatibility Mode Exceptions

Same exceptions as in protected mode.

64-Bit Mode Exceptions

#GP(0)

If the specified segment is not SS and the linear address is in non-canonical form.

#SS(0)

If the specified segment is SS and the source register is in non-canonical form.

#PF(fault-code)

For a page fault.

#UD

If CPUID.7.0:ECX.WAITPKG[bit 5]=0.

UMONITOR-User Level Set Up Monitor Address

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INSTRUCTION SET REFERENCE, M-U

UMWAIT-User Level Monitor Wait

Opcode /

Op/

64/32 bit

CPUID

Description

Instruction

Mode

Feature

Support

Flag

F2 0F AE /6

V/V

WAITPKG

A hint that allows the processor to stop instruction

execution and enter an implementation-dependent

UMWAIT r32, <edx>, <eax>

optimized state until occurrence of a class of events.

Instruction Operand Encoding¹

Op/En

Tuple

Operand 1

Operand 2

Operand 3

Operand 4

N/A

ModRM:r/m (r)

N/A

Description

UMWAIT instructs the processor to enter an implementation-dependent optimized state while monitoring a range

of addresses. The optimized state may be either a light-weight power/performance optimized state or an improved

power/performance optimized state. The selection between the two states is governed by the explicit input register

bit[0] source operand.

UMWAIT is available when CPUID.7.0:ECX.WAITPKG[bit 5] is enumerated as 1. UMWAIT may be executed at any

privilege level. This instruction’s operation is the same in non-64-bit modes and in 64-bit mode.

The input register contains information such as the preferred optimized state the processor should enter as

described in the following table. Bits other than bit 0 are reserved and will result in #GP if nonzero.

Table 4-21. UMWAIT Input Register Bit Definitions

Bit Value

State Name

Wakeup Time

Power Savings

Other Benefits

bit[0] = 0

C0.2

Slower

Larger

Improves performance of the other SMT thread(s) on the same core.

bit[0] = 1

C0.1

Faster

Smaller

N/A

bits[31:1]

N/A

Reserved

The instruction wakes up when the time-stamp counter reaches or exceeds the implicit EDX:EAX 64-bit input value

(if the monitoring hardware did not trigger beforehand).

Prior to executing the UMWAIT instruction, an operating system may specify the maximum delay it allows the

processor to suspend its operation. It can do so by writing TSC-quanta value to the following 32bit MSR (IA32_UM-

WAIT_CONTROL at MSR index E1H):

• IA32_UMWAIT_CONTROL[31:2] - Determines the maximum time in TSC-quanta that the processor can reside

in either C0.1 or C0.2. A zero value indicates no maximum time. The maximum time value is a 32-bit value

where the upper 30 bits come from this field and the lower two bits are zero.

• IA32_UMWAIT_CONTROL[1] - Reserved.

• IA32_UMWAIT_CONTROL[0] - C0.2 is not allowed by the OS. Value of “1” means all C0.2 requests revert to

C0.1.

If the processor that executed a UMWAIT instruction wakes due to the expiration of the operating system time-

limit, the instructions sets RFLAGS.CF; otherwise, that flag is cleared.

The UMWAIT instruction causes a transactional abort when used inside a transactional region.

The UMWAIT instruction operates with the UMONITOR instruction. The two instructions allow the definition of an

address at which to wait (UMONITOR) and an implementation-dependent optimized operation to perform while

waiting (UMWAIT). The execution of UMWAIT is a hint to the processor that it can enter an implementation-depen-

dent-optimized state while waiting for an event or a store operation to the address range armed by UMONITOR. The

UMWAIT instruction will not wait (will not enter an implementation-dependent optimized state) if any of the

1. The Mod field of the ModR/M byte must have value 11B.

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INSTRUCTION SET REFERENCE, M-U

following instructions were executed before UMWAIT and after the most recent execution of UMONITOR: IRET,

MONITOR, SYSEXIT, SYSRET, and far RET (the last if it is changing CPL).

The following additional events cause the processor to exit the implementation-dependent optimized state: a store

to the address range armed by the UMONITOR instruction, an NMI or SMI, a debug exception, a machine check

exception, the BINIT# signal, the INIT# signal, and the RESET# signal. Other implementation-dependent events

may also cause the processor to exit the implementation-dependent optimized state.

In addition, an external interrupt causes the processor to exit the implementation-dependent optimized state

regardless of whether maskable-interrupts are inhibited (EFLAGS.IF =0).

Following exit from the implementation-dependent-optimized state, control passes to the instruction after the

UMWAIT instruction. A pending interrupt that is not masked (including an NMI or an SMI) may be delivered before

execution of that instruction.

Unlike the HLT instruction, the UMWAIT instruction does not restart at the UMWAIT instruction following the

handling of an SMI.

If the preceding UMONITOR instruction did not successfully arm an address range or if UMONITOR was not

executed prior to executing UMWAIT and following the most recent execution of the legacy MONITOR instruction

(UMWAIT does not interoperate with MONITOR), then the processor will not enter an optimized state. Execution

will continue to the instruction following UMWAIT.

A store to the address range armed by the UMONITOR instruction will cause the processor to exit UMWAIT if either

the store was originated by other processor agents or the store was originated by a non-processor agent.

Operation

os_deadline := TSC+(IA32_UMWAIT_CONTROL[31:2]<<2)

instr_deadline := UINT64(EDX:EAX)

IF os_deadline < instr_deadline:

deadline := os_deadline

using_os_deadline := 1

ELSE:

deadline := instr_deadline

using_os_deadline := 0

WHILE monitor hardware armed AND TSC < deadline:

implementation_dependent_optimized_state(Source register, deadline, IA32_UMWAIT_CONTROL[0] )

IF using_os_deadline AND TSC ≥ deadline:

RFLAGS.CF := 1

ELSE:

RFLAGS.CF := 0

RFLAGS.AF,PF,SF,ZF,OF := 0

Intel C/C++ Compiler Intrinsic Equivalent

UMWAIT uint8_t _umwait(uint32_t control, uint64_t counter);

Numeric Exceptions

None.

Exceptions (All Operating Modes)

#GP(0)

If src[31:1] != 0.

If CR4.TSD = 1 and CPL != 0.

#UD

If CPUID.7.0:ECX.WAITPKG[bit 5]=0.

UMWAIT-User Level Monitor Wait

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INSTRUCTION SET REFERENCE, M-U

UNPCKHPD-Unpack and Interleave High Packed Double Precision Floating-Point Values

Opcode/

Op /

64/32 bit

CPUID

Description

Instruction

Mode

Feature Flag

Support

66 0F 15 /r

V/V

SSE2

Unpacks and Interleaves double precision floating-point

UNPCKHPD xmm1, xmm2/m128

values from high quadwords of xmm1 and xmm2/m128.

VEX.128.66.0F.WIG 15 /r

V/V

AVX

Unpacks and Interleaves double precision floating-point

VUNPCKHPD xmm1,xmm2,

values from high quadwords of xmm2 and xmm3/m128.

xmm3/m128

VEX.256.66.0F.WIG 15 /r

V/V

AVX

Unpacks and Interleaves double precision floating-point

VUNPCKHPD ymm1,ymm2,

values from high quadwords of ymm2 and ymm3/m256.

ymm3/m256

EVEX.128.66.0F.W1 15 /r

V/V

AVX512VL

Unpacks and Interleaves double precision floating-point

VUNPCKHPD xmm1 {k1}{z}, xmm2,

AVX512F

values from high quadwords of xmm2 and

xmm3/m128/m64bcst

xmm3/m128/m64bcst subject to writemask k1.

EVEX.256.66.0F.W1 15 /r

V/V

AVX512VL

Unpacks and Interleaves double precision floating-point

VUNPCKHPD ymm1 {k1}{z}, ymm2,

AVX512F

values from high quadwords of ymm2 and

ymm3/m256/m64bcst

ymm3/m256/m64bcst subject to writemask k1.

EVEX.512.66.0F.W1 15 /r

V/V

AVX512F

Unpacks and Interleaves double precision floating-point

VUNPCKHPD zmm1 {k1}{z}, zmm2,

values from high quadwords of zmm2 and

zmm3/m512/m64bcst

zmm3/m512/m64bcst subject to writemask k1.

Instruction Operand Encoding

Op/En

Tuple Type

Operand 1

Operand 2

Operand 3

Operand 4

N/A

ModRM:reg (r, w)

ModRM:r/m (r)

N/A

ModRM:reg (w)

VEX.vvvv (r)

ModRM:r/m (r)

N/A

Full

ModRM:reg (w)

EVEX.vvvv (r)

ModRM:r/m (r)

N/A

Description

Performs an interleaved unpack of the high double precision floating-point values from the first source operand and

the second source operand. See Figure 4-15 in the Intel® 64 and IA-32 Architectures Software Developer’s

Manual, Volume 2B.

128-bit Legacy SSE version: The second source can be an XMM register or an 128-bit memory location. The desti-

nation is not distinct from the first source XMM register and the upper bits (MAXVL-1:128) of the corresponding

ZMM register destination are unmodified. When unpacking from a memory operand, an implementation may fetch

only the appropriate 64 bits; however, alignment to 16-byte boundary and normal segment checking will still be

enforced.

VEX.128 encoded version: The first source operand is a XMM register. The second source operand can be a XMM

the corresponding ZMM register destination are zeroed.

VEX.256 encoded version: The first source operand is a YMM register. The second source operand can be a YMM

EVEX.512 encoded version: The first source operand is a ZMM register. The second source operand is a ZMM

tion operand is a ZMM register, conditionally updated using writemask k1.

EVEX.256 encoded version: The first source operand is a YMM register. The second source operand is a YMM

tion operand is a YMM register, conditionally updated using writemask k1.

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INSTRUCTION SET REFERENCE, M-U

EVEX.128 encoded version: The first source operand is a XMM register. The second source operand is a XMM

tion operand is a XMM register, conditionally updated using writemask k1.

Operation

VUNPCKHPD (EVEX Encoded Versions When SRC2 is a Register)

(KL, VL) = (2, 128), (4, 256), (8, 512)

IF VL >= 128

TMP_DEST[63:0] := SRC1[127:64]

TMP_DEST[127:64] := SRC2[127:64]

FI;

IF VL >= 256

TMP_DEST[191:128] := SRC1[255:192]

TMP_DEST[255:192] := SRC2[255:192]

FI;

IF VL >= 512

TMP_DEST[319:256] := SRC1[383:320]

TMP_DEST[383:320] := SRC2[383:320]

TMP_DEST[447:384] := SRC1[511:448]

TMP_DEST[511:448] := SRC2[511:448]

FI;

FOR j := 0 TO KL-1

i := j * 64

IF k1[j] OR *no writemask*

THEN DEST[i+63:i] := TMP_DEST[i+63:i]

ELSE

IF *merging-masking*

; merging-masking

THEN *DEST[i+63:i] remains unchanged*

ELSE *zeroing-masking*

; zeroing-masking

DEST[i+63:i] := 0

FI;

ENDFOR

DEST[MAXVL-1:VL] := 0

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INSTRUCTION SET REFERENCE, M-U

VUNPCKHPD (EVEX Encoded Version When SRC2 is Memory)

(KL, VL) = (2, 128), (4, 256), (8, 512)

FOR j := 0 TO KL-1

i := j * 64

IF (EVEX.b = 1)

THEN TMP_SRC2[i+63:i] := SRC2[63:0]

ELSE TMP_SRC2[i+63:i] := SRC2[i+63:i]

FI;

ENDFOR;

IF VL >= 128

TMP_DEST[63:0] := SRC1[127:64]

TMP_DEST[127:64] := TMP_SRC2[127:64]

FI;

IF VL >= 256

TMP_DEST[191:128] := SRC1[255:192]

TMP_DEST[255:192] := TMP_SRC2[255:192]

FI;

IF VL >= 512

TMP_DEST[319:256] := SRC1[383:320]

TMP_DEST[383:320] := TMP_SRC2[383:320]

TMP_DEST[447:384] := SRC1[511:448]

TMP_DEST[511:448] := TMP_SRC2[511:448]

FI;

FOR j := 0 TO KL-1

i := j * 64

IF k1[j] OR *no writemask*

THEN DEST[i+63:i] := TMP_DEST[i+63:i]

ELSE

IF *merging-masking*

; merging-masking

THEN *DEST[i+63:i] remains unchanged*

ELSE *zeroing-masking*

; zeroing-masking

DEST[i+63:i] := 0

FI;

ENDFOR

DEST[MAXVL-1:VL] := 0

VUNPCKHPD (VEX.256 Encoded Version)

DEST[63:0] := SRC1[127:64]

DEST[127:64] := SRC2[127:64]

DEST[191:128] := SRC1[255:192]

DEST[255:192] := SRC2[255:192]

DEST[MAXVL-1:256] := 0

VUNPCKHPD (VEX.128 Encoded Version)

DEST[63:0] := SRC1[127:64]

DEST[127:64] := SRC2[127:64]

DEST[MAXVL-1:128] := 0

UNPCKHPD (128-bit Legacy SSE Version)

DEST[63:0] := SRC1[127:64]

DEST[127:64] := SRC2[127:64]

DEST[MAXVL-1:128] (Unmodified)

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INSTRUCTION SET REFERENCE, M-U

Intel C/C++ Compiler Intrinsic Equivalent

VUNPCKHPD __m512d _mm512_unpackhi_pd( __m512d a, __m512d b);

VUNPCKHPD __m512d _mm512_mask_unpackhi_pd(__m512d s, __mmask8 k, __m512d a, __m512d b);

VUNPCKHPD __m512d _mm512_maskz_unpackhi_pd(__mmask8 k, __m512d a, __m512d b);

VUNPCKHPD __m256d _mm256_unpackhi_pd(__m256d a, __m256d b)

VUNPCKHPD __m256d _mm256_mask_unpackhi_pd(__m256d s, __mmask8 k, __m256d a, __m256d b);

VUNPCKHPD __m256d _mm256_maskz_unpackhi_pd(__mmask8 k, __m256d a, __m256d b);

UNPCKHPD __m128d _mm_unpackhi_pd(__m128d a, __m128d b)

VUNPCKHPD __m128d _mm_mask_unpackhi_pd(__m128d s, __mmask8 k, __m128d a, __m128d b);

VUNPCKHPD __m128d _mm_maskz_unpackhi_pd(__mmask8 k, __m128d a, __m128d b);

SIMD Floating-Point Exceptions

None.

Other Exceptions

Non-EVEX-encoded instructions, see Table 2-21, “Type 4 Class Exception Conditions.”

EVEX-encoded instructions, see Table 2-50, “Type E4NF Class Exception Conditions.”

UNPCKHPD-Unpack and Interleave High Packed Double Precision Floating-Point Values

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INSTRUCTION SET REFERENCE, M-U

UNPCKHPS-Unpack and Interleave High Packed Single Precision Floating-Point Values

Opcode/

Op /

64/32 bit

CPUID

Description

Instruction

Mode

Feature

Support

Flag

NP 0F 15 /r

V/V

SSE

Unpacks and Interleaves single precision floating-point

UNPCKHPS xmm1, xmm2/m128

values from high quadwords of xmm1 and xmm2/m128.

VEX.128.0F.WIG 15 /r

V/V

AVX

Unpacks and Interleaves single precision floating-point

VUNPCKHPS xmm1, xmm2,

values from high quadwords of xmm2 and xmm3/m128.

xmm3/m128

VEX.256.0F.WIG 15 /r

V/V

AVX

Unpacks and Interleaves single precision floating-point

VUNPCKHPS ymm1, ymm2,

values from high quadwords of ymm2 and ymm3/m256.

ymm3/m256

EVEX.128.0F.W0 15 /r

V/V

AVX512VL

Unpacks and Interleaves single precision floating-point

VUNPCKHPS xmm1 {k1}{z}, xmm2,

AVX512F

values from high quadwords of xmm2 and

xmm3/m128/m32bcst

xmm3/m128/m32bcst and write result to xmm1 subject to

writemask k1.

EVEX.256.0F.W0 15 /r

V/V

AVX512VL

Unpacks and Interleaves single precision floating-point

VUNPCKHPS ymm1 {k1}{z}, ymm2,

AVX512F

values from high quadwords of ymm2 and

ymm3/m256/m32bcst

ymm3/m256/m32bcst and write result to ymm1 subject to

writemask k1.

EVEX.512.0F.W0 15 /r

V/V

AVX512F

Unpacks and Interleaves single precision floating-point

VUNPCKHPS zmm1 {k1}{z}, zmm2,

values from high quadwords of zmm2 and

zmm3/m512/m32bcst

zmm3/m512/m32bcst and write result to zmm1 subject to

writemask k1.

Instruction Operand Encoding

Op/En

Tuple Type

Operand 1

Operand 2

Operand 3

Operand 4

N/A

ModRM:reg (r, w)

ModRM:r/m (r)

N/A

ModRM:reg (w)

VEX.vvvv (r)

ModRM:r/m (r)

N/A

Full

ModRM:reg (w)

EVEX.vvvv (r)

ModRM:r/m (r)

N/A

Description

Performs an interleaved unpack of the high single precision floating-point values from the first source operand and

the second source operand.

128-bit Legacy SSE version: The second source can be an XMM register or an 128-bit memory location. The desti-

nation is not distinct from the first source XMM register and the upper bits (MAXVL-1:128) of the corresponding

ZMM register destination are unmodified. When unpacking from a memory operand, an implementation may fetch

only the appropriate 64 bits; however, alignment to 16-byte boundary and normal segment checking will still be

enforced.

VEX.128 encoded version: The first source operand is a XMM register. The second source operand can be a XMM

the corresponding ZMM register destination are zeroed.

VEX.256 encoded version: The second source operand is an YMM register or an 256-bit memory location. The first

source operand and destination operands are YMM registers.

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INSTRUCTION SET REFERENCE, M-U

SRC1

SRC2

DEST

Figure 4-27. VUNPCKHPS Operation

EVEX.512 encoded version: The first source operand is a ZMM register. The second source operand is a ZMM

tion operand is a ZMM register, conditionally updated using writemask k1.

EVEX.256 encoded version: The first source operand is a YMM register. The second source operand is a YMM

tion operand is a YMM register, conditionally updated using writemask k1.

EVEX.128 encoded version: The first source operand is a XMM register. The second source operand is a XMM

tion operand is a XMM register, conditionally updated using writemask k1.

Operation

VUNPCKHPS (EVEX Encoded Version When SRC2 is a Register)

(KL, VL) = (4, 128), (8, 256), (16, 512)

IF VL >= 128

TMP_DEST[31:0] := SRC1[95:64]

TMP_DEST[63:32] := SRC2[95:64]

TMP_DEST[95:64] := SRC1[127:96]

TMP_DEST[127:96] := SRC2[127:96]

FI;

IF VL >= 256

TMP_DEST[159:128] := SRC1[223:192]

TMP_DEST[191:160] := SRC2[223:192]

TMP_DEST[223:192] := SRC1[255:224]

TMP_DEST[255:224] := SRC2[255:224]

FI;

IF VL >= 512

TMP_DEST[287:256] := SRC1[351:320]

TMP_DEST[319:288] := SRC2[351:320]

TMP_DEST[351:320] := SRC1[383:352]

TMP_DEST[383:352] := SRC2[383:352]

TMP_DEST[415:384] := SRC1[479:448]

TMP_DEST[447:416] := SRC2[479:448]

TMP_DEST[479:448] := SRC1[511:480]

TMP_DEST[511:480] := SRC2[511:480]

FI;

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INSTRUCTION SET REFERENCE, M-U

FOR j := 0 TO KL-1

i := j * 32

IF k1[j] OR *no writemask*

THEN DEST[i+31:i] := TMP_DEST[i+31:i]

ELSE

IF *merging-masking*

; merging-masking

THEN *DEST[i+31:i] remains unchanged*

ELSE *zeroing-masking*

; zeroing-masking

DEST[i+31:i] := 0

FI;

ENDFOR

DEST[MAXVL-1:VL] := 0

VUNPCKHPS (EVEX Encoded Version When SRC2 is Memory)

(KL, VL) = (4, 128), (8, 256), (16, 512)

FOR j := 0 TO KL-1

i := j * 32

IF (EVEX.b = 1)

THEN TMP_SRC2[i+31:i] := SRC2[31:0]

ELSE TMP_SRC2[i+31:i] := SRC2[i+31:i]

FI;

ENDFOR;

IF VL >= 128

TMP_DEST[31:0] := SRC1[95:64]

TMP_DEST[63:32] := TMP_SRC2[95:64]

TMP_DEST[95:64] := SRC1[127:96]

TMP_DEST[127:96] := TMP_SRC2[127:96]

FI;

IF VL >= 256

TMP_DEST[159:128] := SRC1[223:192]

TMP_DEST[191:160] := TMP_SRC2[223:192]

TMP_DEST[223:192] := SRC1[255:224]

TMP_DEST[255:224] := TMP_SRC2[255:224]

FI;

IF VL >= 512

TMP_DEST[287:256] := SRC1[351:320]

TMP_DEST[319:288] := TMP_SRC2[351:320]

TMP_DEST[351:320] := SRC1[383:352]

TMP_DEST[383:352] := TMP_SRC2[383:352]

TMP_DEST[415:384] := SRC1[479:448]

TMP_DEST[447:416] := TMP_SRC2[479:448]

TMP_DEST[479:448] := SRC1[511:480]

TMP_DEST[511:480] := TMP_SRC2[511:480]

FI;

FOR j := 0 TO KL-1

i := j * 32

IF k1[j] OR *no writemask*

THEN DEST[i+31:i] := TMP_DEST[i+31:i]

ELSE

IF *merging-masking*

; merging-masking

THEN *DEST[i+31:i] remains unchanged*

ELSE *zeroing-masking*

; zeroing-masking

DEST[i+31:i] := 0

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INSTRUCTION SET REFERENCE, M-U

FI;

ENDFOR

DEST[MAXVL-1:VL] := 0

VUNPCKHPS (VEX.256 Encoded Version)

DEST[31:0] := SRC1[95:64]

DEST[63:32] := SRC2[95:64]

DEST[95:64] := SRC1[127:96]

DEST[127:96] := SRC2[127:96]

DEST[159:128] := SRC1[223:192]

DEST[191:160] := SRC2[223:192]

DEST[223:192] := SRC1[255:224]

DEST[255:224] := SRC2[255:224]

DEST[MAXVL-1:256] := 0

VUNPCKHPS (VEX.128 Encoded Version)

DEST[31:0] := SRC1[95:64]

DEST[63:32] := SRC2[95:64]

DEST[95:64] := SRC1[127:96]

DEST[127:96] := SRC2[127:96]

DEST[MAXVL-1:128] := 0

UNPCKHPS (128-bit Legacy SSE Version)

DEST[31:0] := SRC1[95:64]

DEST[63:32] := SRC2[95:64]

DEST[95:64] := SRC1[127:96]

DEST[127:96] := SRC2[127:96]

DEST[MAXVL-1:128] (Unmodified)

Intel C/C++ Compiler Intrinsic Equivalent

VUNPCKHPS __m512 _mm512_unpackhi_ps( __m512 a, __m512 b);

VUNPCKHPS __m512 _mm512_mask_unpackhi_ps(__m512 s, __mmask16 k, __m512 a, __m512 b);

VUNPCKHPS __m512 _mm512_maskz_unpackhi_ps(__mmask16 k, __m512 a, __m512 b);

VUNPCKHPS __m256 _mm256_unpackhi_ps (__m256 a, __m256 b);

VUNPCKHPS __m256 _mm256_mask_unpackhi_ps(__m256 s, __mmask8 k, __m256 a, __m256 b);

VUNPCKHPS __m256 _mm256_maskz_unpackhi_ps(__mmask8 k, __m256 a, __m256 b);

UNPCKHPS __m128 _mm_unpackhi_ps (__m128 a, __m128 b);

VUNPCKHPS __m128 _mm_mask_unpackhi_ps(__m128 s, __mmask8 k, __m128 a, __m128 b);

VUNPCKHPS __m128 _mm_maskz_unpackhi_ps(__mmask8 k, __m128 a, __m128 b);

SIMD Floating-Point Exceptions

None.

Other Exceptions

Non-EVEX-encoded instructions, see Table 2-21, “Type 4 Class Exception Conditions.”

EVEX-encoded instructions, see Table 2-50, “Type E4NF Class Exception Conditions.”

UNPCKHPS-Unpack and Interleave High Packed Single Precision Floating-Point Values

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4-733

INSTRUCTION SET REFERENCE, M-U

UNPCKLPD-Unpack and Interleave Low Packed Double Precision Floating-Point Values

Opcode/

Op /

64/32 bit

CPUID

Description

Instruction

Mode

Feature Flag

Support

66 0F 14 /r

V/V

SSE2

Unpacks and Interleaves double precision floating-point

UNPCKLPD xmm1, xmm2/m128

values from low quadwords of xmm1 and xmm2/m128.

VEX.128.66.0F.WIG 14 /r

V/V

AVX

Unpacks and Interleaves double precision floating-point

VUNPCKLPD xmm1,xmm2,

values from low quadwords of xmm2 and xmm3/m128.

xmm3/m128

VEX.256.66.0F.WIG 14 /r

V/V

AVX

Unpacks and Interleaves double precision floating-point

VUNPCKLPD ymm1,ymm2,

values from low quadwords of ymm2 and ymm3/m256.

ymm3/m256

EVEX.128.66.0F.W1 14 /r

V/V

AVX512VL

Unpacks and Interleaves double precision floating-point

VUNPCKLPD xmm1 {k1}{z}, xmm2,

AVX512F

values from low quadwords of xmm2 and

xmm3/m128/m64bcst

xmm3/m128/m64bcst subject to write mask k1.

EVEX.256.66.0F.W1 14 /r

V/V

AVX512VL

Unpacks and Interleaves double precision floating-point

VUNPCKLPD ymm1 {k1}{z}, ymm2,

AVX512F

values from low quadwords of ymm2 and

ymm3/m256/m64bcst

ymm3/m256/m64bcst subject to write mask k1.

EVEX.512.66.0F.W1 14 /r

V/V

AVX512F

Unpacks and Interleaves double precision floating-point

VUNPCKLPD zmm1 {k1}{z}, zmm2,

values from low quadwords of zmm2 and

zmm3/m512/m64bcst

zmm3/m512/m64bcst subject to write mask k1.

Instruction Operand Encoding

Op/En

Tuple Type

Operand 1

Operand 2

Operand 3

Operand 4

N/A

ModRM:reg (r, w)

ModRM:r/m (r)

N/A

ModRM:reg (w)

VEX.vvvv (r)

ModRM:r/m (r)

N/A

Full

ModRM:reg (w)

EVEX.vvvv (r)

ModRM:r/m (r)

N/A

Description

Performs an interleaved unpack of the low double precision floating-point values from the first source operand and

the second source operand.

128-bit Legacy SSE version: The second source can be an XMM register or an 128-bit memory location. The desti-

nation is not distinct from the first source XMM register and the upper bits (MAXVL-1:128) of the corresponding

ZMM register destination are unmodified. When unpacking from a memory operand, an implementation may fetch

only the appropriate 64 bits; however, alignment to 16-byte boundary and normal segment checking will still be

enforced.

VEX.128 encoded version: The first source operand is a XMM register. The second source operand can be a XMM

the corresponding ZMM register destination are zeroed.

VEX.256 encoded version: The first source operand is a YMM register. The second source operand can be a YMM

EVEX.512 encoded version: The first source operand is a ZMM register. The second source operand is a ZMM

tion operand is a ZMM register, conditionally updated using writemask k1.

EVEX.256 encoded version: The first source operand is a YMM register. The second source operand is a YMM

tion operand is a YMM register, conditionally updated using writemask k1.

EVEX.128 encoded version: The first source operand is an XMM register. The second source operand is a XMM

tion operand is a XMM register, conditionally updated using writemask k1.

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INSTRUCTION SET REFERENCE, M-U

Operation

VUNPCKLPD (EVEX Encoded Versions When SRC2 is a Register)

(KL, VL) = (2, 128), (4, 256), (8, 512)

IF VL >= 128

TMP_DEST[63:0] := SRC1[63:0]

TMP_DEST[127:64] := SRC2[63:0]

FI;

IF VL >= 256

TMP_DEST[191:128] := SRC1[191:128]

TMP_DEST[255:192] := SRC2[191:128]

FI;

IF VL >= 512

TMP_DEST[319:256] := SRC1[319:256]

TMP_DEST[383:320] := SRC2[319:256]

TMP_DEST[447:384] := SRC1[447:384]

TMP_DEST[511:448] := SRC2[447:384]

FI;

FOR j := 0 TO KL-1

i := j * 64

IF k1[j] OR *no writemask*

THEN DEST[i+63:i] := TMP_DEST[i+63:i]

ELSE

IF *merging-masking*

; merging-masking

THEN *DEST[i+63:i] remains unchanged*

ELSE *zeroing-masking*

; zeroing-masking

DEST[i+63:i] := 0

FI;

ENDFOR

DEST[MAXVL-1:VL] := 0

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Vol. 2B

4-735

INSTRUCTION SET REFERENCE, M-U

VUNPCKLPD (EVEX Encoded Version When SRC2 is Memory)

(KL, VL) = (2, 128), (4, 256), (8, 512)

FOR j := 0 TO KL-1

i := j * 64

IF (EVEX.b = 1)

THEN TMP_SRC2[i+63:i] := SRC2[63:0]

ELSE TMP_SRC2[i+63:i] := SRC2[i+63:i]

FI;

ENDFOR;

IF VL >= 128

TMP_DEST[63:0] := SRC1[63:0]

TMP_DEST[127:64] := TMP_SRC2[63:0]

FI;

IF VL >= 256

TMP_DEST[191:128] := SRC1[191:128]

TMP_DEST[255:192] := TMP_SRC2[191:128]

FI;

IF VL >= 512

TMP_DEST[319:256] := SRC1[319:256]

TMP_DEST[383:320] := TMP_SRC2[319:256]

TMP_DEST[447:384] := SRC1[447:384]

TMP_DEST[511:448] := TMP_SRC2[447:384]

FI;

FOR j := 0 TO KL-1

i := j * 64

IF k1[j] OR *no writemask*

THEN DEST[i+63:i] := TMP_DEST[i+63:i]

ELSE

IF *merging-masking*

; merging-masking

THEN *DEST[i+63:i] remains unchanged*

ELSE *zeroing-masking*

; zeroing-masking

DEST[i+63:i] := 0

FI;

ENDFOR

DEST[MAXVL-1:VL] := 0

VUNPCKLPD (VEX.256 Encoded Version)

DEST[63:0] := SRC1[63:0]

DEST[127:64] := SRC2[63:0]

DEST[191:128] := SRC1[191:128]

DEST[255:192] := SRC2[191:128]

DEST[MAXVL-1:256] := 0

VUNPCKLPD (VEX.128 Encoded Version)

DEST[63:0] := SRC1[63:0]

DEST[127:64] := SRC2[63:0]

DEST[MAXVL-1:128] := 0

UNPCKLPD (128-bit Legacy SSE Version)

DEST[63:0] := SRC1[63:0]

DEST[127:64] := SRC2[63:0]

DEST[MAXVL-1:128] (Unmodified)

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INSTRUCTION SET REFERENCE, M-U

Intel C/C++ Compiler Intrinsic Equivalent

VUNPCKLPD __m512d _mm512_unpacklo_pd( __m512d a, __m512d b);

VUNPCKLPD __m512d _mm512_mask_unpacklo_pd(__m512d s, __mmask8 k, __m512d a, __m512d b);

VUNPCKLPD __m512d _mm512_maskz_unpacklo_pd(__mmask8 k, __m512d a, __m512d b);

VUNPCKLPD __m256d _mm256_unpacklo_pd(__m256d a, __m256d b)

VUNPCKLPD __m256d _mm256_mask_unpacklo_pd(__m256d s, __mmask8 k, __m256d a, __m256d b);

VUNPCKLPD __m256d _mm256_maskz_unpacklo_pd(__mmask8 k, __m256d a, __m256d b);

UNPCKLPD __m128d _mm_unpacklo_pd(__m128d a, __m128d b)

VUNPCKLPD __m128d _mm_mask_unpacklo_pd(__m128d s, __mmask8 k, __m128d a, __m128d b);

VUNPCKLPD __m128d _mm_maskz_unpacklo_pd(__mmask8 k, __m128d a, __m128d b);

SIMD Floating-Point Exceptions

None.

Other Exceptions

Non-EVEX-encoded instructions, see Table 2-21, “Type 4 Class Exception Conditions.”

EVEX-encoded instructions, see Table 2-50, “Type E4NF Class Exception Conditions.”

UNPCKLPD-Unpack and Interleave Low Packed Double Precision Floating-Point Values

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INSTRUCTION SET REFERENCE, M-U

UNPCKLPS-Unpack and Interleave Low Packed Single Precision Floating-Point Values

Opcode/

Op /

64/32 bit

CPUID

Description

Instruction

Mode

Feature Flag

Support

NP 0F 14 /r

V/V

SSE

Unpacks and Interleaves single precision floating-point

UNPCKLPS xmm1, xmm2/m128

values from low quadwords of xmm1 and xmm2/m128.

VEX.128.0F.WIG 14 /r

V/V

AVX

Unpacks and Interleaves single precision floating-point

VUNPCKLPS xmm1,xmm2,

values from low quadwords of xmm2 and xmm3/m128.

xmm3/m128

VEX.256.0F.WIG 14 /r

V/V

AVX

Unpacks and Interleaves single precision floating-point

VUNPCKLPS

values from low quadwords of ymm2 and ymm3/m256.

ymm1,ymm2,ymm3/m256

EVEX.128.0F.W0 14 /r

V/V

AVX512VL

Unpacks and Interleaves single precision floating-point

VUNPCKLPS xmm1 {k1}{z}, xmm2,

AVX512F

values from low quadwords of xmm2 and xmm3/mem and

xmm3/m128/m32bcst

write result to xmm1 subject to write mask k1.

EVEX.256.0F.W0 14 /r

V/V

AVX512VL

Unpacks and Interleaves single precision floating-point

VUNPCKLPS ymm1 {k1}{z}, ymm2,

AVX512F

values from low quadwords of ymm2 and ymm3/mem and

ymm3/m256/m32bcst

write result to ymm1 subject to write mask k1.

EVEX.512.0F.W0 14 /r

V/V

AVX512F

Unpacks and Interleaves single precision floating-point

VUNPCKLPS zmm1 {k1}{z}, zmm2,

values from low quadwords of zmm2 and

zmm3/m512/m32bcst

zmm3/m512/m32bcst and write result to zmm1 subject to

write mask k1.

Instruction Operand Encoding

Op/En

Tuple Type

Operand 1

Operand 2

Operand 3

Operand 4

N/A

ModRM:reg (r, w)

ModRM:r/m (r)

N/A

ModRM:reg (w)

VEX.vvvv (r)

ModRM:r/m (r)

N/A

Full

ModRM:reg (w)

EVEX.vvvv (r)

ModRM:r/m (r)

N/A

Description

Performs an interleaved unpack of the low single precision floating-point values from the first source operand and

the second source operand.

128-bit Legacy SSE version: The second source can be an XMM register or an 128-bit memory location. The desti-

nation is not distinct from the first source XMM register and the upper bits (MAXVL-1:128) of the corresponding

ZMM register destination are unmodified. When unpacking from a memory operand, an implementation may fetch

only the appropriate 64 bits; however, alignment to 16-byte boundary and normal segment checking will still be

enforced.

VEX.128 encoded version: The first source operand is a XMM register. The second source operand can be a XMM

the corresponding ZMM register destination are zeroed.

VEX.256 encoded version: The first source operand is a YMM register. The second source operand can be a YMM

4-738

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INSTRUCTION SET REFERENCE, M-U

SRC1

SRC2

DEST

Figure 4-28. VUNPCKLPS Operation

EVEX.512 encoded version: The first source operand is a ZMM register. The second source operand is a ZMM

tion operand is a ZMM register, conditionally updated using writemask k1.

EVEX.256 encoded version: The first source operand is a YMM register. The second source operand is a YMM

tion operand is a YMM register, conditionally updated using writemask k1.

EVEX.128 encoded version: The first source operand is an XMM register. The second source operand is a XMM

tion operand is a XMM register, conditionally updated using writemask k1.

Operation

VUNPCKLPS (EVEX Encoded Version When SRC2 is a ZMM Register)

(KL, VL) = (4, 128), (8, 256), (16, 512)

IF VL >= 128

TMP_DEST[31:0] := SRC1[31:0]

TMP_DEST[63:32] := SRC2[31:0]

TMP_DEST[95:64] := SRC1[63:32]

TMP_DEST[127:96] := SRC2[63:32]

FI;

IF VL >= 256

TMP_DEST[159:128] := SRC1[159:128]

TMP_DEST[191:160] := SRC2[159:128]

TMP_DEST[223:192] := SRC1[191:160]

TMP_DEST[255:224] := SRC2[191:160]

FI;

IF VL >= 512

TMP_DEST[287:256] := SRC1[287:256]

TMP_DEST[319:288] := SRC2[287:256]

TMP_DEST[351:320] := SRC1[319:288]

TMP_DEST[383:352] := SRC2[319:288]

TMP_DEST[415:384] := SRC1[415:384]

TMP_DEST[447:416] := SRC2[415:384]

TMP_DEST[479:448] := SRC1[447:416]

TMP_DEST[511:480] := SRC2[447:416]

FI;

FOR j := 0 TO KL-1

UNPCKLPS-Unpack and Interleave Low Packed Single Precision Floating-Point Values

Vol. 2B

4-739

INSTRUCTION SET REFERENCE, M-U

i := j * 32

IF k1[j] OR *no writemask*

THEN DEST[i+31:i] := TMP_DEST[i+31:i]

ELSE

IF *merging-masking*

; merging-masking

THEN *DEST[i+31:i] remains unchanged*

ELSE *zeroing-masking*

; zeroing-masking

DEST[i+31:i] := 0

FI;

ENDFOR

DEST[MAXVL-1:VL] := 0

VUNPCKLPS (EVEX Encoded Version When SRC2 is Memory)

(KL, VL) = (4, 128), (8, 256), (16, 512)

FOR j := 0 TO KL-1

i := j * 31

IF (EVEX.b = 1)

THEN TMP_SRC2[i+31:i] := SRC2[31:0]

ELSE TMP_SRC2[i+31:i] := SRC2[i+31:i]

FI;

ENDFOR;

IF VL >= 128

TMP_DEST[31:0] := SRC1[31:0]

TMP_DEST[63:32] := TMP_SRC2[31:0]

TMP_DEST[95:64] := SRC1[63:32]

TMP_DEST[127:96] := TMP_SRC2[63:32]

FI;

IF VL >= 256

TMP_DEST[159:128] := SRC1[159:128]

TMP_DEST[191:160] := TMP_SRC2[159:128]

TMP_DEST[223:192] := SRC1[191:160]

TMP_DEST[255:224] := TMP_SRC2[191:160]

FI;

IF VL >= 512

TMP_DEST[287:256] := SRC1[287:256]

TMP_DEST[319:288] := TMP_SRC2[287:256]

TMP_DEST[351:320] := SRC1[319:288]

TMP_DEST[383:352] := TMP_SRC2[319:288]

TMP_DEST[415:384] := SRC1[415:384]

TMP_DEST[447:416] := TMP_SRC2[415:384]

TMP_DEST[479:448] := SRC1[447:416]

TMP_DEST[511:480] := TMP_SRC2[447:416]

FI;

FOR j := 0 TO KL-1

i := j * 32

IF k1[j] OR *no writemask*

THEN DEST[i+31:i] := TMP_DEST[i+31:i]

ELSE

IF *merging-masking*

; merging-masking

THEN *DEST[i+31:i] remains unchanged*

ELSE *zeroing-masking*

; zeroing-masking

DEST[i+31:i] := 0

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INSTRUCTION SET REFERENCE, M-U

FI;

ENDFOR

DEST[MAXVL-1:VL] := 0

UNPCKLPS (VEX.256 Encoded Version)

DEST[31:0] := SRC1[31:0]

DEST[63:32] := SRC2[31:0]

DEST[95:64] := SRC1[63:32]

DEST[127:96] := SRC2[63:32]

DEST[159:128] := SRC1[159:128]

DEST[191:160] := SRC2[159:128]

DEST[223:192] := SRC1[191:160]

DEST[255:224] := SRC2[191:160]

DEST[MAXVL-1:256] := 0

VUNPCKLPS (VEX.128 Encoded Version)

DEST[31:0] := SRC1[31:0]

DEST[63:32] := SRC2[31:0]

DEST[95:64] := SRC1[63:32]

DEST[127:96] := SRC2[63:32]

DEST[MAXVL-1:128] := 0

UNPCKLPS (128-bit Legacy SSE Version)

DEST[31:0] := SRC1[31:0]

DEST[63:32] := SRC2[31:0]

DEST[95:64] := SRC1[63:32]

DEST[127:96] := SRC2[63:32]

DEST[MAXVL-1:128] (Unmodified)

Intel C/C++ Compiler Intrinsic Equivalent

VUNPCKLPS __m512 _mm512_unpacklo_ps(__m512 a, __m512 b);

VUNPCKLPS __m512 _mm512_mask_unpacklo_ps(__m512 s, __mmask16 k, __m512 a, __m512 b);

VUNPCKLPS __m512 _mm512_maskz_unpacklo_ps(__mmask16 k, __m512 a, __m512 b);

VUNPCKLPS __m256 _mm256_unpacklo_ps (__m256 a, __m256 b);

VUNPCKLPS __m256 _mm256_mask_unpacklo_ps(__m256 s, __mmask8 k, __m256 a, __m256 b);

VUNPCKLPS __m256 _mm256_maskz_unpacklo_ps(__mmask8 k, __m256 a, __m256 b);

UNPCKLPS __m128 _mm_unpacklo_ps (__m128 a, __m128 b);

VUNPCKLPS __m128 _mm_mask_unpacklo_ps(__m128 s, __mmask8 k, __m128 a, __m128 b);

VUNPCKLPS __m128 _mm_maskz_unpacklo_ps(__mmask8 k, __m128 a, __m128 b);

SIMD Floating-Point Exceptions

None.

Other Exceptions

Non-EVEX-encoded instructions, see Table 2-21, “Type 4 Class Exception Conditions.”

EVEX-encoded instructions, see Table 2-50, “Type E4NF Class Exception Conditions.”

UNPCKLPS-Unpack and Interleave Low Packed Single Precision Floating-Point Values

Vol. 2B

4-741

Intel 64 and IA-32 Architectures. Software Developer’s Manual (Collection, 2023) - page 40