Intel 64 and IA-32 Architectures. Software Developer’s Manual (Collection, 2023)

INSTRUCTION SET REFERENCE, M-U

description of the REP prefix. This instruction is only useful for accessing I/O ports located in the processor’s I/O

address space. See Chapter 19, “Input/Output,” in the Intel^® 64 and IA-32 Architectures Software Developer’s

Manual, Volume 1, for more information on accessing I/O ports in the I/O address space.

In 64-bit mode, the default operand size is 32 bits; operand size is not promoted by the use of REX.W. In 64-bit

mode, the default address size is 64 bits, and 64-bit address is specified using RSI by default. 32-bit address using

ESI is support using the prefix 67H, but 16-bit address is not supported in 64-bit mode.

IA-32 Architecture Compatibility

After executing an OUTS, OUTSB, OUTSW, or OUTSD instruction, the Pentium processor ensures that the EWBE#

pin has been sampled active before it begins to execute the next instruction. (Note that the instruction can be

prefetched if EWBE# is not active, but it will not be executed until the EWBE# pin is sampled active.) Only the

Pentium processor family has the EWBE# pin.

For the Pentium 4, Intel^® Xeon^®, and P6 processor family, upon execution of an OUTS, OUTSB, OUTSW, or OUTSD

instruction, the processor will not execute the next instruction until the data phase of the transaction is complete.

Operation

IF ((PE = 1) and ((CPL > IOPL) or (VM = 1)))

THEN (* Protected mode with CPL > IOPL or virtual-8086 mode *)

IF (Any I/O Permission Bit for I/O port being accessed = 1)

THEN (* I/O operation is not allowed *)

#GP(0);

ELSE (* I/O operation is allowed *)

DEST := SRC; (* Writes to I/O port *)

FI;

ELSE (Real Mode or Protected Mode or 64-Bit Mode with CPL ≤ IOPL *)

DEST := SRC; (* Writes to I/O port *)

FI;

Byte transfer:

IF 64-bit mode

Then

IF 64-Bit Address Size

THEN

IF DF = 0

THEN RSI := RSI RSI + 1;

ELSE RSI := RSI or - 1;

FI;

ELSE (* 32-Bit Address Size *)

IF DF = 0

THEN ESI := ESI + 1;

ELSE

ESI := ESI - 1;

FI;

ELSE

IF DF = 0

THEN (E)SI := (E)SI + 1;

ELSE (E)SI := (E)SI - 1;

FI;

Word transfer:

IF 64-bit mode

Then

IF 64-Bit Address Size

OUTS/OUTSB/OUTSW/OUTSD-Output String to Port

Vol. 2B

4-179

INSTRUCTION SET REFERENCE, M-U

THEN

IF DF = 0

THEN RSI := RSI RSI + 2;

ELSE RSI := RSI or - 2;

FI;

ELSE (* 32-Bit Address Size *)

IF DF = 0

THEN ESI := ESI + 2;

ELSE

ESI := ESI - 2;

FI;

ELSE

IF DF = 0

THEN (E)SI := (E)SI + 2;

ELSE (E)SI := (E)SI - 2;

FI;

Doubleword transfer:

IF 64-bit mode

Then

IF 64-Bit Address Size

THEN

IF DF = 0

THEN RSI := RSI RSI + 4;

ELSE RSI := RSI or - 4;

FI;

ELSE (* 32-Bit Address Size *)

IF DF = 0

THEN ESI := ESI + 4;

ELSE

ESI := ESI - 4;

FI;

ELSE

IF DF = 0

THEN (E)SI := (E)SI + 4;

ELSE (E)SI := (E)SI - 4;

FI;

Flags Affected

None.

Protected Mode Exceptions

#GP(0)

If the CPL is greater than (has less privilege) the I/O privilege level (IOPL) and any of the

corresponding I/O permission bits in TSS for the I/O port being accessed is 1.

If a memory operand effective address is outside the limit of the CS, DS, ES, FS, or GS

segment.

If the segment register contains a NULL segment selector.

#PF(fault-code)

If a page fault occurs.

#AC(0)

If alignment checking is enabled and an unaligned memory reference is made while the

current privilege level is 3.

#UD

If the LOCK prefix is used.

4-180

Vol. 2B

OUTS/OUTSB/OUTSW/OUTSD-Output String to Port

INSTRUCTION SET REFERENCE, M-U

Real-Address Mode Exceptions

#GP

If a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit.

#SS

If a memory operand effective address is outside the SS segment limit.

#UD

If the LOCK prefix is used.

Virtual-8086 Mode Exceptions

#GP(0)

If any of the I/O permission bits in the TSS for the I/O port being accessed is 1.

#PF(fault-code)

If a page fault occurs.

#AC(0)

If alignment checking is enabled and an unaligned memory reference is made.

#UD

If the LOCK prefix is used.

Compatibility Mode Exceptions

Same as for protected mode exceptions.

64-Bit Mode Exceptions

#SS(0)

If a memory address referencing the SS segment is in a non-canonical form.

#GP(0)

If the CPL is greater than (has less privilege) the I/O privilege level (IOPL) and any of the

corresponding I/O permission bits in TSS for the I/O port being accessed is 1.

If the memory address is in a non-canonical form.

#PF(fault-code)

If a page fault occurs.

#AC(0)

If alignment checking is enabled and an unaligned memory reference is made while the

current privilege level is 3.

#UD

If the LOCK prefix is used.

OUTS/OUTSB/OUTSW/OUTSD-Output String to Port

Vol. 2B

4-181

INSTRUCTION SET REFERENCE, M-U

PABSB/PABSW/PABSD/PABSQ-Packed Absolute Value

Opcode/

Op/

64/32 bit

CPUID

Description

Instruction

Mode

Feature

Support

Flag

NP 0F 38 1C /r¹

V/V

SSSE3

Compute the absolute value of bytes in mm2/m64

and store UNSIGNED result in mm1.

PABSB mm1, mm2/m64

66 0F 38 1C /r

V/V

SSSE3

Compute the absolute value of bytes in

xmm2/m128 and store UNSIGNED result in xmm1.

PABSB xmm1, xmm2/m128

NP 0F 38 1D /r¹

V/V

SSSE3

Compute the absolute value of 16-bit integers in

mm2/m64 and store UNSIGNED result in mm1.

PABSW mm1, mm2/m64

66 0F 38 1D /r

V/V

SSSE3

Compute the absolute value of 16-bit integers in

xmm2/m128 and store UNSIGNED result in xmm1.

PABSW xmm1, xmm2/m128

NP 0F 38 1E /r¹

V/V

SSSE3

Compute the absolute value of 32-bit integers in

mm2/m64 and store UNSIGNED result in mm1.

PABSD mm1, mm2/m64

66 0F 38 1E /r

V/V

SSSE3

Compute the absolute value of 32-bit integers in

xmm2/m128 and store UNSIGNED result in xmm1.

PABSD xmm1, xmm2/m128

VEX.128.66.0F38.WIG 1C /r

V/V

AVX

Compute the absolute value of bytes in

xmm2/m128 and store UNSIGNED result in xmm1.

VPABSB xmm1, xmm2/m128

VEX.128.66.0F38.WIG 1D /r

V/V

AVX

Compute the absolute value of 16- bit integers in

xmm2/m128 and store UNSIGNED result in xmm1.

VPABSW xmm1, xmm2/m128

VEX.128.66.0F38.WIG 1E /r

V/V

AVX

Compute the absolute value of 32- bit integers in

xmm2/m128 and store UNSIGNED result in xmm1.

VPABSD xmm1, xmm2/m128

VEX.256.66.0F38.WIG 1C /r

V/V

AVX2

Compute the absolute value of bytes in

VPABSB ymm1, ymm2/m256

ymm2/m256 and store UNSIGNED result in ymm1.

VEX.256.66.0F38.WIG 1D /r

V/V

AVX2

Compute the absolute value of 16-bit integers in

ymm2/m256 and store UNSIGNED result in ymm1.

VPABSW ymm1, ymm2/m256

VEX.256.66.0F38.WIG 1E /r

V/V

AVX2

Compute the absolute value of 32-bit integers in

ymm2/m256 and store UNSIGNED result in ymm1.

VPABSD ymm1, ymm2/m256

EVEX.128.66.0F38.WIG 1C /r

V/V

AVX512VL

Compute the absolute value of bytes in

VPABSB xmm1 {k1}{z}, xmm2/m128

AVX512BW

xmm2/m128 and store UNSIGNED result in xmm1

using writemask k1.

EVEX.256.66.0F38.WIG 1C /r

V/V

AVX512VL

Compute the absolute value of bytes in

VPABSB ymm1 {k1}{z}, ymm2/m256

AVX512BW

ymm2/m256 and store UNSIGNED result in ymm1

using writemask k1.

EVEX.512.66.0F38.WIG 1C /r

V/V

AVX512BW

Compute the absolute value of bytes in

VPABSB zmm1 {k1}{z}, zmm2/m512

zmm2/m512 and store UNSIGNED result in zmm1

using writemask k1.

EVEX.128.66.0F38.WIG 1D /r

V/V

AVX512VL

Compute the absolute value of 16-bit integers in

VPABSW xmm1 {k1}{z}, xmm2/m128

AVX512BW

xmm2/m128 and store UNSIGNED result in xmm1

using writemask k1.

EVEX.256.66.0F38.WIG 1D /r

V/V

AVX512VL

Compute the absolute value of 16-bit integers in

VPABSW ymm1 {k1}{z}, ymm2/m256

AVX512BW

ymm2/m256 and store UNSIGNED result in ymm1

using writemask k1.

EVEX.512.66.0F38.WIG 1D /r

V/V

AVX512BW

Compute the absolute value of 16-bit integers in

VPABSW zmm1 {k1}{z}, zmm2/m512

zmm2/m512 and store UNSIGNED result in zmm1

using writemask k1.

4-182

Vol. 2B

PABSB/PABSW/PABSD/PABSQ-Packed Absolute Value

INSTRUCTION SET REFERENCE, M-U

Opcode/

Op/

64/32 bit

CPUID

Description

Instruction

Mode

Feature

Support

Flag

EVEX.128.66.0F38.W0 1E /r

V/V

AVX512VL

Compute the absolute value of 32-bit integers in

VPABSD xmm1 {k1}{z}, xmm2/m128/m32bcst

AVX512F

xmm2/m128/m32bcst and store UNSIGNED result

in xmm1 using writemask k1.

EVEX.256.66.0F38.W0 1E /r

V/V

AVX512VL

Compute the absolute value of 32-bit integers in

VPABSD ymm1 {k1}{z}, ymm2/m256/m32bcst

AVX512F

ymm2/m256/m32bcst and store UNSIGNED result

in ymm1 using writemask k1.

EVEX.512.66.0F38.W0 1E /r

V/V

AVX512F

Compute the absolute value of 32-bit integers in

VPABSD zmm1 {k1}{z}, zmm2/m512/m32bcst

zmm2/m512/m32bcst and store UNSIGNED result

in zmm1 using writemask k1.

EVEX.128.66.0F38.W1 1F /r

V/V

AVX512VL

Compute the absolute value of 64-bit integers in

VPABSQ xmm1 {k1}{z}, xmm2/m128/m64bcst

AVX512F

xmm2/m128/m64bcst and store UNSIGNED result

in xmm1 using writemask k1.

EVEX.256.66.0F38.W1 1F /r

V/V

AVX512VL

Compute the absolute value of 64-bit integers in

VPABSQ ymm1 {k1}{z}, ymm2/m256/m64bcst

AVX512F

ymm2/m256/m64bcst and store UNSIGNED result

in ymm1 using writemask k1.

EVEX.512.66.0F38.W1 1F /r

V/V

AVX512F

Compute the absolute value of 64-bit integers in

VPABSQ zmm1 {k1}{z}, zmm2/m512/m64bcst

zmm2/m512/m64bcst and store UNSIGNED result

in zmm1 using writemask k1.

NOTES:

1. See note in Section 2.5, “Intel® AVX and Intel® SSE Instruction Exception Classification,” in the Intel^® 64 and IA-32 Architectures Soft-

ware Developer’s Manual, Volume 2A, and Section 23.25.3, “Exception Conditions of Legacy SIMD Instructions Operating on MMX

Registers,” in the Intel^® 64 and IA-32 Architectures Software Developer’s Manual, Volume 3B.

Instruction Operand Encoding

Op/En

Tuple Type

Operand 1

Operand 2

Operand 3

Operand 4

N/A

ModRM:reg (w)

ModRM:r/m (r)

N/A

Full Mem

ModRM:reg (w)

ModRM:r/m (r)

N/A

Full

ModRM:reg (w)

ModRM:r/m (r)

N/A

Description

PABSB/W/D computes the absolute value of each data element of the source operand (the second operand) and

stores the UNSIGNED results in the destination operand (the first operand). PABSB operates on signed bytes,

PABSW operates on signed 16-bit words, and PABSD operates on signed 32-bit integers.

EVEX encoded VPABSD/Q: The source operand is a ZMM/YMM/XMM register, a 512/256/128-bit memory location,

or a 512/256/128-bit vector broadcasted from a 32/64-bit memory location. The destination operand is a

ZMM/YMM/XMM register updated according to the writemask.

EVEX encoded VPABSB/W: The source operand is a ZMM/YMM/XMM register, or a 512/256/128-bit memory loca-

tion. The destination operand is a ZMM/YMM/XMM register updated according to the writemask.

VEX.256 encoded versions: The source operand is a YMM register or a 256-bit memory location. The destination

operand is a YMM register. The upper bits (MAXVL-1:256) of the corresponding register destination are zeroed.

VEX.128 encoded versions: The source operand is an XMM register or 128-bit memory location. The destination

operand is an XMM register. The upper bits (MAXVL-1:128) of the corresponding register destination are zeroed.

128-bit Legacy SSE version: The source operand can be an XMM register or an 128-bit memory location. The desti-

nation is an XMM register. The upper bits (VL_MAX-1:128) of the corresponding register destination are unmodi-

fied.

VEX.vvvv and EVEX.vvvv are reserved and must be 1111b otherwise instructions will #UD.

PABSB/PABSW/PABSD/PABSQ-Packed Absolute Value

Vol. 2B

4-183

INSTRUCTION SET REFERENCE, M-U

Operation

PABSB With 128-bit Operands:

Unsigned DEST[7:0] := ABS(SRC[7: 0])

Repeat operation for 2nd through 15th bytes

Unsigned DEST[127:120] := ABS(SRC[127:120])

VPABSB With 128-bit Operands:

Unsigned DEST[7:0] := ABS(SRC[7: 0])

Repeat operation for 2nd through 15th bytes

Unsigned DEST[127:120] := ABS(SRC[127:120])

VPABSB With 256-bit Operands:

Unsigned DEST[7:0] := ABS(SRC[7: 0])

Repeat operation for 2nd through 31st bytes

Unsigned DEST[255:248] := ABS(SRC[255:248])

VPABSB (EVEX Encoded Versions)

(KL, VL) = (16, 128), (32, 256), (64, 512)

FOR j := 0 TO KL-1

i := j * 8

IF k1[j] OR *no writemask*

THEN

Unsigned DEST[i+7:i] := ABS(SRC[i+7:i])

ELSE

IF *merging-masking*

; merging-masking

THEN *DEST[i+7:i] remains unchanged*

ELSE *zeroing-masking*

; zeroing-masking

DEST[i+7:i] := 0

FI;

ENDFOR;

DEST[MAXVL-1:VL] := 0

PABSW With 128-bit Operands:

Unsigned DEST[15:0] := ABS(SRC[15:0])

Repeat operation for 2nd through 7th 16-bit words

Unsigned DEST[127:112] := ABS(SRC[127:112])

VPABSW With 128-bit Operands:

Unsigned DEST[15:0] := ABS(SRC[15:0])

Repeat operation for 2nd through 7th 16-bit words

Unsigned DEST[127:112] := ABS(SRC[127:112])

VPABSW With 256-bit Operands:

Unsigned DEST[15:0] := ABS(SRC[15:0])

Repeat operation for 2nd through 15th 16-bit words

Unsigned DEST[255:240] := ABS(SRC[255:240])

4-184

Vol. 2B

PABSB/PABSW/PABSD/PABSQ-Packed Absolute Value

INSTRUCTION SET REFERENCE, M-U

VPABSW (EVEX Encoded Versions)

(KL, VL) = (8, 128), (16, 256), (32, 512)

FOR j := 0 TO KL-1

i := j * 16

IF k1[j] OR *no writemask*

THEN

Unsigned DEST[i+15:i] := ABS(SRC[i+15:i])

ELSE

IF *merging-masking*

; merging-masking

THEN *DEST[i+15:i] remains unchanged*

ELSE *zeroing-masking*

; zeroing-masking

DEST[i+15:i] := 0

FI;

ENDFOR;

DEST[MAXVL-1:VL] := 0

PABSD With 128-bit Operands:

Unsigned DEST[31:0] := ABS(SRC[31:0])

Repeat operation for 2nd through 3rd 32-bit double words

Unsigned DEST[127:96] := ABS(SRC[127:96])

VPABSD With 128-bit Operands:

Unsigned DEST[31:0] := ABS(SRC[31:0])

Repeat operation for 2nd through 3rd 32-bit double words

Unsigned DEST[127:96] := ABS(SRC[127:96])

VPABSD With 256-bit Operands:

Unsigned DEST[31:0] := ABS(SRC[31:0])

Repeat operation for 2nd through 7th 32-bit double words

Unsigned DEST[255:224] := ABS(SRC[255:224])

VPABSD (EVEX Encoded Versions)

(KL, VL) = (4, 128), (8, 256), (16, 512)

FOR j := 0 TO KL-1

i := j * 32

IF k1[j] OR *no writemask*

THEN

IF (EVEX.b = 1) AND (SRC *is memory*)

THEN

Unsigned DEST[i+31:i] := ABS(SRC[31:0])

ELSE

Unsigned DEST[i+31:i] := ABS(SRC[i+31:i])

FI;

ELSE

IF *merging-masking*

; merging-masking

THEN *DEST[i+31:i] remains unchanged*

ELSE *zeroing-masking*

; zeroing-masking

DEST[i+31:i] := 0

FI;

ENDFOR;

DEST[MAXVL-1:VL] := 0

PABSB/PABSW/PABSD/PABSQ-Packed Absolute Value

Vol. 2B

4-185

INSTRUCTION SET REFERENCE, M-U

VPABSQ (EVEX Encoded Versions)

(KL, VL) = (2, 128), (4, 256), (8, 512)

FOR j := 0 TO KL-1

i := j * 64

IF k1[j] OR *no writemask*

THEN

IF (EVEX.b = 1) AND (SRC *is memory*)

THEN

Unsigned DEST[i+63:i] := ABS(SRC[63:0])

ELSE

Unsigned DEST[i+63:i] := ABS(SRC[i+63:i])

FI;

ELSE

IF *merging-masking*

; merging-masking

THEN *DEST[i+63:i] remains unchanged*

ELSE *zeroing-masking*

; zeroing-masking

DEST[i+63:i] := 0

FI;

ENDFOR;

DEST[MAXVL-1:VL] := 0

Intel C/C++ Compiler Intrinsic Equivalents

VPABSB__m512i _mm512_abs_epi8 ( __m512i a)

VPABSW__m512i _mm512_abs_epi16 ( __m512i a)

VPABSB__m512i _mm512_mask_abs_epi8 ( __m512i s, __mmask64 m, __m512i a)

VPABSW__m512i _mm512_mask_abs_epi16 ( __m512i s, __mmask32 m, __m512i a)

VPABSB__m512i _mm512_maskz_abs_epi8 (__mmask64 m, __m512i a)

VPABSW__m512i _mm512_maskz_abs_epi16 (__mmask32 m, __m512i a)

VPABSB__m256i _mm256_mask_abs_epi8 (__m256i s, __mmask32 m, __m256i a)

VPABSW__m256i _mm256_mask_abs_epi16 (__m256i s, __mmask16 m, __m256i a)

VPABSB__m256i _mm256_maskz_abs_epi8 (__mmask32 m, __m256i a)

VPABSW__m256i _mm256_maskz_abs_epi16 (__mmask16 m, __m256i a)

VPABSB__m128i _mm_mask_abs_epi8 (__m128i s, __mmask16 m, __m128i a)

VPABSW__m128i _mm_mask_abs_epi16 (__m128i s, __mmask8 m, __m128i a)

VPABSB__m128i _mm_maskz_abs_epi8 (__mmask16 m, __m128i a)

VPABSW__m128i _mm_maskz_abs_epi16 (__mmask8 m, __m128i a)

VPABSD __m256i _mm256_mask_abs_epi32(__m256i s, __mmask8 k, __m256i a);

VPABSD __m256i _mm256_maskz_abs_epi32( __mmask8 k, __m256i a);

VPABSD __m128i _mm_mask_abs_epi32(__m128i s, __mmask8 k, __m128i a);

VPABSD __m128i _mm_maskz_abs_epi32( __mmask8 k, __m128i a);

VPABSD __m512i _mm512_abs_epi32( __m512i a);

VPABSD __m512i _mm512_mask_abs_epi32(__m512i s, __mmask16 k, __m512i a);

VPABSD __m512i _mm512_maskz_abs_epi32( __mmask16 k, __m512i a);

VPABSQ __m512i _mm512_abs_epi64( __m512i a);

VPABSQ __m512i _mm512_mask_abs_epi64(__m512i s, __mmask8 k, __m512i a);

VPABSQ __m512i _mm512_maskz_abs_epi64( __mmask8 k, __m512i a);

VPABSQ __m256i _mm256_mask_abs_epi64(__m256i s, __mmask8 k, __m256i a);

VPABSQ __m256i _mm256_maskz_abs_epi64( __mmask8 k, __m256i a);

VPABSQ __m128i _mm_mask_abs_epi64(__m128i s, __mmask8 k, __m128i a);

VPABSQ __m128i _mm_maskz_abs_epi64( __mmask8 k, __m128i a);

PABSB __m128i _mm_abs_epi8 (__m128i a)

4-186

Vol. 2B

PABSB/PABSW/PABSD/PABSQ-Packed Absolute Value

INSTRUCTION SET REFERENCE, M-U

VPABSB __m128i _mm_abs_epi8 (__m128i a)

VPABSB __m256i _mm256_abs_epi8 (__m256i a)

PABSW __m128i _mm_abs_epi16 (__m128i a)

VPABSW __m128i _mm_abs_epi16 (__m128i a)

VPABSW __m256i _mm256_abs_epi16 (__m256i a)

PABSD __m128i _mm_abs_epi32 (__m128i a)

VPABSD __m128i _mm_abs_epi32 (__m128i a)

VPABSD __m256i _mm256_abs_epi32 (__m256i a)

SIMD Floating-Point Exceptions

None.

Other Exceptions

Non-EVEX-encoded instruction, see Table 2-21, “Type 4 Class Exception Conditions.”

EVEX-encoded VPABSD/Q, see Table 2-49, “Type E4 Class Exception Conditions.”

EVEX-encoded VPABSB/W, see Exceptions Type E4.nb in Table 2-49, “Type E4 Class Exception Conditions.”

PABSB/PABSW/PABSD/PABSQ-Packed Absolute Value

Vol. 2B

4-187

INSTRUCTION SET REFERENCE, M-U

PACKSSWB/PACKSSDW-Pack With Signed Saturation

Opcode/

Op/

64/32 bit

CPUID

Description

Instruction

Mode

Feature Flag

Support

NP 0F 63 /r¹

V/V

MMX

Converts 4 packed signed word integers from mm1

and from mm2/m64 into 8 packed signed byte

PACKSSWB mm1, mm2/m64

integers in mm1 using signed saturation.

66 0F 63 /r

V/V

SSE2

Converts 8 packed signed word integers from

xmm1 and from xmm2/m128 into 16 packed

PACKSSWB xmm1, xmm2/m128

signed byte integers in xmm1 using signed

saturation.

NP 0F 6B /r¹

V/V

MMX

Converts 2 packed signed doubleword integers

from mm1 and from mm2/m64 into 4 packed

PACKSSDW mm1, mm2/m64

signed word integers in mm1 using signed

saturation.

66 0F 6B /r

V/V

SSE2

Converts 4 packed signed doubleword integers

from xmm1 and from xmm2/m128 into 8 packed

PACKSSDW xmm1, xmm2/m128

signed word integers in xmm1 using signed

saturation.

VEX.128.66.0F.WIG 63 /r

V/V

AVX

Converts 8 packed signed word integers from

xmm2 and from xmm3/m128 into 16 packed

VPACKSSWB xmm1,xmm2, xmm3/m128

signed byte integers in xmm1 using signed

saturation.

VEX.128.66.0F.WIG 6B /r

V/V

AVX

Converts 4 packed signed doubleword integers

from xmm2 and from xmm3/m128 into 8 packed

VPACKSSDW xmm1,xmm2, xmm3/m128

signed word integers in xmm1 using signed

saturation.

VEX.256.66.0F.WIG 63 /r

V/V

AVX2

Converts 16 packed signed word integers from

ymm2 and from ymm3/m256 into 32 packed

VPACKSSWB ymm1, ymm2, ymm3/m256

signed byte integers in ymm1 using signed

saturation.

VEX.256.66.0F.WIG 6B /r

V/V

AVX2

Converts 8 packed signed doubleword integers

from ymm2 and from ymm3/m256 into 16 packed

VPACKSSDW ymm1, ymm2, ymm3/m256

signed word integers in ymm1using signed

saturation.

EVEX.128.66.0F.WIG 63 /r

V/V

AVX512VL

Converts packed signed word integers from xmm2

VPACKSSWB xmm1 {k1}{z}, xmm2,

AVX512BW

and from xmm3/m128 into packed signed byte

xmm3/m128

integers in xmm1 using signed saturation under

writemask k1.

EVEX.256.66.0F.WIG 63 /r

V/V

AVX512VL

Converts packed signed word integers from ymm2

VPACKSSWB ymm1 {k1}{z}, ymm2,

AVX512BW

and from ymm3/m256 into packed signed byte

ymm3/m256

integers in ymm1 using signed saturation under

writemask k1.

EVEX.512.66.0F.WIG 63 /r

V/V

AVX512BW

Converts packed signed word integers from zmm2

VPACKSSWB zmm1 {k1}{z}, zmm2,

and from zmm3/m512 into packed signed byte

zmm3/m512

integers in zmm1 using signed saturation under

writemask k1.

EVEX.128.66.0F.W0 6B /r

V/V

AVX512VL

Converts packed signed doubleword integers from

VPACKSSDW xmm1 {k1}{z}, xmm2,

AVX512BW

xmm2 and from xmm3/m128/m32bcst into packed

xmm3/m128/m32bcst

signed word integers in xmm1 using signed

saturation under writemask k1.

4-188

Vol. 2B

PACKSSWB/PACKSSDW-Pack With Signed Saturation

INSTRUCTION SET REFERENCE, M-U

Opcode/

Op/

64/32 bit

CPUID

Description

Instruction

Mode

Feature Flag

Support

EVEX.256.66.0F.W0 6B /r

V/V

AVX512VL

Converts packed signed doubleword integers from

VPACKSSDW ymm1 {k1}{z}, ymm2,

AVX512BW

ymm2 and from ymm3/m256/m32bcst into packed

ymm3/m256/m32bcst

signed word integers in ymm1 using signed

saturation under writemask k1.

EVEX.512.66.0F.W0 6B /r

V/V

AVX512BW

Converts packed signed doubleword integers from

VPACKSSDW zmm1 {k1}{z}, zmm2,

zmm2 and from zmm3/m512/m32bcst into packed

zmm3/m512/m32bcst

signed word integers in zmm1 using signed

saturation under writemask k1.

NOTES:

1. See note in Section 2.5, “Intel® AVX and Intel® SSE Instruction Exception Classification,” in the Intel^® 64 and IA-32 Architectures Soft-

ware Developer’s Manual, Volume 2A, and Section 23.25.3, “Exception Conditions of Legacy SIMD Instructions Operating on MMX Reg-

isters,” in the Intel^® 64 and IA-32 Architectures Software Developer’s Manual, Volume 3B.

Instruction Operand Encoding

Op/En

Tuple Type

Operand 1

Operand 2

Operand 3

Operand 4

N/A

ModRM:reg (r, w)

ModRM:r/m (r)

N/A

ModRM:reg (w)

VEX.vvvv (r)

ModRM:r/m (r)

N/A

Full Mem

ModRM:reg (w)

EVEX.vvvv (r)

ModRM:r/m (r)

N/A

Full

ModRM:reg (w)

EVEX.vvvv (r)

ModRM:r/m (r)

N/A

Description

Converts packed signed word integers into packed signed byte integers (PACKSSWB) or converts packed signed

doubleword integers into packed signed word integers (PACKSSDW), using saturation to handle overflow condi-

tions. See Figure 4-6 for an example of the packing operation.

64-Bit SRC

64-Bit DEST

D’

C’

B’

A’

64-Bit DEST

Figure 4-6. Operation of the PACKSSDW Instruction Using 64-Bit Operands

PACKSSWB converts packed signed word integers in the first and second source operands into packed signed byte

integers using signed saturation to handle overflow conditions beyond the range of signed byte integers. If the

signed word value is beyond the range of a signed byte value (i.e., greater than 7FH or less than 80H), the satu-

rated signed byte integer value of 7FH or 80H, respectively, is stored in the destination. PACKSSDW converts

packed signed doubleword integers in the first and second source operands into packed signed word integers using

signed saturation to handle overflow conditions beyond 7FFFH and 8000H.

EVEX encoded PACKSSWB: The first source operand is a ZMM/YMM/XMM register. The second source operand is a

ZMM/YMM/XMM register or a 512/256/128-bit memory location. The destination operand is a ZMM/YMM/XMM

EVEX encoded PACKSSDW: The first source operand is a ZMM/YMM/XMM register. The second source operand is a

ZMM/YMM/XMM register, a 512/256/128-bit memory location, or a 512/256/128-bit vector broadcasted from a 32-

PACKSSWB/PACKSSDW-Pack With Signed Saturation

Vol. 2B

4-189

INSTRUCTION SET REFERENCE, M-U

bit memory location. The destination operand is a ZMM/YMM/XMM register, updated conditional under the write-

mask k1.

VEX.256 encoded version: The first source operand is a YMM register. The second source operand is a YMM register

or a 256-bit memory location. The destination operand is a YMM register. The upper bits (MAXVL-1:256) of the

corresponding ZMM register destination are zeroed.

VEX.128 encoded version: The first source operand is an XMM register. The second source operand is an XMM

the corresponding ZMM register destination are zeroed.

128-bit Legacy SSE version: The first source operand is an XMM register. The second operand can be an XMM

upper bits (MAXVL-1:128) of the corresponding ZMM destination register destination are unmodified.

Operation

PACKSSWB Instruction (128-bit Legacy SSE Version)

DEST[7:0] := SaturateSignedWordToSignedByte (DEST[15:0]);

DEST[15:8] := SaturateSignedWordToSignedByte (DEST[31:16]);

DEST[23:16] := SaturateSignedWordToSignedByte (DEST[47:32]);

DEST[31:24] := SaturateSignedWordToSignedByte (DEST[63:48]);

DEST[39:32] := SaturateSignedWordToSignedByte (DEST[79:64]);

DEST[47:40] := SaturateSignedWordToSignedByte (DEST[95:80]);

DEST[55:48] := SaturateSignedWordToSignedByte (DEST[111:96]);

DEST[63:56] := SaturateSignedWordToSignedByte (DEST[127:112]);

DEST[71:64] := SaturateSignedWordToSignedByte (SRC[15:0]);

DEST[79:72] := SaturateSignedWordToSignedByte (SRC[31:16]);

DEST[87:80] := SaturateSignedWordToSignedByte (SRC[47:32]);

DEST[95:88] := SaturateSignedWordToSignedByte (SRC[63:48]);

DEST[103:96] := SaturateSignedWordToSignedByte (SRC[79:64]);

DEST[111:104] := SaturateSignedWordToSignedByte (SRC[95:80]);

DEST[119:112] := SaturateSignedWordToSignedByte (SRC[111:96]);

DEST[127:120] := SaturateSignedWordToSignedByte (SRC[127:112]);

DEST[MAXVL-1:128] (Unmodified)

PACKSSDW Instruction (128-bit Legacy SSE Version)

DEST[15:0] := SaturateSignedDwordToSignedWord (DEST[31:0]);

DEST[31:16] := SaturateSignedDwordToSignedWord (DEST[63:32]);

DEST[47:32] := SaturateSignedDwordToSignedWord (DEST[95:64]);

DEST[63:48] := SaturateSignedDwordToSignedWord (DEST[127:96]);

DEST[79:64] := SaturateSignedDwordToSignedWord (SRC[31:0]);

DEST[95:80] := SaturateSignedDwordToSignedWord (SRC[63:32]);

DEST[111:96] := SaturateSignedDwordToSignedWord (SRC[95:64]);

DEST[127:112] := SaturateSignedDwordToSignedWord (SRC[127:96]);

DEST[MAXVL-1:128] (Unmodified)

4-190

Vol. 2B

PACKSSWB/PACKSSDW-Pack With Signed Saturation

INSTRUCTION SET REFERENCE, M-U

VPACKSSWB Instruction (VEX.128 Encoded Version)

DEST[7:0] := SaturateSignedWordToSignedByte (SRC1[15:0]);

DEST[15:8] := SaturateSignedWordToSignedByte (SRC1[31:16]);

DEST[23:16] := SaturateSignedWordToSignedByte (SRC1[47:32]);

DEST[31:24] := SaturateSignedWordToSignedByte (SRC1[63:48]);

DEST[39:32] := SaturateSignedWordToSignedByte (SRC1[79:64]);

DEST[47:40] := SaturateSignedWordToSignedByte (SRC1[95:80]);

DEST[55:48] := SaturateSignedWordToSignedByte (SRC1[111:96]);

DEST[63:56] := SaturateSignedWordToSignedByte (SRC1[127:112]);

DEST[71:64] := SaturateSignedWordToSignedByte (SRC2[15:0]);

DEST[79:72] := SaturateSignedWordToSignedByte (SRC2[31:16]);

DEST[87:80] := SaturateSignedWordToSignedByte (SRC2[47:32]);

DEST[95:88] := SaturateSignedWordToSignedByte (SRC2[63:48]);

DEST[103:96] := SaturateSignedWordToSignedByte (SRC2[79:64]);

DEST[111:104] := SaturateSignedWordToSignedByte (SRC2[95:80]);

DEST[119:112] := SaturateSignedWordToSignedByte (SRC2[111:96]);

DEST[127:120] := SaturateSignedWordToSignedByte (SRC2[127:112]);

DEST[MAXVL-1:128] := 0;

VPACKSSDW Instruction (VEX.128 Encoded Version)

DEST[15:0] := SaturateSignedDwordToSignedWord (SRC1[31:0]);

DEST[31:16] := SaturateSignedDwordToSignedWord (SRC1[63:32]);

DEST[47:32] := SaturateSignedDwordToSignedWord (SRC1[95:64]);

DEST[63:48] := SaturateSignedDwordToSignedWord (SRC1[127:96]);

DEST[79:64] := SaturateSignedDwordToSignedWord (SRC2[31:0]);

DEST[95:80] := SaturateSignedDwordToSignedWord (SRC2[63:32]);

DEST[111:96] := SaturateSignedDwordToSignedWord (SRC2[95:64]);

DEST[127:112] := SaturateSignedDwordToSignedWord (SRC2[127:96]);

DEST[MAXVL-1:128] := 0;

VPACKSSWB Instruction (VEX.256 Encoded Version)

DEST[7:0] := SaturateSignedWordToSignedByte (SRC1[15:0]);

DEST[15:8] := SaturateSignedWordToSignedByte (SRC1[31:16]);

DEST[23:16] := SaturateSignedWordToSignedByte (SRC1[47:32]);

DEST[31:24] := SaturateSignedWordToSignedByte (SRC1[63:48]);

DEST[39:32] := SaturateSignedWordToSignedByte (SRC1[79:64]);

DEST[47:40] := SaturateSignedWordToSignedByte (SRC1[95:80]);

DEST[55:48] := SaturateSignedWordToSignedByte (SRC1[111:96]);

DEST[63:56] := SaturateSignedWordToSignedByte (SRC1[127:112]);

DEST[71:64] := SaturateSignedWordToSignedByte (SRC2[15:0]);

DEST[79:72] := SaturateSignedWordToSignedByte (SRC2[31:16]);

DEST[87:80] := SaturateSignedWordToSignedByte (SRC2[47:32]);

DEST[95:88] := SaturateSignedWordToSignedByte (SRC2[63:48]);

DEST[103:96] := SaturateSignedWordToSignedByte (SRC2[79:64]);

DEST[111:104] := SaturateSignedWordToSignedByte (SRC2[95:80]);

DEST[119:112] := SaturateSignedWordToSignedByte (SRC2[111:96]);

DEST[127:120] := SaturateSignedWordToSignedByte (SRC2[127:112]);

DEST[135:128] := SaturateSignedWordToSignedByte (SRC1[143:128]);

DEST[143:136] := SaturateSignedWordToSignedByte (SRC1[159:144]);

DEST[151:144] := SaturateSignedWordToSignedByte (SRC1[175:160]);

DEST[159:152] := SaturateSignedWordToSignedByte (SRC1[191:176]);

DEST[167:160] := SaturateSignedWordToSignedByte (SRC1[207:192]);

DEST[175:168] := SaturateSignedWordToSignedByte (SRC1[223:208]);

DEST[183:176] := SaturateSignedWordToSignedByte (SRC1[239:224]);

PACKSSWB/PACKSSDW-Pack With Signed Saturation

Vol. 2B

4-191

INSTRUCTION SET REFERENCE, M-U

DEST[191:184] := SaturateSignedWordToSignedByte (SRC1[255:240]);

DEST[199:192] := SaturateSignedWordToSignedByte (SRC2[143:128]);

DEST[207:200] := SaturateSignedWordToSignedByte (SRC2[159:144]);

DEST[215:208] := SaturateSignedWordToSignedByte (SRC2[175:160]);

DEST[223:216] := SaturateSignedWordToSignedByte (SRC2[191:176]);

DEST[231:224] := SaturateSignedWordToSignedByte (SRC2[207:192]);

DEST[239:232] := SaturateSignedWordToSignedByte (SRC2[223:208]);

DEST[247:240] := SaturateSignedWordToSignedByte (SRC2[239:224]);

DEST[255:248] := SaturateSignedWordToSignedByte (SRC2[255:240]);

DEST[MAXVL-1:256] := 0;

VPACKSSDW Instruction (VEX.256 Encoded Version)

DEST[15:0] := SaturateSignedDwordToSignedWord (SRC1[31:0]);

DEST[31:16] := SaturateSignedDwordToSignedWord (SRC1[63:32]);

DEST[47:32] := SaturateSignedDwordToSignedWord (SRC1[95:64]);

DEST[63:48] := SaturateSignedDwordToSignedWord (SRC1[127:96]);

DEST[79:64] := SaturateSignedDwordToSignedWord (SRC2[31:0]);

DEST[95:80] := SaturateSignedDwordToSignedWord (SRC2[63:32]);

DEST[111:96] := SaturateSignedDwordToSignedWord (SRC2[95:64]);

DEST[127:112] := SaturateSignedDwordToSignedWord (SRC2[127:96]);

DEST[143:128] := SaturateSignedDwordToSignedWord (SRC1[159:128]);

DEST[159:144] := SaturateSignedDwordToSignedWord (SRC1[191:160]);

DEST[175:160] := SaturateSignedDwordToSignedWord (SRC1[223:192]);

DEST[191:176] := SaturateSignedDwordToSignedWord (SRC1[255:224]);

DEST[207:192] := SaturateSignedDwordToSignedWord (SRC2[159:128]);

DEST[223:208] := SaturateSignedDwordToSignedWord (SRC2[191:160]);

DEST[239:224] := SaturateSignedDwordToSignedWord (SRC2[223:192]);

DEST[255:240] := SaturateSignedDwordToSignedWord (SRC2[255:224]);

DEST[MAXVL-1:256] := 0;

VPACKSSWB (EVEX Encoded Versions)

(KL, VL) = (16, 128), (32, 256), (64, 512)

TMP_DEST[7:0] := SaturateSignedWordToSignedByte (SRC1[15:0]);

TMP_DEST[15:8] := SaturateSignedWordToSignedByte (SRC1[31:16]);

TMP_DEST[23:16] := SaturateSignedWordToSignedByte (SRC1[47:32]);

TMP_DEST[31:24] := SaturateSignedWordToSignedByte (SRC1[63:48]);

TMP_DEST[39:32] := SaturateSignedWordToSignedByte (SRC1[79:64]);

TMP_DEST[47:40] := SaturateSignedWordToSignedByte (SRC1[95:80]);

TMP_DEST[55:48] := SaturateSignedWordToSignedByte (SRC1[111:96]);

TMP_DEST[63:56] := SaturateSignedWordToSignedByte (SRC1[127:112]);

TMP_DEST[71:64] := SaturateSignedWordToSignedByte (SRC2[15:0]);

TMP_DEST[79:72] := SaturateSignedWordToSignedByte (SRC2[31:16]);

TMP_DEST[87:80] := SaturateSignedWordToSignedByte (SRC2[47:32]);

TMP_DEST[95:88] := SaturateSignedWordToSignedByte (SRC2[63:48]);

TMP_DEST[103:96] := SaturateSignedWordToSignedByte (SRC2[79:64]);

TMP_DEST[111:104] := SaturateSignedWordToSignedByte (SRC2[95:80]);

TMP_DEST[119:112] := SaturateSignedWordToSignedByte (SRC2[111:96]);

TMP_DEST[127:120] := SaturateSignedWordToSignedByte (SRC2[127:112]);

IF VL >= 256

TMP_DEST[135:128] := SaturateSignedWordToSignedByte (SRC1[143:128]);

TMP_DEST[143:136] := SaturateSignedWordToSignedByte (SRC1[159:144]);

TMP_DEST[151:144] := SaturateSignedWordToSignedByte (SRC1[175:160]);

TMP_DEST[159:152] := SaturateSignedWordToSignedByte (SRC1[191:176]);

TMP_DEST[167:160] := SaturateSignedWordToSignedByte (SRC1[207:192]);

4-192

Vol. 2B

PACKSSWB/PACKSSDW-Pack With Signed Saturation

INSTRUCTION SET REFERENCE, M-U

TMP_DEST[175:168] := SaturateSignedWordToSignedByte (SRC1[223:208]);

TMP_DEST[183:176] := SaturateSignedWordToSignedByte (SRC1[239:224]);

TMP_DEST[191:184] := SaturateSignedWordToSignedByte (SRC1[255:240]);

TMP_DEST[199:192] := SaturateSignedWordToSignedByte (SRC2[143:128]);

TMP_DEST[207:200] := SaturateSignedWordToSignedByte (SRC2[159:144]);

TMP_DEST[215:208] := SaturateSignedWordToSignedByte (SRC2[175:160]);

TMP_DEST[223:216] := SaturateSignedWordToSignedByte (SRC2[191:176]);

TMP_DEST[231:224] := SaturateSignedWordToSignedByte (SRC2[207:192]);

TMP_DEST[239:232] := SaturateSignedWordToSignedByte (SRC2[223:208]);

TMP_DEST[247:240] := SaturateSignedWordToSignedByte (SRC2[239:224]);

TMP_DEST[255:248] := SaturateSignedWordToSignedByte (SRC2[255:240]);

FI;

IF VL >= 512

TMP_DEST[263:256] := SaturateSignedWordToSignedByte (SRC1[271:256]);

TMP_DEST[271:264] := SaturateSignedWordToSignedByte (SRC1[287:272]);

TMP_DEST[279:272] := SaturateSignedWordToSignedByte (SRC1[303:288]);

TMP_DEST[287:280] := SaturateSignedWordToSignedByte (SRC1[319:304]);

TMP_DEST[295:288] := SaturateSignedWordToSignedByte (SRC1[335:320]);

TMP_DEST[303:296] := SaturateSignedWordToSignedByte (SRC1[351:336]);

TMP_DEST[311:304] := SaturateSignedWordToSignedByte (SRC1[367:352]);

TMP_DEST[319:312] := SaturateSignedWordToSignedByte (SRC1[383:368]);

TMP_DEST[327:320] := SaturateSignedWordToSignedByte (SRC2[271:256]);

TMP_DEST[335:328] := SaturateSignedWordToSignedByte (SRC2[287:272]);

TMP_DEST[343:336] := SaturateSignedWordToSignedByte (SRC2[303:288]);

TMP_DEST[351:344] := SaturateSignedWordToSignedByte (SRC2[319:304]);

TMP_DEST[359:352] := SaturateSignedWordToSignedByte (SRC2[335:320]);

TMP_DEST[367:360] := SaturateSignedWordToSignedByte (SRC2[351:336]);

TMP_DEST[375:368] := SaturateSignedWordToSignedByte (SRC2[367:352]);

TMP_DEST[383:376] := SaturateSignedWordToSignedByte (SRC2[383:368]);

TMP_DEST[391:384] := SaturateSignedWordToSignedByte (SRC1[399:384]);

TMP_DEST[399:392] := SaturateSignedWordToSignedByte (SRC1[415:400]);

TMP_DEST[407:400] := SaturateSignedWordToSignedByte (SRC1[431:416]);

TMP_DEST[415:408] := SaturateSignedWordToSignedByte (SRC1[447:432]);

TMP_DEST[423:416] := SaturateSignedWordToSignedByte (SRC1[463:448]);

TMP_DEST[431:424] := SaturateSignedWordToSignedByte (SRC1[479:464]);

TMP_DEST[439:432] := SaturateSignedWordToSignedByte (SRC1[495:480]);

TMP_DEST[447:440] := SaturateSignedWordToSignedByte (SRC1[511:496]);

TMP_DEST[455:448] := SaturateSignedWordToSignedByte (SRC2[399:384]);

TMP_DEST[463:456] := SaturateSignedWordToSignedByte (SRC2[415:400]);

TMP_DEST[471:464] := SaturateSignedWordToSignedByte (SRC2[431:416]);

TMP_DEST[479:472] := SaturateSignedWordToSignedByte (SRC2[447:432]);

TMP_DEST[487:480] := SaturateSignedWordToSignedByte (SRC2[463:448]);

TMP_DEST[495:488] := SaturateSignedWordToSignedByte (SRC2[479:464]);

TMP_DEST[503:496] := SaturateSignedWordToSignedByte (SRC2[495:480]);

TMP_DEST[511:504] := SaturateSignedWordToSignedByte (SRC2[511:496]);

FI;

FOR j := 0 TO KL-1

i := j * 8

IF k1[j] OR *no writemask*

THEN

DEST[i+7:i] := TMP_DEST[i+7:i]

PACKSSWB/PACKSSDW-Pack With Signed Saturation

Vol. 2B

4-193

INSTRUCTION SET REFERENCE, M-U

ELSE

IF *merging-masking*

; merging-masking

THEN *DEST[i+7:i] remains unchanged*

ELSE *zeroing-masking*

; zeroing-masking

DEST[i+7:i] := 0

FI;

ENDFOR;

DEST[MAXVL-1:VL] := 0

VPACKSSDW (EVEX Encoded Versions)

(KL, VL) = (8, 128), (16, 256), (32, 512)

FOR j := 0 TO ((KL/2) - 1)

i := j * 32

IF (EVEX.b == 1) AND (SRC2 *is memory*)

THEN

TMP_SRC2[i+31:i] := SRC2[31:0]

ELSE

TMP_SRC2[i+31:i] := SRC2[i+31:i]

FI;

ENDFOR;

TMP_DEST[15:0] := SaturateSignedDwordToSignedWord (SRC1[31:0]);

TMP_DEST[31:16] := SaturateSignedDwordToSignedWord (SRC1[63:32]);

TMP_DEST[47:32] := SaturateSignedDwordToSignedWord (SRC1[95:64]);

TMP_DEST[63:48] := SaturateSignedDwordToSignedWord (SRC1[127:96]);

TMP_DEST[79:64] := SaturateSignedDwordToSignedWord (TMP_SRC2[31:0]);

TMP_DEST[95:80] := SaturateSignedDwordToSignedWord (TMP_SRC2[63:32]);

TMP_DEST[111:96] := SaturateSignedDwordToSignedWord (TMP_SRC2[95:64]);

TMP_DEST[127:112] := SaturateSignedDwordToSignedWord (TMP_SRC2[127:96]);

IF VL >= 256

TMP_DEST[143:128] := SaturateSignedDwordToSignedWord (SRC1[159:128]);

TMP_DEST[159:144] := SaturateSignedDwordToSignedWord (SRC1[191:160]);

TMP_DEST[175:160] := SaturateSignedDwordToSignedWord (SRC1[223:192]);

TMP_DEST[191:176] := SaturateSignedDwordToSignedWord (SRC1[255:224]);

TMP_DEST[207:192] := SaturateSignedDwordToSignedWord (TMP_SRC2[159:128]);

TMP_DEST[223:208] := SaturateSignedDwordToSignedWord (TMP_SRC2[191:160]);

TMP_DEST[239:224] := SaturateSignedDwordToSignedWord (TMP_SRC2[223:192]);

TMP_DEST[255:240] := SaturateSignedDwordToSignedWord (TMP_SRC2[255:224]);

FI;

IF VL >= 512

TMP_DEST[271:256] := SaturateSignedDwordToSignedWord (SRC1[287:256]);

TMP_DEST[287:272] := SaturateSignedDwordToSignedWord (SRC1[319:288]);

TMP_DEST[303:288] := SaturateSignedDwordToSignedWord (SRC1[351:320]);

TMP_DEST[319:304] := SaturateSignedDwordToSignedWord (SRC1[383:352]);

TMP_DEST[335:320] := SaturateSignedDwordToSignedWord (TMP_SRC2[287:256]);

TMP_DEST[351:336] := SaturateSignedDwordToSignedWord (TMP_SRC2[319:288]);

TMP_DEST[367:352] := SaturateSignedDwordToSignedWord (TMP_SRC2[351:320]);

TMP_DEST[383:368] := SaturateSignedDwordToSignedWord (TMP_SRC2[383:352]);

TMP_DEST[399:384] := SaturateSignedDwordToSignedWord (SRC1[415:384]);

TMP_DEST[415:400] := SaturateSignedDwordToSignedWord (SRC1[447:416]);

TMP_DEST[431:416] := SaturateSignedDwordToSignedWord (SRC1[479:448]);

4-194

Vol. 2B

PACKSSWB/PACKSSDW-Pack With Signed Saturation

INSTRUCTION SET REFERENCE, M-U

TMP_DEST[447:432] := SaturateSignedDwordToSignedWord (SRC1[511:480]);

TMP_DEST[463:448] := SaturateSignedDwordToSignedWord (TMP_SRC2[415:384]);

TMP_DEST[479:464] := SaturateSignedDwordToSignedWord (TMP_SRC2[447:416]);

TMP_DEST[495:480] := SaturateSignedDwordToSignedWord (TMP_SRC2[479:448]);

TMP_DEST[511:496] := SaturateSignedDwordToSignedWord (TMP_SRC2[511:480]);

FI;

FOR j := 0 TO KL-1

i := j * 16

IF k1[j] OR *no writemask*

THEN DEST[i+15:i] := TMP_DEST[i+15:i]

ELSE

IF *merging-masking*

; merging-masking

THEN *DEST[i+15:i] remains unchanged*

ELSE *zeroing-masking*

; zeroing-masking

DEST[i+15:i] := 0

FI;

ENDFOR;

DEST[MAXVL-1:VL] := 0

Intel C/C++ Compiler Intrinsic Equivalents

VPACKSSDW__m512i _mm512_packs_epi32(__m512i m1, __m512i m2);

VPACKSSDW__m512i _mm512_mask_packs_epi32(__m512i s, __mmask32 k, __m512i m1, __m512i m2);

VPACKSSDW__m512i _mm512_maskz_packs_epi32( __mmask32 k, __m512i m1, __m512i m2);

VPACKSSDW__m256i _mm256_mask_packs_epi32( __m256i s, __mmask16 k, __m256i m1, __m256i m2);

VPACKSSDW__m256i _mm256_maskz_packs_epi32( __mmask16 k, __m256i m1, __m256i m2);

VPACKSSDW__m128i _mm_mask_packs_epi32( __m128i s, __mmask8 k, __m128i m1, __m128i m2);

VPACKSSDW__m128i _mm_maskz_packs_epi32( __mmask8 k, __m128i m1, __m128i m2);

VPACKSSWB__m512i _mm512_packs_epi16(__m512i m1, __m512i m2);

VPACKSSWB__m512i _mm512_mask_packs_epi16(__m512i s, __mmask32 k, __m512i m1, __m512i m2);

VPACKSSWB__m512i _mm512_maskz_packs_epi16( __mmask32 k, __m512i m1, __m512i m2);

VPACKSSWB__m256i _mm256_mask_packs_epi16( __m256i s, __mmask16 k, __m256i m1, __m256i m2);

VPACKSSWB__m256i _mm256_maskz_packs_epi16( __mmask16 k, __m256i m1, __m256i m2);

VPACKSSWB__m128i _mm_mask_packs_epi16( __m128i s, __mmask8 k, __m128i m1, __m128i m2);

VPACKSSWB__m128i _mm_maskz_packs_epi16( __mmask8 k, __m128i m1, __m128i m2);

PACKSSWB __m128i _mm_packs_epi16(__m128i m1, __m128i m2)

PACKSSDW __m128i _mm_packs_epi32(__m128i m1, __m128i m2)

VPACKSSWB __m256i _mm256_packs_epi16(__m256i m1, __m256i m2)

VPACKSSDW __m256i _mm256_packs_epi32(__m256i m1, __m256i m2)

SIMD Floating-Point Exceptions

None.

Other Exceptions

Non-EVEX-encoded instruction, see Table 2-21, “Type 4 Class Exception Conditions.”

EVEX-encoded VPACKSSDW, see Table 2-50, “Type E4NF Class Exception Conditions.”

EVEX-encoded VPACKSSWB, see Exceptions Type E4NF.nb in Table 2-50, “Type E4NF Class Exception Conditions.”

PACKSSWB/PACKSSDW-Pack With Signed Saturation

Vol. 2B

4-195

INSTRUCTION SET REFERENCE, M-U

PACKUSDW-Pack With Unsigned Saturation

Opcode/

Op /

64/32 bit

CPUID

Description

Instruction

Mode

Feature Flag

Support

66 0F 38 2B /r

V/V

SSE4_1

Convert 4 packed signed doubleword integers from xmm1

PACKUSDW xmm1, xmm2/m128

and 4 packed signed doubleword integers from xmm2/m128

into 8 packed unsigned word integers in xmm1 using

unsigned saturation.

VEX.128.66.0F38 2B /r

V/V

AVX

Convert 4 packed signed doubleword integers from xmm2

VPACKUSDW xmm1,xmm2,

and 4 packed signed doubleword integers from xmm3/m128

xmm3/m128

into 8 packed unsigned word integers in xmm1 using

unsigned saturation.

VEX.256.66.0F38 2B /r

V/V

AVX2

Convert 8 packed signed doubleword integers from ymm2

VPACKUSDW ymm1, ymm2,

and 8 packed signed doubleword integers from ymm3/m256

ymm3/m256

into 16 packed unsigned word integers in ymm1 using

unsigned saturation.

EVEX.128.66.0F38.W0 2B /r

V/V

AVX512VL

Convert packed signed doubleword integers from xmm2 and

VPACKUSDW xmm1{k1}{z}, xmm2,

AVX512BW

packed signed doubleword integers from

xmm3/m128/m32bcst

xmm3/m128/m32bcst into packed unsigned word integers in

xmm1 using unsigned saturation under writemask k1.

EVEX.256.66.0F38.W0 2B /r

V/V

AVX512VL

Convert packed signed doubleword integers from ymm2 and

VPACKUSDW ymm1{k1}{z}, ymm2,

AVX512BW

packed signed doubleword integers from

ymm3/m256/m32bcst

ymm3/m256/m32bcst into packed unsigned word integers in

ymm1 using unsigned saturation under writemask k1.

EVEX.512.66.0F38.W0 2B /r

V/V

AVX512BW

Convert packed signed doubleword integers from zmm2 and

VPACKUSDW zmm1{k1}{z}, zmm2,

packed signed doubleword integers from

zmm3/m512/m32bcst

zmm3/m512/m32bcst into packed unsigned word integers in

zmm1 using unsigned saturation under writemask k1.

Instruction Operand Encoding

Op/En

Tuple Type

Operand 1

Operand 2

Operand 3

Operand 4

N/A

ModRM:reg (r, w)

ModRM:r/m (r)

N/A

ModRM:reg (w)

VEX.vvvv (r)

ModRM:r/m (r)

N/A

Full

ModRM:reg (w)

EVEX.vvvv (r)

ModRM:r/m (r)

N/A

Description

Converts packed signed doubleword integers in the first and second source operands into packed unsigned word

integers using unsigned saturation to handle overflow conditions. If the signed doubleword value is beyond the

range of an unsigned word (that is, greater than FFFFH or less than 0000H), the saturated unsigned word integer

value of FFFFH or 0000H, respectively, is stored in the destination.

EVEX encoded versions: The first source operand is a ZMM/YMM/XMM register. The second source operand is a

ZMM/YMM/XMM register, a 512/256/128-bit memory location, or a 512/256/128-bit vector broadcasted from a 32-

bit memory location. The destination operand is a ZMM register, updated conditionally under the writemask k1.

VEX.256 encoded version: The first source operand is a YMM register. The second source operand is a YMM register

or a 256-bit memory location. The destination operand is a YMM register. The upper bits (MAXVL-1:256) of the

corresponding ZMM register destination are zeroed.

VEX.128 encoded version: The first source operand is an XMM register. The second source operand is an XMM

the corresponding ZMM register destination are zeroed.

4-196

Vol. 2B

PACKUSDW-Pack With Unsigned Saturation

INSTRUCTION SET REFERENCE, M-U

128-bit Legacy SSE version: The first source operand is an XMM register. The second operand can be an XMM

upper bits (MAXVL-1:128) of the corresponding destination register destination are unmodified.

Operation

PACKUSDW (Legacy SSE Instruction)

TMP[15:0] := (DEST[31:0] < 0) ? 0 : DEST[15:0];

DEST[15:0] := (DEST[31:0] > FFFFH) ? FFFFH : TMP[15:0] ;

TMP[31:16] := (DEST[63:32] < 0) ? 0 : DEST[47:32];

DEST[31:16] := (DEST[63:32] > FFFFH) ? FFFFH : TMP[31:16] ;

TMP[47:32] := (DEST[95:64] < 0) ? 0 : DEST[79:64];

DEST[47:32] := (DEST[95:64] > FFFFH) ? FFFFH : TMP[47:32] ;

TMP[63:48] := (DEST[127:96] < 0) ? 0 : DEST[111:96];

DEST[63:48] := (DEST[127:96] > FFFFH) ? FFFFH : TMP[63:48] ;

TMP[79:64] := (SRC[31:0] < 0) ? 0 : SRC[15:0];

DEST[79:64] := (SRC[31:0] > FFFFH) ? FFFFH : TMP[79:64] ;

TMP[95:80] := (SRC[63:32] < 0) ? 0 : SRC[47:32];

DEST[95:80] := (SRC[63:32] > FFFFH) ? FFFFH : TMP[95:80] ;

TMP[111:96] := (SRC[95:64] < 0) ? 0 : SRC[79:64];

DEST[111:96] := (SRC[95:64] > FFFFH) ? FFFFH : TMP[111:96] ;

TMP[127:112] := (SRC[127:96] < 0) ? 0 : SRC[111:96];

DEST[127:112] := (SRC[127:96] > FFFFH) ? FFFFH : TMP[127:112] ;

DEST[MAXVL-1:128] (Unmodified)

PACKUSDW (VEX.128 Encoded Version)

TMP[15:0] := (SRC1[31:0] < 0) ? 0 : SRC1[15:0];

DEST[15:0] := (SRC1[31:0] > FFFFH) ? FFFFH : TMP[15:0] ;

TMP[31:16] := (SRC1[63:32] < 0) ? 0 : SRC1[47:32];

DEST[31:16] := (SRC1[63:32] > FFFFH) ? FFFFH : TMP[31:16] ;

TMP[47:32] := (SRC1[95:64] < 0) ? 0 : SRC1[79:64];

DEST[47:32] := (SRC1[95:64] > FFFFH) ? FFFFH : TMP[47:32] ;

TMP[63:48] := (SRC1[127:96] < 0) ? 0 : SRC1[111:96];

DEST[63:48] := (SRC1[127:96] > FFFFH) ? FFFFH : TMP[63:48] ;

TMP[79:64] := (SRC2[31:0] < 0) ? 0 : SRC2[15:0];

DEST[79:64] := (SRC2[31:0] > FFFFH) ? FFFFH : TMP[79:64] ;

TMP[95:80] := (SRC2[63:32] < 0) ? 0 : SRC2[47:32];

DEST[95:80] := (SRC2[63:32] > FFFFH) ? FFFFH : TMP[95:80] ;

TMP[111:96] := (SRC2[95:64] < 0) ? 0 : SRC2[79:64];

DEST[111:96] := (SRC2[95:64] > FFFFH) ? FFFFH : TMP[111:96] ;

TMP[127:112] := (SRC2[127:96] < 0) ? 0 : SRC2[111:96];

DEST[127:112] := (SRC2[127:96] > FFFFH) ? FFFFH : TMP[127:112];

DEST[MAXVL-1:128] := 0;

VPACKUSDW (VEX.256 Encoded Version)

TMP[15:0] := (SRC1[31:0] < 0) ? 0 : SRC1[15:0];

DEST[15:0] := (SRC1[31:0] > FFFFH) ? FFFFH : TMP[15:0] ;

TMP[31:16] := (SRC1[63:32] < 0) ? 0 : SRC1[47:32];

DEST[31:16] := (SRC1[63:32] > FFFFH) ? FFFFH : TMP[31:16] ;

TMP[47:32] := (SRC1[95:64] < 0) ? 0 : SRC1[79:64];

DEST[47:32] := (SRC1[95:64] > FFFFH) ? FFFFH : TMP[47:32] ;

TMP[63:48] := (SRC1[127:96] < 0) ? 0 : SRC1[111:96];

DEST[63:48] := (SRC1[127:96] > FFFFH) ? FFFFH : TMP[63:48] ;

TMP[79:64] := (SRC2[31:0] < 0) ? 0 : SRC2[15:0];

DEST[79:64] := (SRC2[31:0] > FFFFH) ? FFFFH : TMP[79:64] ;

PACKUSDW-Pack With Unsigned Saturation

Vol. 2B

4-197

INSTRUCTION SET REFERENCE, M-U

TMP[95:80] := (SRC2[63:32] < 0) ? 0 : SRC2[47:32];

DEST[95:80] := (SRC2[63:32] > FFFFH) ? FFFFH : TMP[95:80] ;

TMP[111:96] := (SRC2[95:64] < 0) ? 0 : SRC2[79:64];

DEST[111:96] := (SRC2[95:64] > FFFFH) ? FFFFH : TMP[111:96] ;

TMP[127:112] := (SRC2[127:96] < 0) ? 0 : SRC2[111:96];

DEST[127:112] := (SRC2[127:96] > FFFFH) ? FFFFH : TMP[127:112] ;

TMP[143:128] := (SRC1[159:128] < 0) ? 0 : SRC1[143:128];

DEST[143:128] := (SRC1[159:128] > FFFFH) ? FFFFH : TMP[143:128] ;

TMP[159:144] := (SRC1[191:160] < 0) ? 0 : SRC1[175:160];

DEST[159:144] := (SRC1[191:160] > FFFFH) ? FFFFH : TMP[159:144] ;

TMP[175:160] := (SRC1[223:192] < 0) ? 0 : SRC1[207:192];

DEST[175:160] := (SRC1[223:192] > FFFFH) ? FFFFH : TMP[175:160] ;

TMP[191:176] := (SRC1[255:224] < 0) ? 0 : SRC1[239:224];

DEST[191:176] := (SRC1[255:224] > FFFFH) ? FFFFH : TMP[191:176] ;

TMP[207:192] := (SRC2[159:128] < 0) ? 0 : SRC2[143:128];

DEST[207:192] := (SRC2[159:128] > FFFFH) ? FFFFH : TMP[207:192] ;

TMP[223:208] := (SRC2[191:160] < 0) ? 0 : SRC2[175:160];

DEST[223:208] := (SRC2[191:160] > FFFFH) ? FFFFH : TMP[223:208] ;

TMP[239:224] := (SRC2[223:192] < 0) ? 0 : SRC2[207:192];

DEST[239:224] := (SRC2[223:192] > FFFFH) ? FFFFH : TMP[239:224] ;

TMP[255:240] := (SRC2[255:224] < 0) ? 0 : SRC2[239:224];

DEST[255:240] := (SRC2[255:224] > FFFFH) ? FFFFH : TMP[255:240] ;

DEST[MAXVL-1:256] := 0;

VPACKUSDW (EVEX Encoded Versions)

(KL, VL) = (8, 128), (16, 256), (32, 512)

FOR j := 0 TO ((KL/2) - 1)

i := j * 32

IF (EVEX.b == 1) AND (SRC2 *is memory*)

THEN

TMP_SRC2[i+31:i] := SRC2[31:0]

ELSE

TMP_SRC2[i+31:i] := SRC2[i+31:i]

FI;

ENDFOR;

TMP[15:0] := (SRC1[31:0] < 0) ? 0 : SRC1[15:0];

DEST[15:0] := (SRC1[31:0] > FFFFH) ? FFFFH : TMP[15:0] ;

TMP[31:16] := (SRC1[63:32] < 0) ? 0 : SRC1[47:32];

DEST[31:16] := (SRC1[63:32] > FFFFH) ? FFFFH : TMP[31:16] ;

TMP[47:32] := (SRC1[95:64] < 0) ? 0 : SRC1[79:64];

DEST[47:32] := (SRC1[95:64] > FFFFH) ? FFFFH : TMP[47:32] ;

TMP[63:48] := (SRC1[127:96] < 0) ? 0 : SRC1[111:96];

DEST[63:48] := (SRC1[127:96] > FFFFH) ? FFFFH : TMP[63:48] ;

TMP[79:64] := (TMP_SRC2[31:0] < 0) ? 0 : TMP_SRC2[15:0];

DEST[79:64] := (TMP_SRC2[31:0] > FFFFH) ? FFFFH : TMP[79:64] ;

TMP[95:80] := (TMP_SRC2[63:32] < 0) ? 0 : TMP_SRC2[47:32];

DEST[95:80] := (TMP_SRC2[63:32] > FFFFH) ? FFFFH : TMP[95:80] ;

TMP[111:96] := (TMP_SRC2[95:64] < 0) ? 0 : TMP_SRC2[79:64];

DEST[111:96] := (TMP_SRC2[95:64] > FFFFH) ? FFFFH : TMP[111:96] ;

TMP[127:112] := (TMP_SRC2[127:96] < 0) ? 0 : TMP_SRC2[111:96];

DEST[127:112] := (TMP_SRC2[127:96] > FFFFH) ? FFFFH : TMP[127:112] ;

IF VL >= 256

4-198

Vol. 2B

PACKUSDW-Pack With Unsigned Saturation

INSTRUCTION SET REFERENCE, M-U

TMP[143:128] := (SRC1[159:128] < 0) ? 0 : SRC1[143:128];

DEST[143:128] := (SRC1[159:128] > FFFFH) ? FFFFH : TMP[143:128] ;

TMP[159:144] := (SRC1[191:160] < 0) ? 0 : SRC1[175:160];

DEST[159:144] := (SRC1[191:160] > FFFFH) ? FFFFH : TMP[159:144] ;

TMP[175:160] := (SRC1[223:192] < 0) ? 0 : SRC1[207:192];

DEST[175:160] := (SRC1[223:192] > FFFFH) ? FFFFH : TMP[175:160] ;

TMP[191:176] := (SRC1[255:224] < 0) ? 0 : SRC1[239:224];

DEST[191:176] := (SRC1[255:224] > FFFFH) ? FFFFH : TMP[191:176] ;

TMP[207:192] := (TMP_SRC2[159:128] < 0) ? 0 : TMP_SRC2[143:128];

DEST[207:192] := (TMP_SRC2[159:128] > FFFFH) ? FFFFH : TMP[207:192] ;

TMP[223:208] := (TMP_SRC2[191:160] < 0) ? 0 : TMP_SRC2[175:160];

DEST[223:208] := (TMP_SRC2[191:160] > FFFFH) ? FFFFH : TMP[223:208] ;

TMP[239:224] := (TMP_SRC2[223:192] < 0) ? 0 : TMP_SRC2[207:192];

DEST[239:224] := (TMP_SRC2[223:192] > FFFFH) ? FFFFH : TMP[239:224] ;

TMP[255:240] := (TMP_SRC2[255:224] < 0) ? 0 : TMP_SRC2[239:224];

DEST[255:240] := (TMP_SRC2[255:224] > FFFFH) ? FFFFH : TMP[255:240] ;

FI;

IF VL >= 512

TMP[271:256] := (SRC1[287:256] < 0) ? 0 : SRC1[271:256];

DEST[271:256] := (SRC1[287:256] > FFFFH) ? FFFFH : TMP[271:256] ;

TMP[287:272] := (SRC1[319:288] < 0) ? 0 : SRC1[303:288];

DEST[287:272] := (SRC1[319:288] > FFFFH) ? FFFFH : TMP[287:272] ;

TMP[303:288] := (SRC1[351:320] < 0) ? 0 : SRC1[335:320];

DEST[303:288] := (SRC1[351:320] > FFFFH) ? FFFFH : TMP[303:288] ;

TMP[319:304] := (SRC1[383:352] < 0) ? 0 : SRC1[367:352];

DEST[319:304] := (SRC1[383:352] > FFFFH) ? FFFFH : TMP[319:304] ;

TMP[335:320] := (TMP_SRC2[287:256] < 0) ? 0 : TMP_SRC2[271:256];

DEST[335:304] := (TMP_SRC2[287:256] > FFFFH) ? FFFFH : TMP[79:64] ;

TMP[351:336] := (TMP_SRC2[319:288] < 0) ? 0 : TMP_SRC2[303:288];

DEST[351:336] := (TMP_SRC2[319:288] > FFFFH) ? FFFFH : TMP[351:336] ;

TMP[367:352] := (TMP_SRC2[351:320] < 0) ? 0 : TMP_SRC2[315:320];

DEST[367:352] := (TMP_SRC2[351:320] > FFFFH) ? FFFFH : TMP[367:352] ;

TMP[383:368] := (TMP_SRC2[383:352] < 0) ? 0 : TMP_SRC2[367:352];

DEST[383:368] := (TMP_SRC2[383:352] > FFFFH) ? FFFFH : TMP[383:368] ;

TMP[399:384] := (SRC1[415:384] < 0) ? 0 : SRC1[399:384];

DEST[399:384] := (SRC1[415:384] > FFFFH) ? FFFFH : TMP[399:384] ;

TMP[415:400] := (SRC1[447:416] < 0) ? 0 : SRC1[431:416];

DEST[415:400] := (SRC1[447:416] > FFFFH) ? FFFFH : TMP[415:400] ;

TMP[431:416] := (SRC1[479:448] < 0) ? 0 : SRC1[463:448];

DEST[431:416] := (SRC1[479:448] > FFFFH) ? FFFFH : TMP[431:416] ;

TMP[447:432] := (SRC1[511:480] < 0) ? 0 : SRC1[495:480];

DEST[447:432] := (SRC1[511:480] > FFFFH) ? FFFFH : TMP[447:432] ;

TMP[463:448] := (TMP_SRC2[415:384] < 0) ? 0 : TMP_SRC2[399:384];

DEST[463:448] := (TMP_SRC2[415:384] > FFFFH) ? FFFFH : TMP[463:448] ;

TMP[475:464] := (TMP_SRC2[447:416] < 0) ? 0 : TMP_SRC2[431:416];

DEST[475:464] := (TMP_SRC2[447:416] > FFFFH) ? FFFFH : TMP[475:464] ;

TMP[491:476] := (TMP_SRC2[479:448] < 0) ? 0 : TMP_SRC2[463:448];

DEST[491:476] := (TMP_SRC2[479:448] > FFFFH) ? FFFFH : TMP[491:476] ;

TMP[511:492] := (TMP_SRC2[511:480] < 0) ? 0 : TMP_SRC2[495:480];

DEST[511:492] := (TMP_SRC2[511:480] > FFFFH) ? FFFFH : TMP[511:492] ;

FI;

FOR j := 0 TO KL-1

i := j * 16

IF k1[j] OR *no writemask*

PACKUSDW-Pack With Unsigned Saturation

Vol. 2B

4-199

INSTRUCTION SET REFERENCE, M-U

THEN

DEST[i+15:i] := TMP_DEST[i+15:i]

ELSE

IF *merging-masking*

; merging-masking

THEN *DEST[i+15:i] remains unchanged*

ELSE *zeroing-masking*

; zeroing-masking

DEST[i+15:i] := 0

FI;

ENDFOR;

DEST[MAXVL-1:VL] := 0

Intel C/C++ Compiler Intrinsic Equivalents

VPACKUSDW__m512i _mm512_packus_epi32(__m512i m1, __m512i m2);

VPACKUSDW__m512i _mm512_mask_packus_epi32(__m512i s, __mmask32 k, __m512i m1, __m512i m2);

VPACKUSDW__m512i _mm512_maskz_packus_epi32( __mmask32 k, __m512i m1, __m512i m2);

VPACKUSDW__m256i _mm256_mask_packus_epi32( __m256i s, __mmask16 k, __m256i m1, __m256i m2);

VPACKUSDW__m256i _mm256_maskz_packus_epi32( __mmask16 k, __m256i m1, __m256i m2);

VPACKUSDW__m128i _mm_mask_packus_epi32( __m128i s, __mmask8 k, __m128i m1, __m128i m2);

VPACKUSDW__m128i _mm_maskz_packus_epi32( __mmask8 k, __m128i m1, __m128i m2);

PACKUSDW__m128i _mm_packus_epi32(__m128i m1, __m128i m2);

VPACKUSDW__m256i _mm256_packus_epi32(__m256i m1, __m256i m2);

SIMD Floating-Point Exceptions

None.

Other Exceptions

Non-EVEX-encoded instruction, see Table 2-21, “Type 4 Class Exception Conditions.”

EVEX-encoded instruction, see Table 2-50, “Type E4NF Class Exception Conditions.”

4-200

Vol. 2B

PACKUSDW-Pack With Unsigned Saturation

INSTRUCTION SET REFERENCE, M-U

PACKUSWB-Pack With Unsigned Saturation

Opcode/

Op/

64/32 bit

CPUID

Description

Instruction

Mode

Feature Flag

Support

NP 0F 67 /r¹

V/V

MMX

Converts 4 signed word integers from mm and

4 signed word integers from mm/m64 into 8

PACKUSWB mm, mm/m64

unsigned byte integers in mm using unsigned

saturation.

66 0F 67 /r

V/V

SSE2

Converts 8 signed word integers from xmm1

and 8 signed word integers from xmm2/m128

PACKUSWB xmm1, xmm2/m128

into 16 unsigned byte integers in xmm1 using

unsigned saturation.

VEX.128.66.0F.WIG 67 /r

V/V

AVX

Converts 8 signed word integers from xmm2

and 8 signed word integers from xmm3/m128

VPACKUSWB xmm1, xmm2, xmm3/m128

into 16 unsigned byte integers in xmm1 using

unsigned saturation.

VEX.256.66.0F.WIG 67 /r

V/V

AVX2

Converts 16 signed word integers from ymm2

and 16signed word integers from ymm3/m256

VPACKUSWB ymm1, ymm2, ymm3/m256

into 32 unsigned byte integers in ymm1 using

unsigned saturation.

EVEX.128.66.0F.WIG 67 /r

V/V

AVX512VL

Converts signed word integers from xmm2 and

VPACKUSWB xmm1{k1}{z}, xmm2, xmm3/m128

AVX512BW

signed word integers from xmm3/m128 into

unsigned byte integers in xmm1 using unsigned

saturation under writemask k1.

EVEX.256.66.0F.WIG 67 /r

V/V

AVX512VL

Converts signed word integers from ymm2 and

VPACKUSWB ymm1{k1}{z}, ymm2, ymm3/m256

AVX512BW

signed word integers from ymm3/m256 into

unsigned byte integers in ymm1 using unsigned

saturation under writemask k1.

EVEX.512.66.0F.WIG 67 /r

V/V

AVX512BW

Converts signed word integers from zmm2 and

VPACKUSWB zmm1{k1}{z}, zmm2, zmm3/m512

signed word integers from zmm3/m512 into

unsigned byte integers in zmm1 using unsigned

saturation under writemask k1.

NOTES:

1. See note in Section 2.5, “Intel® AVX and Intel® SSE Instruction Exception Classification,” in the Intel^® 64 and IA-32 Architectures Soft-

ware Developer’s Manual, Volume 2A, and Section 23.25.3, “Exception Conditions of Legacy SIMD Instructions Operating on MMX

Registers,” in the Intel^® 64 and IA-32 Architectures Software Developer’s Manual, Volume 3B.

Instruction Operand Encoding

Op/En

Tuple Type

Operand 1

Operand 2

Operand 3

Operand 4

N/A

ModRM:reg (r, w)

ModRM:r/m (r)

N/A

ModRM:reg (w)

VEX.vvvv (r)

ModRM:r/m (r)

N/A

Full Mem

ModRM:reg (w)

EVEX.vvvv (r)

ModRM:r/m (r)

N/A

Description

Converts 4, 8, 16, or 32 signed word integers from the destination operand (first operand) and 4, 8, 16, or 32

signed word integers from the source operand (second operand) into 8, 16, 32 or 64 unsigned byte integers and

stores the result in the destination operand. (See Figure 4-6 for an example of the packing operation.) If a signed

word integer value is beyond the range of an unsigned byte integer (that is, greater than FFH or less than 00H), the

saturated unsigned byte integer value of FFH or 00H, respectively, is stored in the destination.

EVEX.512 encoded version: The first source operand is a ZMM register. The second source operand is a ZMM

PACKUSWB-Pack With Unsigned Saturation

Vol. 2B

4-201

INSTRUCTION SET REFERENCE, M-U

VEX.256 and EVEX.256 encoded versions: The first source operand is a YMM register. The second source operand

is a YMM register or a 256-bit memory location. The destination operand is a YMM register. The upper bits (MAXVL-

1:256) of the corresponding ZMM register destination are zeroed.

VEX.128 and EVEX.128 encoded versions: The first source operand is an XMM register. The second source operand

is an XMM register or 128-bit memory location. The destination operand is an XMM register. The upper bits (MAXVL-

1:128) of the corresponding register destination are zeroed.

128-bit Legacy SSE version: The first source operand is an XMM register. The second operand can be an XMM

upper bits (MAXVL-1:128) of the corresponding register destination are unmodified.

Operation

PACKUSWB (With 64-bit Operands)

DEST[7:0] := SaturateSignedWordToUnsignedByte DEST[15:0];

DEST[15:8] := SaturateSignedWordToUnsignedByte DEST[31:16];

DEST[23:16] := SaturateSignedWordToUnsignedByte DEST[47:32];

DEST[31:24] := SaturateSignedWordToUnsignedByte DEST[63:48];

DEST[39:32] := SaturateSignedWordToUnsignedByte SRC[15:0];

DEST[47:40] := SaturateSignedWordToUnsignedByte SRC[31:16];

DEST[55:48] := SaturateSignedWordToUnsignedByte SRC[47:32];

DEST[63:56] := SaturateSignedWordToUnsignedByte SRC[63:48];

PACKUSWB (Legacy SSE Instruction)

DEST[7:0] := SaturateSignedWordToUnsignedByte (DEST[15:0]);

DEST[15:8] := SaturateSignedWordToUnsignedByte (DEST[31:16]);

DEST[23:16] := SaturateSignedWordToUnsignedByte (DEST[47:32]);

DEST[31:24] := SaturateSignedWordToUnsignedByte (DEST[63:48]);

DEST[39:32] := SaturateSignedWordToUnsignedByte (DEST[79:64]);

DEST[47:40] := SaturateSignedWordToUnsignedByte (DEST[95:80]);

DEST[55:48] := SaturateSignedWordToUnsignedByte (DEST[111:96]);

DEST[63:56] := SaturateSignedWordToUnsignedByte (DEST[127:112]);

DEST[71:64] := SaturateSignedWordToUnsignedByte (SRC[15:0]);

DEST[79:72] := SaturateSignedWordToUnsignedByte (SRC[31:16]);

DEST[87:80] := SaturateSignedWordToUnsignedByte (SRC[47:32]);

DEST[95:88] := SaturateSignedWordToUnsignedByte (SRC[63:48]);

DEST[103:96] := SaturateSignedWordToUnsignedByte (SRC[79:64]);

DEST[111:104] := SaturateSignedWordToUnsignedByte (SRC[95:80]);

DEST[119:112] := SaturateSignedWordToUnsignedByte (SRC[111:96]);

DEST[127:120] := SaturateSignedWordToUnsignedByte (SRC[127:112]);

PACKUSWB (VEX.128 Encoded Version)

DEST[7:0] := SaturateSignedWordToUnsignedByte (SRC1[15:0]);

DEST[15:8] := SaturateSignedWordToUnsignedByte (SRC1[31:16]);

DEST[23:16] := SaturateSignedWordToUnsignedByte (SRC1[47:32]);

DEST[31:24] := SaturateSignedWordToUnsignedByte (SRC1[63:48]);

DEST[39:32] := SaturateSignedWordToUnsignedByte (SRC1[79:64]);

DEST[47:40] := SaturateSignedWordToUnsignedByte (SRC1[95:80]);

DEST[55:48] := SaturateSignedWordToUnsignedByte (SRC1[111:96]);

DEST[63:56] := SaturateSignedWordToUnsignedByte (SRC1[127:112]);

DEST[71:64] := SaturateSignedWordToUnsignedByte (SRC2[15:0]);

DEST[79:72] := SaturateSignedWordToUnsignedByte (SRC2[31:16]);

DEST[87:80] := SaturateSignedWordToUnsignedByte (SRC2[47:32]);

DEST[95:88] := SaturateSignedWordToUnsignedByte (SRC2[63:48]);

DEST[103:96] := SaturateSignedWordToUnsignedByte (SRC2[79:64]);

DEST[111:104] := SaturateSignedWordToUnsignedByte (SRC2[95:80]);

4-202

Vol. 2B

PACKUSWB-Pack With Unsigned Saturation

INSTRUCTION SET REFERENCE, M-U

DEST[119:112] := SaturateSignedWordToUnsignedByte (SRC2[111:96]);

DEST[127:120] := SaturateSignedWordToUnsignedByte (SRC2[127:112]);

DEST[MAXVL-1:128] := 0;

VPACKUSWB (VEX.256 Encoded Version)