Intel 64 and IA-32 Architectures. Software Developer’s Manual (Collection, 2023)

INSTRUCTION SET REFERENCE, A-L

INPUT EAX = 07H: Returns Structured Extended Feature Enumeration Information

When CPUID executes with EAX set to 07H and ECX = 0, the processor returns information about the maximum

input value for sub-leaves that contain extended feature flags. See Table 3-8.

When CPUID executes with EAX set to 07H and the input value of ECX is invalid (see leaf 07H entry in Table 3-8),

the processor returns 0 in EAX/EBX/ECX/EDX. In subleaf 0, EAX returns the maximum input value of the highest

leaf 7 sub-leaf, and EBX, ECX & EDX contain information of extended feature flags.

INPUT EAX = 09H: Returns Direct Cache Access Information

When CPUID executes with EAX set to 09H, the processor returns information about Direct Cache Access capabili-

ties. See Table 3-8.

INPUT EAX = 0AH: Returns Architectural Performance Monitoring Features

When CPUID executes with EAX set to 0AH, the processor returns information about support for architectural

performance monitoring capabilities. Architectural performance monitoring is supported if the version ID (see

Table 3-8) is greater than Pn 0. See Table 3-8.

For each version of architectural performance monitoring capability, software must enumerate this leaf to discover

the programming facilities and the architectural performance events available in the processor. The details are

described in Chapter 24, “Introduction to Virtual Machine Extensions,” in the Intel^® 64 and IA-32 Architectures

Software Developer’s Manual, Volume 3C.

INPUT EAX = 0BH: Returns Extended Topology Information

CPUID leaf 1FH is a preferred superset to leaf 0BH. Intel recommends first checking for the existence of Leaf 1FH

before using leaf 0BH.

When CPUID executes with EAX set to 0BH, the processor returns information about extended topology enumera-

tion data. Software must detect the presence of CPUID leaf 0BH by verifying (a) the highest leaf index supported

by CPUID is >= 0BH, and (b) CPUID.0BH:EBX[15:0] reports a non-zero value. See Table 3-8.

INPUT EAX = 0DH: Returns Processor Extended States Enumeration Information

When CPUID executes with EAX set to 0DH and ECX = 0, the processor returns information about the bit-vector

representation of all processor state extensions that are supported in the processor and storage size requirements

of the XSAVE/XRSTOR area. See Table 3-8.

When CPUID executes with EAX set to 0DH and ECX = n (n > 1, and is a valid sub-leaf index), the processor returns

information about the size and offset of each processor extended state save area within the XSAVE/XRSTOR area.

See Table 3-8. Software can use the forward-extendable technique depicted below to query the valid sub-leaves

and obtain size and offset information for each processor extended state save area:

For i = 2 to 62 // sub-leaf 1 is reserved

IF (CPUID.(EAX=0DH, ECX=0):VECTOR[i] = 1 ) // VECTOR is the 64-bit value of EDX:EAX

Execute CPUID.(EAX=0DH, ECX = i) to examine size and offset for sub-leaf i;

FI;

INPUT EAX = 0FH: Returns Intel Resource Director Technology (Intel RDT) Monitoring Enumeration Information

When CPUID executes with EAX set to 0FH and ECX = 0, the processor returns information about the bit-vector

representation of QoS monitoring resource types that are supported in the processor and maximum range of RMID

values the processor can use to monitor of any supported resource types. Each bit, starting from bit 1, corresponds

to a specific resource type if the bit is set. The bit position corresponds to the sub-leaf index (or ResID) that soft-

ware must use to query QoS monitoring capability available for that type. See Table 3-8.

When CPUID executes with EAX set to 0FH and ECX = n (n >= 1, and is a valid ResID), the processor returns infor-

mation software can use to program IA32_PQR_ASSOC, IA32_QM_EVTSEL MSRs before reading QoS data from the

IA32_QM_CTR MSR.

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INSTRUCTION SET REFERENCE, A-L

INPUT EAX = 10H: Returns Intel Resource Director Technology (Intel RDT) Allocation Enumeration Information

When CPUID executes with EAX set to 10H and ECX = 0, the processor returns information about the bit-vector

representation of QoS Enforcement resource types that are supported in the processor. Each bit, starting from bit

1, corresponds to a specific resource type if the bit is set. The bit position corresponds to the sub-leaf index (or

ResID) that software must use to query QoS enforcement capability available for that type. See Table 3-8.

When CPUID executes with EAX set to 10H and ECX = n (n >= 1, and is a valid ResID), the processor returns infor-

mation about available classes of service and range of QoS mask MSRs that software can use to configure each

class of services using capability bit masks in the QoS Mask registers, IA32_resourceType_Mask_n.

INPUT EAX = 12H: Returns Intel SGX Enumeration Information

When CPUID executes with EAX set to 12H and ECX = 0H, the processor returns information about Intel SGX capa-

bilities. See Table 3-8.

When CPUID executes with EAX set to 12H and ECX = 1H, the processor returns information about Intel SGX attri-

butes. See Table 3-8.

When CPUID executes with EAX set to 12H and ECX = n (n > 1), the processor returns information about Intel SGX

Enclave Page Cache. See Table 3-8.

INPUT EAX = 14H: Returns Intel Processor Trace Enumeration Information

When CPUID executes with EAX set to 14H and ECX = 0H, the processor returns information about Intel Processor

Trace extensions. See Table 3-8.

When CPUID executes with EAX set to 14H and ECX = n (n > 0 and less than the number of non-zero bits in

CPUID.(EAX=14H, ECX= 0H).EAX), the processor returns information about packet generation in Intel Processor

Trace. See Table 3-8.

INPUT EAX = 15H: Returns Time Stamp Counter and Nominal Core Crystal Clock Information

When CPUID executes with EAX set to 15H and ECX = 0H, the processor returns information about Time Stamp

Counter and Core Crystal Clock. See Table 3-8.

INPUT EAX = 16H: Returns Processor Frequency Information

When CPUID executes with EAX set to 16H, the processor returns information about Processor Frequency Informa-

tion. See Table 3-8.

INPUT EAX = 17H: Returns System-On-Chip Information

When CPUID executes with EAX set to 17H, the processor returns information about the System-On-Chip Vendor

Attribute Enumeration. See Table 3-8.

INPUT EAX = 18H: Returns Deterministic Address Translation Parameters Information

When CPUID executes with EAX set to 18H, the processor returns information about the Deterministic Address

Translation Parameters. See Table 3-8.

INPUT EAX = 19H: Returns Key Locker Information

When CPUID executes with EAX set to 19H, the processor returns information about Key Locker. See Table 3-8.

INPUT EAX = 1AH: Returns Native Model ID Information

When CPUID executes with EAX set to 1AH, the processor returns information about Native Model Identification.

See Table 3-8.

INPUT EAX = 1BH: Returns PCONFIG Information

When CPUID executes with EAX set to 1BH, the processor returns information about PCONFIG capabilities. This

information is enumerated in sub-leaves selected by the value of ECX (starting with 0).

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INSTRUCTION SET REFERENCE, A-L

Each sub-leaf of CPUID function 1BH enumerates its sub-leaf type in EAX. If a sub-leaf type is 0, the sub-leaf is

invalid and zero is returned in EBX, ECX, and EDX. In this case, all subsequent sub-leaves (selected by larger input

values of ECX) are also invalid.

The only valid sub-leaf type currently defined is 1, indicating that the sub-leaf enumerates target identifiers for the

PCONFIG instruction. Any non-zero value returned in EBX, ECX, or EDX indicates a valid target identifier of the

PCONFIG instruction (any value of zero should be ignored). The only target identifier currently defined is 1, indi-

cating TME-MK. See the “If VEX.vvvv ≠ 1111B.” instruction in Chapter 4 of the Intel^® 64 and IA-32 Architectures

Software Developer’s Manual, Volume 2B, for more information.

INPUT EAX = 1CH: Returns Last Branch Record Information

When CPUID executes with EAX set to 1CH, the processor returns information about LBRs (the architectural

feature). See Table 3-8.

INPUT EAX = 1DH: Returns Tile Information

When CPUID executes with EAX set to 1DH and ECX = 0H, the processor returns information about tile

architecture. See Table 3-8.

When CPUID executes with EAX set to 1DH and ECX = 1H, the processor returns information about tile palette 1.

See Table 3-8.

INPUT EAX = 1EH: Returns TMUL Information

When CPUID executes with EAX set to 1EH and ECX = 0H, the processor returns information about TMUL

capabilities. See Table 3-8.

INPUT EAX = 1FH: Returns V2 Extended Topology Information

When CPUID executes with EAX set to 1FH, the processor returns information about extended topology enumera-

tion data. Software must detect the presence of CPUID leaf 1FH by verifying (a) the highest leaf index supported

by CPUID is >= 1FH, and (b) CPUID.1FH:EBX[15:0] reports a non-zero value. See Table 3-8.

INPUT EAX = 20H: Returns History Reset Information

When CPUID executes with EAX set to 20H, the processor returns information about History Reset. See Table 3-8.

METHODS FOR RETURNING BRANDING INFORMATION

Use the following techniques to access branding information:

1. Processor brand string method.

2. Processor brand index; this method uses a software supplied brand string table.

These two methods are discussed in the following sections. For methods that are available in early processors, see

Section: “Identification of Earlier IA-32 Processors” in Chapter 20 of the Intel^® 64 and IA-32 Architectures Soft-

ware Developer’s Manual, Volume 1.

The Processor Brand String Method

Figure 3-9 describes the algorithm used for detection of the brand string. Processor brand identification software

should execute this algorithm on all Intel 64 and IA-32 processors.

This method (introduced with Pentium 4 processors) returns an ASCII brand identification string and the Processor

Base frequency of the processor to the EAX, EBX, ECX, and EDX registers.

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INSTRUCTION SET REFERENCE, A-L

Input: EAX=

0x80000000

CPUID

False

Processor Brand

IF (EAX & 0x80000000)

String Not

Supported

CPUID

True ≥

Function

Extended

Supported

EAX Return Value =

Max. Extended CPUID

Function Index

True

IF (EAX Return Value

Processor Brand

String Supported

≥ 0x80000004)

OM15194

Figure 3-9. Determination of Support for the Processor Brand String

How Brand Strings Work

To use the brand string method, execute CPUID with EAX input of 8000002H through 80000004H. For each input

value, CPUID returns 16 ASCII characters using EAX, EBX, ECX, and EDX. The returned string will be NULL-termi-

nated.

Table 3-13 shows the brand string that is returned by the first processor in the Pentium 4 processor family.

Table 3-13. Processor Brand String Returned with Pentium 4 Processor

EAX Input Value

Return Values

ASCII Equivalent

80000002H

EAX = 20202020H

“

”

EBX = 20202020H

“

”

ECX = 20202020H

“

”

EDX = 6E492020H

“nI ”

80000003H

EAX = 286C6574H

“(let”

EBX = 50202952H

“P )R”

ECX = 69746E65H

“itne”

EDX = 52286D75H

“R(mu”

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INSTRUCTION SET REFERENCE, A-L

Table 3-13. Processor Brand String Returned with Pentium 4 Processor (Contd.)

EAX Input Value

Return Values

ASCII Equivalent

80000004H

EAX = 20342029H

“ 4 )”

EBX = 20555043H

“ UPC”

ECX = 30303531H

“0051”

EDX = 007A484DH

“\0zHM”

Extracting the Processor Frequency from Brand Strings

Figure 3-10 provides an algorithm which software can use to extract the Processor Base frequency from the

processor brand string.

Scan "Brand String" in

Reverse Byte Order

"zHM", or

Match

"zHG", or

Substring

"zHT"

False

IF Substring Matched

Report Error

Determine "Freq"

If "zHM"

True

and "Multiplier"

Multiplier = 1 x 10⁶

If "zHG"

Multiplier = 1 x 10⁹

Determine "Multiplier"

If "zHT"

Multiplier = 1 x 10¹²

Scan Digits

Until Blank

Reverse Digits

Determine "Freq"

In Reverse Order

To Decimal Value

Processor Base

Frequency =

"Freq" = X.YZ if

"Freq" x "Multiplier"

Digits = "ZY.X"

Figure 3-10. Algorithm for Extracting Processor Frequency

The Processor Brand Index Method

The brand index method (introduced with Pentium^® III Xeon^® processors) provides an entry point into a brand

identification table that is maintained in memory by system software and is accessible from system- and user-level

code. In this table, each brand index is associate with an ASCII brand identification string that identifies the official

Intel family and model number of a processor.

When CPUID executes with EAX set to 1, the processor returns a brand index to the low byte in EBX. Software can

then use this index to locate the brand identification string for the processor in the brand identification table. The

first entry (brand index 0) in this table is reserved, allowing for backward compatibility with processors that do not

support the brand identification feature. Starting with processor signature family ID = 0FH, model = 03H, brand

index method is no longer supported. Use brand string method instead.

Table 3-14 shows brand indices that have identification strings associated with them.

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INSTRUCTION SET REFERENCE, A-L

Table 3-14. Mapping of Brand Indices; and Intel 64 and IA-32 Processor Brand Strings

Brand Index

Brand String

00H

This processor does not support the brand identification feature

01H

Intel(R) Celeron(R) processor¹

02H

Intel(R) Pentium(R) III processor¹

03H

Intel(R) Pentium(R) III Xeon(R) processor; If processor signature = 000006B1h, then Intel(R) Celeron(R)

processor

04H

Intel(R) Pentium(R) III processor

06H

Mobile Intel(R) Pentium(R) III processor-M

07H

Mobile Intel(R) Celeron(R) processor¹

08H

Intel(R) Pentium(R) 4 processor

09H

Intel(R) Pentium(R) 4 processor

0AH

Intel(R) Celeron(R) processor¹

0BH

Intel(R) Xeon(R) processor; If processor signature = 00000F13h, then Intel(R) Xeon(R) processor MP

0CH

Intel(R) Xeon(R) processor MP

0EH

Mobile Intel(R) Pentium(R) 4 processor-M; If processor signature = 00000F13h, then Intel(R) Xeon(R) processor

0FH

Mobile Intel(R) Celeron(R) processor¹

11H

Mobile Genuine Intel(R) processor

12H

Intel(R) Celeron(R) M processor

13H

Mobile Intel(R) Celeron(R) processor¹

14H

Intel(R) Celeron(R) processor

15H

Mobile Genuine Intel(R) processor

16H

Intel(R) Pentium(R) M processor

17H

Mobile Intel(R) Celeron(R) processor¹

18H - 0FFH

RESERVED

NOTES:

1. Indicates versions of these processors that were introduced after the Pentium III

IA-32 Architecture Compatibility

CPUID is not supported in early models of the Intel486 processor or in any IA-32 processor earlier than the

Intel486 processor.

Operation

IA32_BIOS_SIGN_ID MSR := Update with installed microcode revision number;

CASE (EAX) OF

EAX = 0:

EAX := Highest basic function input value understood by CPUID;

EBX := Vendor identification string;

EDX := Vendor identification string;

ECX := Vendor identification string;

BREAK;

EAX = 1H:

EAX[3:0] := Stepping ID;

EAX[7:4] := Model;

EAX[11:8] := Family;

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INSTRUCTION SET REFERENCE, A-L

EAX[13:12] := Processor type;

EAX[15:14] := Reserved;

EAX[19:16] := Extended Model;

EAX[27:20] := Extended Family;

EAX[31:28] := Reserved;

EBX[7:0] := Brand Index; (* Reserved if the value is zero. *)

EBX[15:8] := CLFLUSH Line Size;

EBX[16:23] := Reserved; (* Number of threads enabled = 2 if MT enable fuse set. *)

EBX[24:31] := Initial APIC ID;

ECX := Feature flags; (* See Figure 3-7. *)

EDX := Feature flags; (* See Figure 3-8. *)

BREAK;

EAX = 2H:

EAX := Cache and TLB information;

EBX := Cache and TLB information;

ECX := Cache and TLB information;

EDX := Cache and TLB information;

BREAK;

EAX = 3H:

EAX := Reserved;

EBX := Reserved;

ECX := ProcessorSerialNumber[31:0];

(* Pentium III processors only, otherwise reserved. *)

EDX := ProcessorSerialNumber[63:32];

(* Pentium III processors only, otherwise reserved. *

BREAK

EAX = 4H:

EAX := Deterministic Cache Parameters Leaf; (* See Table 3-8. *)

EBX := Deterministic Cache Parameters Leaf;

ECX := Deterministic Cache Parameters Leaf;

EDX := Deterministic Cache Parameters Leaf;

BREAK;

EAX = 5H:

EAX := MONITOR/MWAIT Leaf; (* See Table 3-8. *)

EBX := MONITOR/MWAIT Leaf;

ECX := MONITOR/MWAIT Leaf;

EDX := MONITOR/MWAIT Leaf;

BREAK;

EAX = 6H:

EAX := Thermal and Power Management Leaf; (* See Table 3-8. *)

EBX := Thermal and Power Management Leaf;

ECX := Thermal and Power Management Leaf;

EDX := Thermal and Power Management Leaf;

BREAK;

EAX = 7H:

EAX := Structured Extended Feature Flags Enumeration Leaf; (* See Table 3-8. *)

EBX := Structured Extended Feature Flags Enumeration Leaf;

ECX := Structured Extended Feature Flags Enumeration Leaf;

EDX := Structured Extended Feature Flags Enumeration Leaf;

BREAK;

EAX = 8H:

EAX := Reserved = 0;

EBX := Reserved = 0;

ECX := Reserved = 0;

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INSTRUCTION SET REFERENCE, A-L

EDX := Reserved = 0;

BREAK;

EAX = 9H:

EAX := Direct Cache Access Information Leaf; (* See Table 3-8. *)

EBX := Direct Cache Access Information Leaf;

ECX := Direct Cache Access Information Leaf;

EDX := Direct Cache Access Information Leaf;

BREAK;

EAX = AH:

EAX := Architectural Performance Monitoring Leaf; (* See Table 3-8. *)

EBX := Architectural Performance Monitoring Leaf;

ECX := Architectural Performance Monitoring Leaf;

EDX := Architectural Performance Monitoring Leaf;

BREAK

EAX = BH:

EAX := Extended Topology Enumeration Leaf; (* See Table 3-8. *)

EBX := Extended Topology Enumeration Leaf;

ECX := Extended Topology Enumeration Leaf;

EDX := Extended Topology Enumeration Leaf;

BREAK;

EAX = CH:

EAX := Reserved = 0;

EBX := Reserved = 0;

ECX := Reserved = 0;

EDX := Reserved = 0;

BREAK;

EAX = DH:

EAX := Processor Extended State Enumeration Leaf; (* See Table 3-8. *)

EBX := Processor Extended State Enumeration Leaf;

ECX := Processor Extended State Enumeration Leaf;

EDX := Processor Extended State Enumeration Leaf;

BREAK;

EAX = EH:

EAX := Reserved = 0;

EBX := Reserved = 0;

ECX := Reserved = 0;

EDX := Reserved = 0;

BREAK;

EAX = FH:

EAX := Intel Resource Director Technology Monitoring Enumeration Leaf; (* See Table 3-8. *)

EBX := Intel Resource Director Technology Monitoring Enumeration Leaf;

ECX := Intel Resource Director Technology Monitoring Enumeration Leaf;

EDX := Intel Resource Director Technology Monitoring Enumeration Leaf;

BREAK;

EAX = 10H:

EAX := Intel Resource Director Technology Allocation Enumeration Leaf; (* See Table 3-8. *)

EBX := Intel Resource Director Technology Allocation Enumeration Leaf;

ECX := Intel Resource Director Technology Allocation Enumeration Leaf;

EDX := Intel Resource Director Technology Allocation Enumeration Leaf;

BREAK;

EAX = 12H:

EAX := Intel SGX Enumeration Leaf; (* See Table 3-8. *)

EBX := Intel SGX Enumeration Leaf;

ECX := Intel SGX Enumeration Leaf;

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INSTRUCTION SET REFERENCE, A-L

EDX := Intel SGX Enumeration Leaf;

BREAK;

EAX = 14H:

EAX := Intel Processor Trace Enumeration Leaf; (* See Table 3-8. *)

EBX := Intel Processor Trace Enumeration Leaf;

ECX := Intel Processor Trace Enumeration Leaf;

EDX := Intel Processor Trace Enumeration Leaf;

BREAK;

EAX = 15H:

EAX := Time Stamp Counter and Nominal Core Crystal Clock Information Leaf; (* See Table 3-8. *)

EBX := Time Stamp Counter and Nominal Core Crystal Clock Information Leaf;

ECX := Time Stamp Counter and Nominal Core Crystal Clock Information Leaf;

EDX := Time Stamp Counter and Nominal Core Crystal Clock Information Leaf;

BREAK;

EAX = 16H:

EAX := Processor Frequency Information Enumeration Leaf; (* See Table 3-8. *)

EBX := Processor Frequency Information Enumeration Leaf;

ECX := Processor Frequency Information Enumeration Leaf;

EDX := Processor Frequency Information Enumeration Leaf;

BREAK;

EAX = 17H:

EAX := System-On-Chip Vendor Attribute Enumeration Leaf; (* See Table 3-8. *)

EBX := System-On-Chip Vendor Attribute Enumeration Leaf;

ECX := System-On-Chip Vendor Attribute Enumeration Leaf;

EDX := System-On-Chip Vendor Attribute Enumeration Leaf;

BREAK;

EAX = 18H:

EAX := Deterministic Address Translation Parameters Enumeration Leaf; (* See Table 3-8. *)

EBX := Deterministic Address Translation Parameters Enumeration Leaf;

ECX := Deterministic Address Translation Parameters Enumeration Leaf;

EDX := Deterministic Address Translation Parameters Enumeration Leaf;

BREAK;

EAX = 19H:

EAX := Key Locker Enumeration Leaf; (* See Table 3-8. *)

EBX := Key Locker Enumeration Leaf;

ECX := Key Locker Enumeration Leaf;

EDX := Key Locker Enumeration Leaf;

BREAK;

EAX = 1AH:

EAX := Native Model ID Enumeration Leaf; (* See Table 3-8. *)

EBX := Native Model ID Enumeration Leaf;

ECX := Native Model ID Enumeration Leaf;

EDX := Native Model ID Enumeration Leaf;

BREAK;

EAX = 1BH:

EAX := PCONFIG Information Enumeration Leaf; (* See “INPUT EAX = 1BH: Returns PCONFIG Information” on page 3-252. *)

EBX := PCONFIG Information Enumeration Leaf;

ECX := PCONFIG Information Enumeration Leaf;

EDX := PCONFIG Information Enumeration Leaf;

BREAK;

EAX = 1CH:

EAX := Last Branch Record Information Enumeration Leaf; (* See Table 3-8. *)

EBX := Last Branch Record Information Enumeration Leaf;

ECX := Last Branch Record Information Enumeration Leaf;

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INSTRUCTION SET REFERENCE, A-L

EDX := Last Branch Record Information Enumeration Leaf;

BREAK;

EAX = 1DH:

EAX := Tile Information Enumeration Leaf; (* See Table 3-8. *)

EBX := Tile Information Enumeration Leaf;

ECX := Tile Information Enumeration Leaf;

EDX := Tile Information Enumeration Leaf;

BREAK;

EAX = 1EH:

EAX := TMUL Information Enumeration Leaf; (* See Table 3-8. *)

EBX := TMUL Information Enumeration Leaf;

ECX := TMUL Information Enumeration Leaf;

EDX := TMUL Information Enumeration Leaf;

BREAK;

EAX = 1FH:

EAX := V2 Extended Topology Enumeration Leaf; (* See Table 3-8. *)

EBX := V2 Extended Topology Enumeration Leaf;

ECX := V2 Extended Topology Enumeration Leaf;

EDX := V2 Extended Topology Enumeration Leaf;

BREAK;

EAX = 20H:

EAX := Processor History Reset Sub-leaf; (* See Table 3-8. *)

EBX := Processor History Reset Sub-leaf;

ECX := Processor History Reset Sub-leaf;

EDX := Processor History Reset Sub-leaf;

BREAK;

EAX = 80000000H:

EAX := Highest extended function input value understood by CPUID;

EBX := Reserved;

ECX := Reserved;

EDX := Reserved;

BREAK;

EAX = 80000001H:

EAX := Reserved;

EBX := Reserved;

ECX := Extended Feature Bits (* See Table 3-8.*);

EDX := Extended Feature Bits (* See Table 3-8. *);

BREAK;

EAX = 80000002H:

EAX := Processor Brand String;

EBX := Processor Brand String, continued;

ECX := Processor Brand String, continued;

EDX := Processor Brand String, continued;

BREAK;

EAX = 80000003H:

EAX := Processor Brand String, continued;

EBX := Processor Brand String, continued;

ECX := Processor Brand String, continued;

EDX := Processor Brand String, continued;

BREAK;

EAX = 80000004H:

EAX := Processor Brand String, continued;

EBX := Processor Brand String, continued;

ECX := Processor Brand String, continued;

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INSTRUCTION SET REFERENCE, A-L

EDX := Processor Brand String, continued;

BREAK;

EAX = 80000005H:

EAX := Reserved = 0;

EBX := Reserved = 0;

ECX := Reserved = 0;

EDX := Reserved = 0;

BREAK;

EAX = 80000006H:

EAX := Reserved = 0;

EBX := Reserved = 0;

ECX := Cache information;

EDX := Reserved = 0;

BREAK;

EAX = 80000007H:

EAX := Reserved = 0;

EBX := Reserved = 0;

ECX := Reserved = 0;

EDX := Reserved = Misc Feature Flags;

BREAK;

EAX = 80000008H:

EAX := Address Size Information;

EBX := Misc Feature Flags;

ECX := Reserved = 0;

EDX := Reserved = 0;

BREAK;

EAX >= 40000000H and EAX <= 4FFFFFFFH:

DEFAULT: (* EAX = Value outside of recognized range for CPUID. *)

(* If the highest basic information leaf data depend on ECX input value, ECX is honored.*)

EAX := Reserved; (* Information returned for highest basic information leaf. *)

EBX := Reserved; (* Information returned for highest basic information leaf. *)

ECX := Reserved; (* Information returned for highest basic information leaf. *)

EDX := Reserved; (* Information returned for highest basic information leaf. *)

BREAK;

ESAC;

Flags Affected

None.

Exceptions (All Operating Modes)

#UD

If the LOCK prefix is used.

In earlier IA-32 processors that do not support the CPUID instruction, execution of the instruc-

tion results in an invalid opcode (#UD) exception being generated.

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INSTRUCTION SET REFERENCE, A-L

CRC32-Accumulate CRC32 Value

Opcode/

Op/

64-Bit

Compat/

Description

Instruction

Mode

Leg Mode

F2 0F 38 F0 /r

Valid

Accumulate CRC32 on r/m8.

CRC32 r32, r/m8

F2 REX 0F 38 F0 /r

Valid

N.E.

Accumulate CRC32 on r/m8.

CRC32 r32, r/m8¹

F2 0F 38 F1 /r

Valid

Accumulate CRC32 on r/m16.

CRC32 r32, r/m16

F2 0F 38 F1 /r

Valid

Accumulate CRC32 on r/m32.

CRC32 r32, r/m32

F2 REX.W 0F 38 F0 /r

Valid

N.E.

Accumulate CRC32 on r/m8.

CRC32 r64, r/m8

F2 REX.W 0F 38 F1 /r

Valid

N.E.

Accumulate CRC32 on r/m64.

CRC32 r64, r/m64

NOTES:

1. In 64-bit mode, r/m8 can not be encoded to access the following byte registers if a REX prefix is used: AH, BH, CH, DH.

Instruction Operand Encoding

Op/En

Operand 1

Operand 2

Operand 3

Operand 4

ModRM:reg (r, w)

ModRM:r/m (r)

N/A

Description

Starting with an initial value in the first operand (destination operand), accumulates a CRC32 (polynomial

11EDC6F41H) value for the second operand (source operand) and stores the result in the destination operand. The

source operand can be a register or a memory location. The destination operand must be an r32 or r64 register. If

the destination is an r64 register, then the 32-bit result is stored in the least significant double word and

00000000H is stored in the most significant double word of the r64 register.

The initial value supplied in the destination operand is a double word integer stored in the r32 register or the least

significant double word of the r64 register. To incrementally accumulate a CRC32 value, software retains the result

of the previous CRC32 operation in the destination operand, then executes the CRC32 instruction again with new

input data in the source operand. Data contained in the source operand is processed in reflected bit order. This

means that the most significant bit of the source operand is treated as the least significant bit of the quotient, and

so on, for all the bits of the source operand. Likewise, the result of the CRC operation is stored in the destination

operand in reflected bit order. This means that the most significant bit of the resulting CRC (bit 31) is stored in the

least significant bit of the destination operand (bit 0), and so on, for all the bits of the CRC.

Operation

Notes:

BIT_REFLECT64: DST[63-0] = SRC[0-63]

BIT_REFLECT32: DST[31-0] = SRC[0-31]

BIT_REFLECT16: DST[15-0] = SRC[0-15]

BIT_REFLECT8: DST[7-0] = SRC[0-7]

MOD2: Remainder from Polynomial division modulus 2

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INSTRUCTION SET REFERENCE, A-L

CRC32 instruction for 64-bit source operand and 64-bit destination operand:

TEMP1[63-0] := BIT_REFLECT64 (SRC[63-0])

TEMP2[31-0] := BIT_REFLECT32 (DEST[31-0])

TEMP3[95-0] := TEMP1[63-0] « 32

TEMP4[95-0] := TEMP2[31-0] « 64

TEMP5[95-0] := TEMP3[95-0] XOR TEMP4[95-0]

TEMP6[31-0] := TEMP5[95-0] MOD2 11EDC6F41H

DEST[31-0] := BIT_REFLECT (TEMP6[31-0])

DEST[63-32] := 00000000H

CRC32 instruction for 32-bit source operand and 32-bit destination operand:

TEMP1[31-0] := BIT_REFLECT32 (SRC[31-0])

TEMP2[31-0] := BIT_REFLECT32 (DEST[31-0])

TEMP3[63-0] := TEMP1[31-0] « 32

TEMP4[63-0] := TEMP2[31-0] « 32

TEMP5[63-0] := TEMP3[63-0] XOR TEMP4[63-0]

TEMP6[31-0] := TEMP5[63-0] MOD2 11EDC6F41H

DEST[31-0] := BIT_REFLECT (TEMP6[31-0])

CRC32 instruction for 16-bit source operand and 32-bit destination operand:

TEMP1[15-0] := BIT_REFLECT16 (SRC[15-0])

TEMP2[31-0] := BIT_REFLECT32 (DEST[31-0])

TEMP3[47-0] := TEMP1[15-0] « 32

TEMP4[47-0] := TEMP2[31-0] « 16

TEMP5[47-0] := TEMP3[47-0] XOR TEMP4[47-0]

TEMP6[31-0] := TEMP5[47-0] MOD2 11EDC6F41H

DEST[31-0] := BIT_REFLECT (TEMP6[31-0])

CRC32 instruction for 8-bit source operand and 64-bit destination operand:

TEMP1[7-0] := BIT_REFLECT8(SRC[7-0])

TEMP2[31-0] := BIT_REFLECT32 (DEST[31-0])

TEMP3[39-0] := TEMP1[7-0] « 32

TEMP4[39-0] := TEMP2[31-0] « 8

TEMP5[39-0] := TEMP3[39-0] XOR TEMP4[39-0]

TEMP6[31-0] := TEMP5[39-0] MOD2 11EDC6F41H

DEST[31-0] := BIT_REFLECT (TEMP6[31-0])

DEST[63-32] := 00000000H

CRC32 instruction for 8-bit source operand and 32-bit destination operand:

TEMP1[7-0] := BIT_REFLECT8(SRC[7-0])

TEMP2[31-0] := BIT_REFLECT32 (DEST[31-0])

TEMP3[39-0] := TEMP1[7-0] « 32

TEMP4[39-0] := TEMP2[31-0] « 8

TEMP5[39-0] := TEMP3[39-0] XOR TEMP4[39-0]

TEMP6[31-0] := TEMP5[39-0] MOD2 11EDC6F41H

DEST[31-0] := BIT_REFLECT (TEMP6[31-0])

Flags Affected

None.

CRC32-Accumulate CRC32 Value

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INSTRUCTION SET REFERENCE, A-L

Intel C/C++ Compiler Intrinsic Equivalent

unsigned int _mm_crc32_u8( unsigned int crc, unsigned char data )

unsigned int _mm_crc32_u16( unsigned int crc, unsigned short data )

unsigned int _mm_crc32_u32( unsigned int crc, unsigned int data )

unsigned __int64 _mm_crc32_u64( unsigned __int64 crc, unsigned __int64 data )

SIMD Floating-Point Exceptions

None.

Protected Mode Exceptions

#GP(0)

If a memory operand effective address is outside the CS, DS, ES, FS or GS segments.

#SS(0)

If a memory operand effective address is outside the SS segment limit.

#PF (fault-code)

For a page fault.

#AC(0)

If alignment checking is enabled and an unaligned memory reference is made while the

current privilege level is 3.

#UD

If CPUID.01H:ECX.SSE4_2 [Bit 20] = 0.

If LOCK prefix is used.

Real-Address Mode Exceptions

#GP(0)

If any part of the operand lies outside of the effective address space from 0 to 0FFFFH.

#SS(0)

If a memory operand effective address is outside the SS segment limit.

#UD

If CPUID.01H:ECX.SSE4_2 [Bit 20] = 0.

If LOCK prefix is used.

Virtual 8086 Mode Exceptions

#GP(0)

If any part of the operand lies outside of the effective address space from 0 to 0FFFFH.

#SS(0)

If a memory operand effective address is outside the SS segment limit.

#PF (fault-code)

For a page fault.

#AC(0)

If alignment checking is enabled and an unaligned memory reference is made.

#UD

If CPUID.01H:ECX.SSE4_2 [Bit 20] = 0.

If LOCK prefix is used.

Compatibility Mode Exceptions

Same exceptions as in Protected Mode.

64-Bit Mode Exceptions

#GP(0)

If the memory address is in a non-canonical form.

#SS(0)

If a memory address referencing the SS segment is in a non-canonical form.

#PF (fault-code)

For a page fault.

#AC(0)

If alignment checking is enabled and an unaligned memory reference is made while the

current privilege level is 3.

#UD

If CPUID.01H:ECX.SSE4_2 [Bit 20] = 0.

If LOCK prefix is used.

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CRC32-Accumulate CRC32 Value

INSTRUCTION SET REFERENCE, A-L

CVTDQ2PD-Convert Packed Doubleword Integers to Packed Double Precision Floating-Point

Values

Opcode/

Op /

64/32 bit

CPUID

Description

Instruction

Mode

Feature

Support

Flag

F3 0F E6 /r

V/V

SSE2

Convert two packed signed doubleword integers from

CVTDQ2PD xmm1, xmm2/m64

xmm2/mem to two packed double precision floating-point

values in xmm1.

VEX.128.F3.0F.WIG E6 /r

V/V

AVX

Convert two packed signed doubleword integers from

VCVTDQ2PD xmm1, xmm2/m64

xmm2/mem to two packed double precision floating-point

values in xmm1.

VEX.256.F3.0F.WIG E6 /r

V/V

AVX

Convert four packed signed doubleword integers from

VCVTDQ2PD ymm1, xmm2/m128

xmm2/mem to four packed double precision floating-point

values in ymm1.

EVEX.128.F3.0F.W0 E6 /r

V/V

AVX512VL

Convert 2 packed signed doubleword integers from

VCVTDQ2PD xmm1 {k1}{z},

AVX512F

xmm2/m64/m32bcst to eight packed double precision

xmm2/m64/m32bcst

floating-point values in xmm1 with writemask k1.

EVEX.256.F3.0F.W0 E6 /r

V/V

AVX512VL

Convert 4 packed signed doubleword integers from

VCVTDQ2PD ymm1 {k1}{z},

AVX512F

xmm2/m128/m32bcst to 4 packed double precision

xmm2/m128/m32bcst

floating-point values in ymm1 with writemask k1.

EVEX.512.F3.0F.W0 E6 /r

V/V

AVX512F

Convert eight packed signed doubleword integers from

VCVTDQ2PD zmm1 {k1}{z},

ymm2/m256/m32bcst to eight packed double precision

ymm2/m256/m32bcst

floating-point values in zmm1 with writemask k1.

Instruction Operand Encoding

Op/En

Tuple Type

Operand 1

Operand 2

Operand 3

Operand 4

N/A

ModRM:reg (w)

ModRM:r/m (r)

N/A

Half

ModRM:reg (w)

ModRM:r/m (r)

N/A

Description

Converts two, four or eight packed signed doubleword integers in the source operand (the second operand) to two,

four or eight packed double precision floating-point values in the destination operand (the first operand).

EVEX encoded versions: The source operand can be a YMM/XMM/XMM (low 64 bits) register, a 256/128/64-bit

memory location or a 256/128/64-bit vector broadcasted from a 32-bit memory location. The destination operand

is a ZMM/YMM/XMM register conditionally updated with writemask k1. Attempt to encode this instruction with EVEX

embedded rounding is ignored.

VEX.256 encoded version: The source operand is an XMM register or 128- bit memory location. The destination

operand is a YMM register.

VEX.128 encoded version: The source operand is an XMM register or 64- bit memory location. The destination

operand is a XMM register. The upper Bits (MAXVL-1:128) of the corresponding ZMM register destination are

zeroed.

128-bit Legacy SSE version: The source operand is an XMM register or 64- bit memory location. The destination

operand is an XMM register. The upper Bits (MAXVL-1:128) of the corresponding ZMM register destination are

unmodified.

VEX.vvvv and EVEX.vvvv are reserved and must be 1111b, otherwise instructions will #UD.

CVTDQ2PD-Convert Packed Doubleword Integers to Packed Double Precision Floating-Point Values

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INSTRUCTION SET REFERENCE, A-L

VCVTDQ2PD (EVEX Encoded Versions) When SRC Operand is a Memory Source

(KL, VL) = (2, 128), (4, 256), (8, 512)

FOR j := 0 TO KL-1

i := j * 64

k := j * 32

IF k1[j] OR *no writemask*

THEN

IF (EVEX.b = 1)

THEN

DEST[i+63:i] :=

Convert_Integer_To_Double_Precision_Floating_Point(SRC[31:0])

ELSE

DEST[i+63:i] :=

Convert_Integer_To_Double_Precision_Floating_Point(SRC[k+31:k])

FI;

ELSE

IF *merging-masking*

; merging-masking

THEN *DEST[i+63:i] remains unchanged*

ELSE

; zeroing-masking

DEST[i+63:i] := 0

FI;

ENDFOR

DEST[MAXVL-1:VL] := 0

VCVTDQ2PD (VEX.256 Encoded Version)

DEST[63:0] := Convert_Integer_To_Double_Precision_Floating_Point(SRC[31:0])

DEST[127:64] := Convert_Integer_To_Double_Precision_Floating_Point(SRC[63:32])

DEST[191:128] := Convert_Integer_To_Double_Precision_Floating_Point(SRC[95:64])

DEST[255:192] := Convert_Integer_To_Double_Precision_Floating_Point(SRC[127:96)

DEST[MAXVL-1:256] := 0

VCVTDQ2PD (VEX.128 Encoded Version)

DEST[63:0] := Convert_Integer_To_Double_Precision_Floating_Point(SRC[31:0])

DEST[127:64] := Convert_Integer_To_Double_Precision_Floating_Point(SRC[63:32])

DEST[MAXVL-1:128] := 0

CVTDQ2PD (128-bit Legacy SSE Version)

DEST[63:0] := Convert_Integer_To_Double_Precision_Floating_Point(SRC[31:0])

DEST[127:64] := Convert_Integer_To_Double_Precision_Floating_Point(SRC[63:32])

DEST[MAXVL-1:128] (unmodified)

Intel C/C++ Compiler Intrinsic Equivalent

VCVTDQ2PD __m512d _mm512_cvtepi32_pd( __m256i a);

VCVTDQ2PD __m512d _mm512_mask_cvtepi32_pd( __m512d s, __mmask8 k, __m256i a);

VCVTDQ2PD __m512d _mm512_maskz_cvtepi32_pd( __mmask8 k, __m256i a);

VCVTDQ2PD __m256d _mm256_cvtepi32_pd (__m128i src);

VCVTDQ2PD __m256d _mm256_mask_cvtepi32_pd( __m256d s, __mmask8 k, __m256i a);

VCVTDQ2PD __m256d _mm256_maskz_cvtepi32_pd( __mmask8 k, __m256i a);

VCVTDQ2PD __m128d _mm_mask_cvtepi32_pd( __m128d s, __mmask8 k, __m128i a);

VCVTDQ2PD __m128d _mm_maskz_cvtepi32_pd( __mmask8 k, __m128i a);

CVTDQ2PD __m128d _mm_cvtepi32_pd (__m128i src)

CVTDQ2PD-Convert Packed Doubleword Integers to Packed Double Precision Floating-Point Values

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INSTRUCTION SET REFERENCE, A-L

CVTDQ2PS-Convert Packed Doubleword Integers to Packed Single Precision Floating-Point

Values

Opcode

Op /

64/32 bit

CPUID

Description

Instruction

Mode

Feature

Support

Flag

NP 0F 5B /r

V/V

SSE2

Convert four packed signed doubleword integers from

CVTDQ2PS xmm1, xmm2/m128

xmm2/mem to four packed single precision floating-

point values in xmm1.

VEX.128.0F.WIG 5B /r

V/V

AVX

Convert four packed signed doubleword integers from

VCVTDQ2PS xmm1, xmm2/m128

xmm2/mem to four packed single precision floating-

point values in xmm1.

VEX.256.0F.WIG 5B /r

V/V

AVX

Convert eight packed signed doubleword integers from

VCVTDQ2PS ymm1, ymm2/m256

ymm2/mem to eight packed single precision floating-

point values in ymm1.

EVEX.128.0F.W0 5B /r

V/V

AVX512VL

Convert four packed signed doubleword integers from

VCVTDQ2PS xmm1 {k1}{z},

AVX512F

xmm2/m128/m32bcst to four packed single precision

xmm2/m128/m32bcst

floating-point values in xmm1with writemask k1.

EVEX.256.0F.W0 5B /r

V/V

AVX512VL

Convert eight packed signed doubleword integers from

VCVTDQ2PS ymm1 {k1}{z},

AVX512F

ymm2/m256/m32bcst to eight packed single precision

ymm2/m256/m32bcst

floating-point values in ymm1with writemask k1.

EVEX.512.0F.W0 5B /r

V/V

AVX512F

Convert sixteen packed signed doubleword integers

VCVTDQ2PS zmm1 {k1}{z},

from zmm2/m512/m32bcst to sixteen packed single

zmm2/m512/m32bcst{er}

precision floating-point values in zmm1with writemask

k1.

Instruction Operand Encoding

Op/En

Tuple Type

Operand 1

Operand 2

Operand 3

Operand 4

N/A

ModRM:reg (w)

ModRM:r/m (r)

N/A

Full

ModRM:reg (w)

ModRM:r/m (r)

N/A

Description

Converts four, eight or sixteen packed signed doubleword integers in the source operand to four, eight or sixteen

packed single precision floating-point values in the destination operand.

EVEX encoded versions: The source operand can be a ZMM/YMM/XMM register, a 512/256/128-bit memory loca-

tion or a 512/256/128-bit vector broadcasted from a 32-bit memory location. The destination operand is a

ZMM/YMM/XMM register conditionally updated with writemask k1.

VEX.256 encoded version: The source operand is a YMM register or 256- bit memory location. The destination

operand is a YMM register. Bits (MAXVL-1:256) of the corresponding register destination are zeroed.

VEX.128 encoded version: The source operand is an XMM register or 128- bit memory location. The destination

operand is a XMM register. The upper bits (MAXVL-1:128) of the corresponding register destination are zeroed.

128-bit Legacy SSE version: The source operand is an XMM register or 128- bit memory location. The destination

operand is an XMM register. The upper Bits (MAXVL-1:128) of the corresponding register destination are unmodi-

fied.

VEX.vvvv and EVEX.vvvv are reserved and must be 1111b, otherwise instructions will #UD.

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INSTRUCTION SET REFERENCE, A-L

Operation

VCVTDQ2PS (EVEX Encoded Versions) When SRC Operand is a Register

(KL, VL) = (4, 128), (8, 256), (16, 512)

IF (VL = 512) AND (EVEX.b = 1)

THEN

SET_ROUNDING_MODE_FOR_THIS_INSTRUCTION(EVEX.RC); ; refer to Table 15-4 in the Intel^® 64 and IA-32 Architectures

Software Developer’s Manual, Volume 1

ELSE

SET_ROUNDING_MODE_FOR_THIS_INSTRUCTION(MXCSR.RC); ; refer to Table 15-4 in the Intel^® 64 and IA-32 Architectures

Software Developer’s Manual, Volume 1

FI;

FOR j := 0 TO KL-1

i := j * 32

IF k1[j] OR *no writemask*

THEN DEST[i+31:i] :=

Convert_Integer_To_Single_Precision_Floating_Point(SRC[i+31:i])

ELSE

IF *merging-masking*

; merging-masking

THEN *DEST[i+31:i] remains unchanged*

ELSE

; zeroing-masking

DEST[i+31:i] := 0

FI;

ENDFOR

DEST[MAXVL-1:VL] := 0

VCVTDQ2PS (EVEX Encoded Versions) When SRC Operand is a Memory Source

(KL, VL) = (4, 128), (8, 256), (16, 512)

FOR j := 0 TO KL-1

i := j * 32

IF k1[j] OR *no writemask*

THEN

IF (EVEX.b = 1)

THEN

DEST[i+31:i] :=

Convert_Integer_To_Single_Precision_Floating_Point(SRC[31:0])

ELSE

DEST[i+31:i] :=

Convert_Integer_To_Single_Precision_Floating_Point(SRC[i+31:i])

FI;

ELSE

IF *merging-masking*

; merging-masking

THEN *DEST[i+31:i] remains unchanged*

ELSE

; zeroing-masking

DEST[i+31:i] := 0

FI;

ENDFOR

DEST[MAXVL-1:VL] := 0

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INSTRUCTION SET REFERENCE, A-L

VCVTDQ2PS (VEX.256 Encoded Version)

DEST[31:0] := Convert_Integer_To_Single_Precision_Floating_Point(SRC[31:0])

DEST[63:32] := Convert_Integer_To_Single_Precision_Floating_Point(SRC[63:32])

DEST[95:64] := Convert_Integer_To_Single_Precision_Floating_Point(SRC[95:64])

DEST[127:96] := Convert_Integer_To_Single_Precision_Floating_Point(SRC[127:96)

DEST[159:128] := Convert_Integer_To_Single_Precision_Floating_Point(SRC[159:128])

DEST[191:160] := Convert_Integer_To_Single_Precision_Floating_Point(SRC[191:160])

DEST[223:192] := Convert_Integer_To_Single_Precision_Floating_Point(SRC[223:192])

DEST[255:224] := Convert_Integer_To_Single_Precision_Floating_Point(SRC[255:224)

DEST[MAXVL-1:256] := 0

VCVTDQ2PS (VEX.128 Encoded Version)

DEST[31:0] := Convert_Integer_To_Single_Precision_Floating_Point(SRC[31:0])

DEST[63:32] := Convert_Integer_To_Single_Precision_Floating_Point(SRC[63:32])

DEST[95:64] := Convert_Integer_To_Single_Precision_Floating_Point(SRC[95:64])

DEST[127:96] := Convert_Integer_To_Single_Precision_Floating_Point(SRC[127z:96)

DEST[MAXVL-1:128] := 0

CVTDQ2PS (128-bit Legacy SSE Version)

DEST[31:0] := Convert_Integer_To_Single_Precision_Floating_Point(SRC[31:0])

DEST[63:32] := Convert_Integer_To_Single_Precision_Floating_Point(SRC[63:32])

DEST[95:64] := Convert_Integer_To_Single_Precision_Floating_Point(SRC[95:64])

DEST[127:96] := Convert_Integer_To_Single_Precision_Floating_Point(SRC[127z:96)

DEST[MAXVL-1:128] (unmodified)

Intel C/C++ Compiler Intrinsic Equivalent

VCVTDQ2PS __m512 _mm512_cvtepi32_ps( __m512i a);

VCVTDQ2PS __m512 _mm512_mask_cvtepi32_ps( __m512 s, __mmask16 k, __m512i a);

VCVTDQ2PS __m512 _mm512_maskz_cvtepi32_ps( __mmask16 k, __m512i a);

VCVTDQ2PS __m512 _mm512_cvt_roundepi32_ps( __m512i a, int r);

VCVTDQ2PS __m512 _mm512_mask_cvt_roundepi_ps( __m512 s, __mmask16 k, __m512i a, int r);

VCVTDQ2PS __m512 _mm512_maskz_cvt_roundepi32_ps( __mmask16 k, __m512i a, int r);

VCVTDQ2PS __m256 _mm256_mask_cvtepi32_ps( __m256 s, __mmask8 k, __m256i a);

VCVTDQ2PS __m256 _mm256_maskz_cvtepi32_ps( __mmask8 k, __m256i a);

VCVTDQ2PS __m128 _mm_mask_cvtepi32_ps( __m128 s, __mmask8 k, __m128i a);

VCVTDQ2PS __m128 _mm_maskz_cvtepi32_ps( __mmask8 k, __m128i a);

CVTDQ2PS __m256 _mm256_cvtepi32_ps (__m256i src)

CVTDQ2PS __m128 _mm_cvtepi32_ps (__m128i src)

SIMD Floating-Point Exceptions

Precision.

Other Exceptions

VEX-encoded instructions, see Table 2-19, “Type 2 Class Exception Conditions.”

EVEX-encoded instructions, see Table 2-46, “Type E2 Class Exception Conditions.”

Additionally:

#UD

If VEX.vvvv != 1111B or EVEX.vvvv != 1111B.

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INSTRUCTION SET REFERENCE, A-L

CVTPD2DQ-Convert Packed Double Precision Floating-Point Values to Packed Doubleword

Integers

Opcode

Op /

64/32 bit

CPUID

Description

Instruction

Mode

Feature

Support

Flag

F2 0F E6 /r

V/V

SSE2

Convert two packed double precision floating-point

CVTPD2DQ xmm1, xmm2/m128

values in xmm2/mem to two signed doubleword

integers in xmm1.

VEX.128.F2.0F.WIG E6 /r

V/V

AVX

Convert two packed double precision floating-point

VCVTPD2DQ xmm1, xmm2/m128

values in xmm2/mem to two signed doubleword

integers in xmm1.

VEX.256.F2.0F.WIG E6 /r

V/V

AVX

Convert four packed double precision floating-point

VCVTPD2DQ xmm1, ymm2/m256

values in ymm2/mem to four signed doubleword

integers in xmm1.

EVEX.128.F2.0F.W1 E6 /r

V/V

AVX512VL

Convert two packed double precision floating-point

VCVTPD2DQ xmm1 {k1}{z},

AVX512F

values in xmm2/m128/m64bcst to two signed

xmm2/m128/m64bcst

doubleword integers in xmm1 subject to writemask k1.

EVEX.256.F2.0F.W1 E6 /r

V/V

AVX512VL

Convert four packed double precision floating-point

VCVTPD2DQ xmm1 {k1}{z},

AVX512F

values in ymm2/m256/m64bcst to four signed

ymm2/m256/m64bcst

doubleword integers in xmm1 subject to writemask k1.

EVEX.512.F2.0F.W1 E6 /r

V/V

AVX512F

Convert eight packed double precision floating-point

VCVTPD2DQ ymm1 {k1}{z},

values in zmm2/m512/m64bcst to eight signed

zmm2/m512/m64bcst{er}

doubleword integers in ymm1 subject to writemask k1.

Instruction Operand Encoding

Op/En

Tuple Type

Operand 1

Operand 2

Operand 3

Operand 4

N/A

ModRM:reg (w)

ModRM:r/m (r)

N/A

Full

ModRM:reg (w)

ModRM:r/m (r)

N/A

Description

Converts packed double precision floating-point values in the source operand (second operand) to packed signed

doubleword integers in the destination operand (first operand).

When a conversion is inexact, the value returned is rounded according to the rounding control bits in the MXCSR

format, the floating-point invalid exception is raised, and if this exception is masked, the indefinite integer value

(2^w-1, where w represents the number of bits in the destination format) is returned.

EVEX encoded versions: The source operand is a ZMM/YMM/XMM register, a 512-bit memory location, or a 512-bit

vector broadcasted from a 64-bit memory location. The destination operand is a ZMM/YMM/XMM register condi-

tionally updated with writemask k1. The upper bits (MAXVL-1:256/128/64) of the corresponding destination are

zeroed.

VEX.256 encoded version: The source operand is a YMM register or 256- bit memory location. The destination

operand is an XMM register. The upper bits (MAXVL-1:128) of the corresponding ZMM register destination are

zeroed.

VEX.128 encoded version: The source operand is an XMM register or 128- bit memory location. The destination

operand is a XMM register. The upper bits (MAXVL-1:64) of the corresponding ZMM register destination are zeroed.

128-bit Legacy SSE version: The source operand is an XMM register or 128- bit memory location. The destination

operand is an XMM register. Bits[127:64] of the destination XMM register are zeroed. However, the upper bits

(MAXVL-1:128) of the corresponding ZMM register destination are unmodified.

VEX.vvvv and EVEX.vvvv are reserved and must be 1111b, otherwise instructions will #UD.

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INSTRUCTION SET REFERENCE, A-L

SRC

DEST

Figure 3-12. VCVTPD2DQ (VEX.256 encoded version)

Operation

VCVTPD2DQ (EVEX Encoded Versions) When SRC Operand is a Register

(KL, VL) = (2, 128), (4, 256), (8, 512)

IF (VL = 512) AND (EVEX.b = 1)

THEN

SET_ROUNDING_MODE_FOR_THIS_INSTRUCTION(EVEX.RC);

ELSE

SET_ROUNDING_MODE_FOR_THIS_INSTRUCTION(MXCSR.RC);

FI;

FOR j := 0 TO KL-1

i := j * 32

k := j * 64

IF k1[j] OR *no writemask*

THEN DEST[i+31:i] :=

Convert_Double_Precision_Floating_Point_To_Integer(SRC[k+63:k])

ELSE

IF *merging-masking*

; merging-masking

THEN *DEST[i+31:i] remains unchanged*

ELSE

; zeroing-masking

DEST[i+31:i] := 0

FI;

ENDFOR

DEST[MAXVL-1:VL/2] := 0

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INSTRUCTION SET REFERENCE, A-L

VCVTPD2DQ (EVEX Encoded Versions) When SRC Operand is a Memory Source

(KL, VL) = (2, 128), (4, 256), (8, 512)

FOR j := 0 TO KL-1

i := j * 32

k := j * 64

IF k1[j] OR *no writemask*

THEN

IF (EVEX.b = 1)

THEN

DEST[i+31:i] :=

Convert_Double_Precision_Floating_Point_To_Integer(SRC[63:0])

ELSE

DEST[i+31:i] :=

Convert_Double_Precision_Floating_Point_To_Integer(SRC[k+63:k])

FI;

ELSE

IF *merging-masking*

; merging-masking

THEN *DEST[i+31:i] remains unchanged*

ELSE

; zeroing-masking

DEST[i+31:i] := 0

FI;

ENDFOR

DEST[MAXVL-1:VL/2] := 0

VCVTPD2DQ (VEX.256 Encoded Version)

DEST[31:0] := Convert_Double_Precision_Floating_Point_To_Integer(SRC[63:0])

DEST[63:32] := Convert_Double_Precision_Floating_Point_To_Integer(SRC[127:64])

DEST[95:64] := Convert_Double_Precision_Floating_Point_To_Integer(SRC[191:128])

DEST[127:96] := Convert_Double_Precision_Floating_Point_To_Integer(SRC[255:192)

DEST[MAXVL-1:128] := 0

VCVTPD2DQ (VEX.128 Encoded Version)

DEST[31:0] := Convert_Double_Precision_Floating_Point_To_Integer(SRC[63:0])

DEST[63:32] := Convert_Double_Precision_Floating_Point_To_Integer(SRC[127:64])

DEST[MAXVL-1:64] := 0

CVTPD2DQ (128-bit Legacy SSE Version)

DEST[31:0] := Convert_Double_Precision_Floating_Point_To_Integer(SRC[63:0])

DEST[63:32] := Convert_Double_Precision_Floating_Point_To_Integer(SRC[127:64])

DEST[127:64] := 0

DEST[MAXVL-1:128] (unmodified)

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INSTRUCTION SET REFERENCE, A-L

Intel C/C++ Compiler Intrinsic Equivalent

VCVTPD2DQ __m256i _mm512_cvtpd_epi32( __m512d a);

VCVTPD2DQ __m256i _mm512_mask_cvtpd_epi32( __m256i s, __mmask8 k, __m512d a);

VCVTPD2DQ __m256i _mm512_maskz_cvtpd_epi32( __mmask8 k, __m512d a);

VCVTPD2DQ __m256i _mm512_cvt_roundpd_epi32( __m512d a, int r);

VCVTPD2DQ __m256i _mm512_mask_cvt_roundpd_epi32( __m256i s, __mmask8 k, __m512d a, int r);

VCVTPD2DQ __m256i _mm512_maskz_cvt_roundpd_epi32( __mmask8 k, __m512d a, int r);

VCVTPD2DQ __m128i _mm256_mask_cvtpd_epi32( __m128i s, __mmask8 k, __m256d a);

VCVTPD2DQ __m128i _mm256_maskz_cvtpd_epi32( __mmask8 k, __m256d a);

VCVTPD2DQ __m128i _mm_mask_cvtpd_epi32( __m128i s, __mmask8 k, __m128d a);

VCVTPD2DQ __m128i _mm_maskz_cvtpd_epi32( __mmask8 k, __m128d a);

VCVTPD2DQ __m128i _mm256_cvtpd_epi32 (__m256d src)

CVTPD2DQ __m128i _mm_cvtpd_epi32 (__m128d src)

SIMD Floating-Point Exceptions

Invalid, Precision.

Other Exceptions

See Table 2-19, “Type 2 Class Exception Conditions.”

EVEX-encoded instructions, see Table 2-46, “Type E2 Class Exception Conditions.”

Additionally:

#UD

If VEX.vvvv != 1111B or EVEX.vvvv != 1111B.

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INSTRUCTION SET REFERENCE, A-L

CVTPD2PI-Convert Packed Double Precision Floating-Point Values to Packed Dword Integers

Opcode/

Op/

64/32 bit

CPUID

Description

Instruction

Mode

Feature

Support

Flag

66 0F 2D /r

V/V

SSE2

Convert two packed double precision floating-

point values from xmm/m128 to two packed

CVTPD2PI mm, xmm/m128

signed doubleword integers in mm.

Instruction Operand Encoding

Op/En

Operand 1

Operand 2

Operand 3

Operand 4

ModRM:reg (w)

ModRM:r/m (r)

N/A

Description

Converts two packed double precision floating-point values in the source operand (second operand) to two packed

signed doubleword integers in the destination operand (first operand).

The source operand can be an XMM register or a 128-bit memory location. The destination operand is an MMX tech-

nology register.

When a conversion is inexact, the value returned is rounded according to the rounding control bits in the MXCSR

exception is raised, and if this exception is masked, the indefinite integer value (80000000H) is returned.

This instruction causes a transition from x87 FPU to MMX technology operation (that is, the x87 FPU top-of-stack

pointer is set to 0 and the x87 FPU tag word is set to all 0s [valid]). If this instruction is executed while an x87 FPU

floating-point exception is pending, the exception is handled before the CVTPD2PI instruction is executed.

In 64-bit mode, use of the REX.R prefix permits this instruction to access additional registers (XMM8-XMM15).

Operation

DEST[31:0] := Convert_Double_Precision_Floating_Point_To_Integer32(SRC[63:0]);

DEST[63:32] := Convert_Double_Precision_Floating_Point_To_Integer32(SRC[127:64]);

Intel C/C++ Compiler Intrinsic Equivalent

CVTPD1PI __m64 _mm_cvtpd_pi32(__m128d a)

SIMD Floating-Point Exceptions

Invalid, Precision.

Other Exceptions

See Table 23-4, “Exception Conditions for Legacy SIMD/MMX Instructions with FP Exception and 16-Byte Align-

ment” in the Intel^® 64 and IA-32 Architectures Software Developer’s Manual, Volume 3B.

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INSTRUCTION SET REFERENCE, A-L

CVTPD2PS-Convert Packed Double Precision Floating-Point Values to Packed Single Precision

Floating-Point Values

Opcode/

Op /

64/32 bit

CPUID

Description

Instruction

Mode

Feature

Support

Flag

66 0F 5A /r

V/V

SSE2

Convert two packed double precision floating-point

CVTPD2PS xmm1, xmm2/m128

values in xmm2/mem to two single precision floating-

point values in xmm1.

VEX.128.66.0F.WIG 5A /r

V/V

AVX

Convert two packed double precision floating-point

VCVTPD2PS xmm1, xmm2/m128

values in xmm2/mem to two single precision floating-

point values in xmm1.

VEX.256.66.0F.WIG 5A /r

V/V

AVX

Convert four packed double precision floating-point

VCVTPD2PS xmm1, ymm2/m256

values in ymm2/mem to four single precision floating-

point values in xmm1.

EVEX.128.66.0F.W1 5A /r

V/V

AVX512VL

Convert two packed double precision floating-point

VCVTPD2PS xmm1 {k1}{z},

AVX512F

values in xmm2/m128/m64bcst to two single

xmm2/m128/m64bcst

precision floating-point values in xmm1with

writemask k1.

EVEX.256.66.0F.W1 5A /r

V/V

AVX512VL

Convert four packed double precision floating-point

VCVTPD2PS xmm1 {k1}{z},

AVX512F

values in ymm2/m256/m64bcst to four single

ymm2/m256/m64bcst

precision floating-point values in xmm1with

writemask k1.

EVEX.512.66.0F.W1 5A /r

V/V

AVX512F

Convert eight packed double precision floating-point

VCVTPD2PS ymm1 {k1}{z},

values in zmm2/m512/m64bcst to eight single

zmm2/m512/m64bcst{er}

precision floating-point values in ymm1with

writemask k1.

Instruction Operand Encoding

Op/En

Tuple Type

Operand 1

Operand 2

Operand 3

Operand 4

N/A

ModRM:reg (w)

ModRM:r/m (r)

N/A

Full

ModRM:reg (w)

ModRM:r/m (r)

N/A

Description

Converts two, four or eight packed double precision floating-point values in the source operand (second operand)

to two, four or eight packed single precision floating-point values in the destination operand (first operand).

When a conversion is inexact, the value returned is rounded according to the rounding control bits in the MXCSR

EVEX encoded versions: The source operand is a ZMM/YMM/XMM register, a 512/256/128-bit memory location, or

a 512/256/128-bit vector broadcasted from a 64-bit memory location. The destination operand is a

YMM/XMM/XMM (low 64-bits) register conditionally updated with writemask k1. The upper bits (MAXVL-

1:256/128/64) of the corresponding destination are zeroed.

VEX.256 encoded version: The source operand is a YMM register or 256- bit memory location. The destination

operand is an XMM register. The upper bits (MAXVL-1:128) of the corresponding ZMM register destination are

zeroed.

VEX.128 encoded version: The source operand is an XMM register or 128- bit memory location. The destination

operand is a XMM register. The upper bits (MAXVL-1:64) of the corresponding ZMM register destination are zeroed.

128-bit Legacy SSE version: The source operand is an XMM register or 128- bit memory location. The destination

operand is an XMM register. Bits[127:64] of the destination XMM register are zeroed. However, the upper Bits

(MAXVL-1:128) of the corresponding ZMM register destination are unmodified.

VEX.vvvv and EVEX.vvvv are reserved and must be 1111b otherwise instructions will #UD.

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INSTRUCTION SET REFERENCE, A-L

SRC

DEST

Figure 3-13. VCVTPD2PS (VEX.256 encoded version)

Operation

VCVTPD2PS (EVEX Encoded Version) When SRC Operand is a Register

(KL, VL) = (2, 128), (4, 256), (8, 512)

IF (VL = 512) AND (EVEX.b = 1)

THEN

SET_ROUNDING_MODE_FOR_THIS_INSTRUCTION(EVEX.RC);

ELSE

SET_ROUNDING_MODE_FOR_THIS_INSTRUCTION(MXCSR.RC);

FI;

FOR j := 0 TO KL-1

i := j * 32

k := j * 64

IF k1[j] OR *no writemask*

THEN

DEST[i+31:i] := Convert_Double_Precision_Floating_Point_To_Single_Precision_Floating_Point(SRC[k+63:k])

ELSE

IF *merging-masking*

; merging-masking

THEN *DEST[i+31:i] remains unchanged*

ELSE

; zeroing-masking

DEST[i+31:i] := 0

FI;

ENDFOR

DEST[MAXVL-1:VL/2] := 0

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INSTRUCTION SET REFERENCE, A-L

VCVTPD2PS (EVEX Encoded Version) When SRC Operand is a Memory Source

(KL, VL) = (2, 128), (4, 256), (8, 512)

FOR j := 0 TO KL-1

i := j * 32

k := j * 64

IF k1[j] OR *no writemask*

THEN

IF (EVEX.b = 1)

THEN

DEST[i+31:i] :=Convert_Double_Precision_Floating_Point_To_Single_Precision_Floating_Point(SRC[63:0])

ELSE

DEST[i+31:i] := Convert_Double_Precision_Floating_Point_To_Single_Precision_Floating_Point(SRC[k+63:k])

FI;

ELSE

IF *merging-masking*

; merging-masking

THEN *DEST[i+31:i] remains unchanged*

ELSE

; zeroing-masking

DEST[i+31:i] := 0

FI;

ENDFOR

DEST[MAXVL-1:VL/2] := 0

VCVTPD2PS (VEX.256 Encoded Version)

DEST[31:0] := Convert_Double_Precision_To_Single_Precision_Floating_Point(SRC[63:0])

DEST[63:32] := Convert_Double_Precision_To_Single_Precision_Floating_Point(SRC[127:64])

DEST[95:64] := Convert_Double_Precision_To_Single_Precision_Floating_Point(SRC[191:128])

DEST[127:96] := Convert_Double_Precision_To_Single_Precision_Floating_Point(SRC[255:192)

DEST[MAXVL-1:128] := 0

VCVTPD2PS (VEX.128 Encoded Version)

DEST[31:0] := Convert_Double_Precision_To_Single_Precision_Floating_Point(SRC[63:0])

DEST[63:32] := Convert_Double_Precision_To_Single_Precision_Floating_Point(SRC[127:64])

DEST[MAXVL-1:64] := 0

CVTPD2PS (128-bit Legacy SSE Version)

DEST[31:0] := Convert_Double_Precision_To_Single_Precision_Floating_Point(SRC[63:0])

DEST[63:32] := Convert_Double_Precision_To_Single_Precision_Floating_Point(SRC[127:64])

DEST[127:64] := 0

DEST[MAXVL-1:128] (unmodified)

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INSTRUCTION SET REFERENCE, A-L

Intel C/C++ Compiler Intrinsic Equivalent

VCVTPD2PS __m256 _mm512_cvtpd_ps( __m512d a);

VCVTPD2PS __m256 _mm512_mask_cvtpd_ps( __m256 s, __mmask8 k, __m512d a);

VCVTPD2PS __m256 _mm512_maskz_cvtpd_ps( __mmask8 k, __m512d a);

VCVTPD2PS __m256 _mm512_cvt_roundpd_ps( __m512d a, int r);

VCVTPD2PS __m256 _mm512_mask_cvt_roundpd_ps( __m256 s, __mmask8 k, __m512d a, int r);

VCVTPD2PS __m256 _mm512_maskz_cvt_roundpd_ps( __mmask8 k, __m512d a, int r);

VCVTPD2PS __m128 _mm256_mask_cvtpd_ps( __m128 s, __mmask8 k, __m256d a);

VCVTPD2PS __m128 _mm256_maskz_cvtpd_ps( __mmask8 k, __m256d a);

VCVTPD2PS __m128 _mm_mask_cvtpd_ps( __m128 s, __mmask8 k, __m128d a);

VCVTPD2PS __m128 _mm_maskz_cvtpd_ps( __mmask8 k, __m128d a);

VCVTPD2PS __m128 _mm256_cvtpd_ps (__m256d a)

CVTPD2PS __m128 _mm_cvtpd_ps (__m128d a)

SIMD Floating-Point Exceptions

Invalid, Precision, Underflow, Overflow, Denormal.

Other Exceptions

VEX-encoded instructions, see Table 2-19, “Type 2 Class Exception Conditions.”

EVEX-encoded instructions, see Table 2-46, “Type E2 Class Exception Conditions.”

Additionally:

#UD

If VEX.vvvv != 1111B or EVEX.vvvv != 1111B.

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INSTRUCTION SET REFERENCE, A-L

CVTPI2PD-Convert Packed Dword Integers to Packed Double Precision Floating-Point Values

Opcode/

Op/

64-Bit

Compat/

Description

Instruction

Mode

Leg Mode

66 0F 2A /r

Valid

Convert two packed signed doubleword

integers from mm/mem64 to two packed

CVTPI2PD xmm, mm/m64¹

double precision floating-point values in xmm.

NOTES:

1. Operation is different for different operand sets; see the Description section.

Instruction Operand Encoding

Op/En

Operand 1

Operand 2

Operand 3

Operand 4

ModRM:reg (w)

ModRM:r/m (r)

N/A

Description

Converts two packed signed doubleword integers in the source operand (second operand) to two packed double

precision floating-point values in the destination operand (first operand).

The source operand can be an MMX technology register or a 64-bit memory location. The destination operand is an

XMM register. In addition, depending on the operand configuration:

• For operands xmm, mm: the instruction causes a transition from x87 FPU to MMX technology operation (that

is, the x87 FPU top-of-stack pointer is set to 0 and the x87 FPU tag word is set to all 0s [valid]). If this

instruction is executed while an x87 FPU floating-point exception is pending, the exception is handled before

the CVTPI2PD instruction is executed.

• For operands xmm, m64: the instruction does not cause a transition to MMX technology and does not take

x87 FPU exceptions.

In 64-bit mode, use of the REX.R prefix permits this instruction to access additional registers (XMM8-XMM15).

Operation

DEST[63:0] := Convert_Integer_To_Double_Precision_Floating_Point(SRC[31:0]);

DEST[127:64] := Convert_Integer_To_Double_Precision_Floating_Point(SRC[63:32]);

Intel C/C++ Compiler Intrinsic Equivalent

CVTPI2PD __m128d _mm_cvtpi32_pd(__m64 a)

SIMD Floating-Point Exceptions

None.

Other Exceptions

See Table 23-6, “Exception Conditions for Legacy SIMD/MMX Instructions with XMM and without FP Exception” in

the Intel^® 64 and IA-32 Architectures Software Developer’s Manual, Volume 3B.

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INSTRUCTION SET REFERENCE, A-L

CVTPI2PS-Convert Packed Dword Integers to Packed Single Precision Floating-Point Values

Opcode/

Op/

64-Bit

Compat/

Description

Instruction

Mode

Leg Mode

NP 0F 2A /r

Valid

Convert two signed doubleword integers

from mm/m64 to two single precision

CVTPI2PS xmm, mm/m64

floating-point values in xmm.

Instruction Operand Encoding

Op/En

Operand 1

Operand 2

Operand 3

Operand 4

ModRM:reg (r, w)

ModRM:r/m (r)

N/A

Description

Converts two packed signed doubleword integers in the source operand (second operand) to two packed single

precision floating-point values in the destination operand (first operand).

The source operand can be an MMX technology register or a 64-bit memory location. The destination operand is an

XMM register. The results are stored in the low quadword of the destination operand, and the high quadword

remains unchanged. When a conversion is inexact, the value returned is rounded according to the rounding control

bits in the MXCSR register.

This instruction causes a transition from x87 FPU to MMX technology operation (that is, the x87 FPU top-of-stack

pointer is set to 0 and the x87 FPU tag word is set to all 0s [valid]). If this instruction is executed while an x87 FPU

floating-point exception is pending, the exception is handled before the CVTPI2PS instruction is executed.

In 64-bit mode, use of the REX.R prefix permits this instruction to access additional registers (XMM8-XMM15).

Operation

DEST[31:0] := Convert_Integer_To_Single_Precision_Floating_Point(SRC[31:0]);

DEST[63:32] := Convert_Integer_To_Single_Precision_Floating_Point(SRC[63:32]);

(* High quadword of destination unchanged *)

Intel C/C++ Compiler Intrinsic Equivalent

CVTPI2PS __m128 _mm_cvtpi32_ps(__m128 a, __m64 b)

SIMD Floating-Point Exceptions

Precision.

Other Exceptions

See Table 23-5, “Exception Conditions for Legacy SIMD/MMX Instructions with XMM and FP Exception” in the Intel^®

64 and IA-32 Architectures Software Developer’s Manual, Volume 3B.

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INSTRUCTION SET REFERENCE, A-L

CVTPS2DQ-Convert Packed Single Precision Floating-Point Values to Packed Signed

Doubleword Integer Values

Opcode/

Op /

64/32 bit

CPUID

Description

Instruction

Mode

Feature

Support

Flag

66 0F 5B /r

V/V

SSE2

Convert four packed single precision floating-point values

CVTPS2DQ xmm1, xmm2/m128

from xmm2/mem to four packed signed doubleword values

in xmm1.

VEX.128.66.0F.WIG 5B /r

V/V

AVX

Convert four packed single precision floating-point values

VCVTPS2DQ xmm1, xmm2/m128

from xmm2/mem to four packed signed doubleword values

in xmm1.

VEX.256.66.0F.WIG 5B /r

V/V

AVX

Convert eight packed single precision floating-point values

VCVTPS2DQ ymm1, ymm2/m256

from ymm2/mem to eight packed signed doubleword values

in ymm1.

EVEX.128.66.0F.W0 5B /r

V/V

AVX512VL

Convert four packed single precision floating-point values

VCVTPS2DQ xmm1 {k1}{z},

AVX512F

from xmm2/m128/m32bcst to four packed signed

xmm2/m128/m32bcst

doubleword values in xmm1 subject to writemask k1.

EVEX.256.66.0F.W0 5B /r

V/V

AVX512VL

Convert eight packed single precision floating-point values

VCVTPS2DQ ymm1 {k1}{z},

AVX512F

from ymm2/m256/m32bcst to eight packed signed

ymm2/m256/m32bcst

doubleword values in ymm1 subject to writemask k1.

EVEX.512.66.0F.W0 5B /r

V/V

AVX512F

Convert sixteen packed single precision floating-point

VCVTPS2DQ zmm1 {k1}{z},

values from zmm2/m512/m32bcst to sixteen packed

zmm2/m512/m32bcst{er}

signed doubleword values in zmm1 subject to writemask

k1.

Instruction Operand Encoding

Op/En

Tuple Type

Operand 1

Operand 2

Operand 3

Operand 4

N/A

ModRM:reg (w)

ModRM:r/m (r)

N/A

Full

ModRM:reg (w)

ModRM:r/m (r)

N/A

Description

Converts four, eight or sixteen packed single precision floating-point values in the source operand to four, eight or

sixteen signed doubleword integers in the destination operand.

When a conversion is inexact, the value returned is rounded according to the rounding control bits in the MXCSR

format, the floating-point invalid exception is raised, and if this exception is masked, the indefinite integer value

(2^w-1, where w represents the number of bits in the destination format) is returned.

EVEX encoded versions: The source operand is a ZMM register, a 512-bit memory location or a 512-bit vector

broadcasted from a 32-bit memory location. The destination operand is a ZMM register conditionally updated with

writemask k1.

VEX.256 encoded version: The source operand is a YMM register or 256- bit memory location. The destination

operand is a YMM register. The upper bits (MAXVL-1:256) of the corresponding ZMM register destination are

zeroed.

VEX.128 encoded version: The source operand is an XMM register or 128- bit memory location. The destination

operand is a XMM register. The upper bits (MAXVL-1:128) of the corresponding ZMM register destination are

zeroed.

128-bit Legacy SSE version: The source operand is an XMM register or 128- bit memory location. The destination

operand is an XMM register. The upper bits (MAXVL-1:128) of the corresponding ZMM register destination are

unmodified.

VEX.vvvv and EVEX.vvvv are reserved and must be 1111b otherwise instructions will #UD.

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INSTRUCTION SET REFERENCE, A-L

Operation

VCVTPS2DQ (Encoded Versions) When SRC Operand is a Register

(KL, VL) = (4, 128), (8, 256), (16, 512)

IF (VL = 512) AND (EVEX.b = 1)

THEN

SET_ROUNDING_MODE_FOR_THIS_INSTRUCTION(EVEX.RC);

ELSE

SET_ROUNDING_MODE_FOR_THIS_INSTRUCTION(MXCSR.RC);

FI;

FOR j := 0 TO KL-1

i := j * 32

IF k1[j] OR *no writemask*

THEN DEST[i+31:i] :=

Convert_Single_Precision_Floating_Point_To_Integer(SRC[i+31:i])

ELSE

IF *merging-masking*

; merging-masking

THEN *DEST[i+31:i] remains unchanged*

ELSE

; zeroing-masking

DEST[i+31:i] := 0

FI;

ENDFOR

DEST[MAXVL-1:VL] := 0

VCVTPS2DQ (EVEX Encoded Versions) When SRC Operand is a Memory Source

(KL, VL) = (4, 128), (8, 256), (16, 512)

FOR j := 0 TO 15

i := j * 32

IF k1[j] OR *no writemask*

THEN

IF (EVEX.b = 1)

THEN

DEST[i+31:i] :=

Convert_Single_Precision_Floating_Point_To_Integer(SRC[31:0])

ELSE

DEST[i+31:i] :=

Convert_Single_Precision_Floating_Point_To_Integer(SRC[i+31:i])

FI;

ELSE

IF *merging-masking*

; merging-masking

THEN *DEST[i+31:i] remains unchanged*

ELSE

; zeroing-masking

DEST[i+31:i] := 0

FI;

ENDFOR

DEST[MAXVL-1:VL] := 0

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INSTRUCTION SET REFERENCE, A-L

VCVTPS2DQ (VEX.256 Encoded Version)

DEST[31:0] := Convert_Single_Precision_Floating_Point_To_Integer(SRC[31:0])

DEST[63:32] := Convert_Single_Precision_Floating_Point_To_Integer(SRC[63:32])

DEST[95:64] := Convert_Single_Precision_Floating_Point_To_Integer(SRC[95:64])

DEST[127:96] := Convert_Single_Precision_Floating_Point_To_Integer(SRC[127:96)

DEST[159:128] := Convert_Single_Precision_Floating_Point_To_Integer(SRC[159:128])

DEST[191:160] := Convert_Single_Precision_Floating_Point_To_Integer(SRC[191:160])

DEST[223:192] := Convert_Single_Precision_Floating_Point_To_Integer(SRC[223:192])

DEST[255:224] := Convert_Single_Precision_Floating_Point_To_Integer(SRC[255:224])

VCVTPS2DQ (VEX.128 Encoded Version)

DEST[31:0] := Convert_Single_Precision_Floating_Point_To_Integer(SRC[31:0])

DEST[63:32] := Convert_Single_Precision_Floating_Point_To_Integer(SRC[63:32])

DEST[95:64] := Convert_Single_Precision_Floating_Point_To_Integer(SRC[95:64])

DEST[127:96] := Convert_Single_Precision_Floating_Point_To_Integer(SRC[127:96])

DEST[MAXVL-1:128] := 0

CVTPS2DQ (128-bit Legacy SSE Version)

DEST[31:0] := Convert_Single_Precision_Floating_Point_To_Integer(SRC[31:0])

DEST[63:32] := Convert_Single_Precision_Floating_Point_To_Integer(SRC[63:32])

DEST[95:64] := Convert_Single_Precision_Floating_Point_To_Integer(SRC[95:64])

DEST[127:96] := Convert_Single_Precision_Floating_Point_To_Integer(SRC[127:96])

DEST[MAXVL-1:128] (unmodified)

Intel C/C++ Compiler Intrinsic Equivalent

VCVTPS2DQ __m512i _mm512_cvtps_epi32( __m512 a);

VCVTPS2DQ __m512i _mm512_mask_cvtps_epi32( __m512i s, __mmask16 k, __m512 a);

VCVTPS2DQ __m512i _mm512_maskz_cvtps_epi32( __mmask16 k, __m512 a);

VCVTPS2DQ __m512i _mm512_cvt_roundps_epi32( __m512 a, int r);

VCVTPS2DQ __m512i _mm512_mask_cvt_roundps_epi32( __m512i s, __mmask16 k, __m512 a, int r);

VCVTPS2DQ __m512i _mm512_maskz_cvt_roundps_epi32( __mmask16 k, __m512 a, int r);

VCVTPS2DQ __m256i _mm256_mask_cvtps_epi32( __m256i s, __mmask8 k, __m256 a);

VCVTPS2DQ __m256i _mm256_maskz_cvtps_epi32( __mmask8 k, __m256 a);

VCVTPS2DQ __m128i _mm_mask_cvtps_epi32( __m128i s, __mmask8 k, __m128 a);

VCVTPS2DQ __m128i _mm_maskz_cvtps_epi32( __mmask8 k, __m128 a);

VCVTPS2DQ __ m256i _mm256_cvtps_epi32 (__m256 a)

CVTPS2DQ __m128i _mm_cvtps_epi32 (__m128 a)

SIMD Floating-Point Exceptions

Invalid, Precision.

Other Exceptions

VEX-encoded instructions, see Table 2-19, “Type 2 Class Exception Conditions.”

EVEX-encoded instructions, see Table 2-46, “Type E2 Class Exception Conditions.”

Additionally:

#UD

If VEX.vvvv != 1111B or EVEX.vvvv != 1111B.

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INSTRUCTION SET REFERENCE, A-L

CVTPS2PD-Convert Packed Single Precision Floating-Point Values to Packed Double Precision

Floating-Point Values

Opcode/

Op /

64/32 bit

CPUID

Description

Instruction

Mode

Feature Flag

Support

NP 0F 5A /r

V/V

SSE2

Convert two packed single precision floating-point values in

CVTPS2PD xmm1, xmm2/m64

xmm2/m64 to two packed double precision floating-point

values in xmm1.

VEX.128.0F.WIG 5A /r

V/V

AVX

Convert two packed single precision floating-point values in

VCVTPS2PD xmm1, xmm2/m64

xmm2/m64 to two packed double precision floating-point

values in xmm1.

VEX.256.0F.WIG 5A /r

V/V

AVX

Convert four packed single precision floating-point values in

VCVTPS2PD ymm1, xmm2/m128

xmm2/m128 to four packed double precision floating-point

values in ymm1.

EVEX.128.0F.W0 5A /r

V/V

AVX512VL

Convert two packed single precision floating-point values in

VCVTPS2PD xmm1 {k1}{z},

AVX512F

xmm2/m64/m32bcst to packed double precision floating-

xmm2/m64/m32bcst

point values in xmm1 with writemask k1.

EVEX.256.0F.W0 5A /r

V/V

AVX512VL

Convert four packed single precision floating-point values in

VCVTPS2PD ymm1 {k1}{z},

xmm2/m128/m32bcst to packed double precision floating-

xmm2/m128/m32bcst

point values in ymm1 with writemask k1.

EVEX.512.0F.W0 5A /r

V/V

AVX512F

Convert eight packed single precision floating-point values in

VCVTPS2PD zmm1 {k1}{z},

ymm2/m256/b32bcst to eight packed double precision

ymm2/m256/m32bcst{sae}

floating-point values in zmm1 with writemask k1.

Instruction Operand Encoding

Op/En

Tuple Type

Operand 1

Operand 2

Operand 3

Operand 4

N/A

ModRM:reg (w)

ModRM:r/m (r)

N/A

Half

ModRM:reg (w)

ModRM:r/m (r)

N/A

Description

Converts two, four or eight packed single precision floating-point values in the source operand (second operand) to

two, four or eight packed double precision floating-point values in the destination operand (first operand).

EVEX encoded versions: The source operand is a YMM/XMM/XMM (low 64-bits) register, a 256/128/64-bit memory

location or a 256/128/64-bit vector broadcasted from a 32-bit memory location. The destination operand is a

ZMM/YMM/XMM register conditionally updated with writemask k1.

VEX.256 encoded version: The source operand is an XMM register or 128- bit memory location. The destination

operand is a YMM register. Bits (MAXVL-1:256) of the corresponding destination ZMM register are zeroed.

VEX.128 encoded version: The source operand is an XMM register or 64- bit memory location. The destination

operand is a XMM register. The upper Bits (MAXVL-1:128) of the corresponding ZMM register destination are

zeroed.

128-bit Legacy SSE version: The source operand is an XMM register or 64- bit memory location. The destination

operand is an XMM register. The upper Bits (MAXVL-1:128) of the corresponding ZMM register destination are

unmodified.

Note: VEX.vvvv and EVEX.vvvv are reserved and must be 1111b otherwise instructions will #UD.

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INSTRUCTION SET REFERENCE, A-L

SRC

DEST

Figure 3-14. CVTPS2PD (VEX.256 encoded version)

Operation

VCVTPS2PD (EVEX Encoded Versions) When SRC Operand is a Register

(KL, VL) = (2, 128), (4, 256), (8, 512)

FOR j := 0 TO KL-1

i := j * 64

k := j * 32

IF k1[j] OR *no writemask*

THEN DEST[i+63:i] :=

Convert_Single_Precision_To_Double_Precision_Floating_Point(SRC[k+31:k])

ELSE

IF *merging-masking*

; merging-masking

THEN *DEST[i+63:i] remains unchanged*

ELSE

; zeroing-masking

DEST[i+63:i] := 0

FI;

ENDFOR

DEST[MAXVL-1:VL] := 0

VCVTPS2PD (EVEX Encoded Versions) When SRC Operand is a Memory Source

(KL, VL) = (2, 128), (4, 256), (8, 512)

FOR j := 0 TO KL-1

i := j * 64

k := j * 32

IF k1[j] OR *no writemask*

THEN

IF (EVEX.b = 1)

THEN

DEST[i+63:i] :=

Convert_Single_Precision_To_Double_Precision_Floating_Point(SRC[31:0])

ELSE

DEST[i+63:i] :=

Convert_Single_Precision_To_Double_Precision_Floating_Point(SRC[k+31:k])

FI;

ELSE

CVTPS2PD-Convert Packed Single Precision Floating-Point Values to Packed Double Precision Floating-Point Values

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INSTRUCTION SET REFERENCE, A-L

IF *merging-masking*

; merging-masking

THEN *DEST[i+63:i] remains unchanged*

ELSE

; zeroing-masking

DEST[i+63:i] := 0

FI;

ENDFOR

DEST[MAXVL-1:VL] := 0

VCVTPS2PD (VEX.256 Encoded Version)

DEST[63:0] := Convert_Single_Precision_To_Double_Precision_Floating_Point(SRC[31:0])

DEST[127:64] := Convert_Single_Precision_To_Double_Precision_Floating_Point(SRC[63:32])

DEST[191:128] := Convert_Single_Precision_To_Double_Precision_Floating_Point(SRC[95:64])

DEST[255:192] := Convert_Single_Precision_To_Double_Precision_Floating_Point(SRC[127:96)

DEST[MAXVL-1:256] := 0

VCVTPS2PD (VEX.128 Encoded Version)

DEST[63:0] := Convert_Single_Precision_To_Double_Precision_Floating_Point(SRC[31:0])

DEST[127:64] := Convert_Single_Precision_To_Double_Precision_Floating_Point(SRC[63:32])

DEST[MAXVL-1:128] := 0

CVTPS2PD (128-bit Legacy SSE Version)

DEST[63:0] := Convert_Single_Precision_To_Double_Precision_Floating_Point(SRC[31:0])

DEST[127:64] := Convert_Single_Precision_To_Double_Precision_Floating_Point(SRC[63:32])

DEST[MAXVL-1:128] (unmodified)

Intel C/C++ Compiler Intrinsic Equivalent

VCVTPS2PD __m512d _mm512_cvtps_pd( __m256 a);

VCVTPS2PD __m512d _mm512_mask_cvtps_pd( __m512d s, __mmask8 k, __m256 a);

VCVTPS2PD __m512d _mm512_maskz_cvtps_pd( __mmask8 k, __m256 a);

VCVTPS2PD __m512d _mm512_cvt_roundps_pd( __m256 a, int sae);

VCVTPS2PD __m512d _mm512_mask_cvt_roundps_pd( __m512d s, __mmask8 k, __m256 a, int sae);

VCVTPS2PD __m512d _mm512_maskz_cvt_roundps_pd( __mmask8 k, __m256 a, int sae);

VCVTPS2PD __m256d _mm256_mask_cvtps_pd( __m256d s, __mmask8 k, __m128 a);

VCVTPS2PD __m256d _mm256_maskz_cvtps_pd( __mmask8 k, __m128a);

VCVTPS2PD __m128d _mm_mask_cvtps_pd( __m128d s, __mmask8 k, __m128 a);

VCVTPS2PD __m128d _mm_maskz_cvtps_pd( __mmask8 k, __m128 a);

VCVTPS2PD __m256d _mm256_cvtps_pd (__m128 a)

CVTPS2PD __m128d _mm_cvtps_pd (__m128 a)

SIMD Floating-Point Exceptions

Invalid, Denormal.

Other Exceptions

VEX-encoded instructions, see Table 2-20, “Type 3 Class Exception Conditions.”

EVEX-encoded instructions, see Table 2-47, “Type E3 Class Exception Conditions.”

Additionally:

#UD

If VEX.vvvv != 1111B or EVEX.vvvv != 1111B.

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INSTRUCTION SET REFERENCE, A-L

CVTPS2PI-Convert Packed Single Precision Floating-Point Values to Packed Dword Integers

Opcode/

Op/

64-Bit

Compat/

Description

Instruction

Mode

Leg Mode

NP 0F 2D /r

Valid

Convert two packed single precision floating-

point values from xmm/m64 to two packed

CVTPS2PI mm, xmm/m64

signed doubleword integers in mm.

Instruction Operand Encoding

Op/En

Operand 1

Operand 2

Operand 3

Operand 4

ModRM:reg (w)

ModRM:r/m (r)

N/A

Description

Converts two packed single precision floating-point values in the source operand (second operand) to two packed

signed doubleword integers in the destination operand (first operand).

The source operand can be an XMM register or a 128-bit memory location. The destination operand is an MMX tech-

nology register. When the source operand is an XMM register, the two single precision floating-point values are

contained in the low quadword of the register. When a conversion is inexact, the value returned is rounded

according to the rounding control bits in the MXCSR register. If a converted result is larger than the maximum

signed doubleword integer, the floating-point invalid exception is raised, and if this exception is masked, the indef-

inite integer value (80000000H) is returned.

CVTPS2PI causes a transition from x87 FPU to MMX technology operation (that is, the x87 FPU top-of-stack pointer

is set to 0 and the x87 FPU tag word is set to all 0s [valid]). If this instruction is executed while an x87 FPU floating-

point exception is pending, the exception is handled before the CVTPS2PI instruction is executed.

In 64-bit mode, use of the REX.R prefix permits this instruction to access additional registers (XMM8-XMM15).

Operation

DEST[31:0] := Convert_Single_Precision_Floating_Point_To_Integer(SRC[31:0]);

DEST[63:32] := Convert_Single_Precision_Floating_Point_To_Integer(SRC[63:32]);

Intel C/C++ Compiler Intrinsic Equivalent

CVTPS2PI __m64 _mm_cvtps_pi32(__m128 a)

SIMD Floating-Point Exceptions

Invalid, Precision.

Other Exceptions

See Table 23-5, “Exception Conditions for Legacy SIMD/MMX Instructions with XMM and FP Exception,” in the

Intel^® 64 and IA-32 Architectures Software Developer’s Manual, Volume 3B.

CVTPS2PI-Convert Packed Single Precision Floating-Point Values to Packed Dword Integers

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INSTRUCTION SET REFERENCE, A-L

CVTSD2SI-Convert Scalar Double Precision Floating-Point Value to Doubleword Integer

Opcode/

Op /

64/32 bit

CPUID

Description

Instruction

Mode

Feature

Support

Flag

F2 0F 2D /r

V/V

SSE2

Convert one double precision floating-point value from

CVTSD2SI r32, xmm1/m64

xmm1/m64 to one signed doubleword integer r32.

F2 REX.W 0F 2D /r

V/N.E.

SSE2

Convert one double precision floating-point value from

CVTSD2SI r64, xmm1/m64

xmm1/m64 to one signed quadword integer sign-

extended into r64.

VEX.LIG.F2.0F.W0 2D /r ¹

V/V

AVX

Convert one double precision floating-point value from

VCVTSD2SI r32, xmm1/m64

xmm1/m64 to one signed doubleword integer r32.

VEX.LIG.F2.0F.W1 2D /r ¹

V/N.E.²

AVX

Convert one double precision floating-point value from

VCVTSD2SI r64, xmm1/m64

xmm1/m64 to one signed quadword integer sign-

extended into r64.

EVEX.LLIG.F2.0F.W0 2D /r

V/V

AVX512F

Convert one double precision floating-point value from

VCVTSD2SI r32, xmm1/m64{er}

xmm1/m64 to one signed doubleword integer r32.

EVEX.LLIG.F2.0F.W1 2D /r

V/N.E.²

AVX512F

Convert one double precision floating-point value from

VCVTSD2SI r64, xmm1/m64{er}

xmm1/m64 to one signed quadword integer sign-

extended into r64.

NOTES:

1. Software should ensure VCVTSD2SI is encoded with VEX.L=0. Encoding VCVTSD2SI with VEX.L=1 may encounter unpredictable

behavior across different processor generations.

2. VEX.W1/EVEX.W1 in non-64 bit is ignored; the instructions behaves as if the W0 version is used.

Instruction Operand Encoding

Op/En

Tuple Type

Operand 1

Operand 2

Operand 3

Operand 4

N/A

ModRM:reg (w)

ModRM:r/m (r)

N/A

Tuple1 Fixed

ModRM:reg (w)

ModRM:r/m (r)

N/A

Description

Converts a double precision floating-point value in the source operand (the second operand) to a signed double-

word integer in the destination operand (first operand). The source operand can be an XMM register or a 64-bit

memory location. The destination operand is a general-purpose register. When the source operand is an XMM

When a conversion is inexact, the value returned is rounded according to the rounding control bits in the MXCSR

If a converted result exceeds the range limits of signed doubleword integer (in non-64-bit modes or 64-bit mode

with REX.W/VEX.W/EVEX.W=0), the floating-point invalid exception is raised, and if this exception is masked, the

indefinite integer value (80000000H) is returned.

If a converted result exceeds the range limits of signed quadword integer (in 64-bit mode and

REX.W/VEX.W/EVEX.W = 1), the floating-point invalid exception is raised, and if this exception is masked, the

indefinite integer value (80000000_00000000H) is returned.

Legacy SSE instruction: Use of the REX.W prefix promotes the instruction to produce 64-bit data in 64-bit mode.

See the summary chart at the beginning of this section for encoding data and limits.

Note: VEX.vvvv and EVEX.vvvv are reserved and must be 1111b, otherwise instructions will #UD.

Software should ensure VCVTSD2SI is encoded with VEX.L=0. Encoding VCVTSD2SI with VEX.L=1 may encounter

unpredictable behavior across different processor generations.

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INSTRUCTION SET REFERENCE, A-L

Operation

VCVTSD2SI (EVEX Encoded Version)

IF SRC *is register* AND (EVEX.b = 1)

THEN

SET_ROUNDING_MODE_FOR_THIS_INSTRUCTION(EVEX.RC);

ELSE

SET_ROUNDING_MODE_FOR_THIS_INSTRUCTION(MXCSR.RC);

FI;

IF 64-Bit Mode and OperandSize = 64

THEN

DEST[63:0] := Convert_Double_Precision_Floating_Point_To_Integer(SRC[63:0]);

ELSE

DEST[31:0] := Convert_Double_Precision_Floating_Point_To_Integer(SRC[63:0]);

(V)CVTSD2SI

IF 64-Bit Mode and OperandSize = 64

THEN

DEST[63:0] := Convert_Double_Precision_Floating_Point_To_Integer(SRC[63:0]);

ELSE

DEST[31:0] := Convert_Double_Precision_Floating_Point_To_Integer(SRC[63:0]);

FI;

Intel C/C++ Compiler Intrinsic Equivalent

VCVTSD2SI int _mm_cvtsd_i32(__m128d);

VCVTSD2SI int _mm_cvt_roundsd_i32(__m128d, int r);

VCVTSD2SI __int64 _mm_cvtsd_i64(__m128d);

VCVTSD2SI __int64 _mm_cvt_roundsd_i64(__m128d, int r);

CVTSD2SI __int64 _mm_cvtsd_si64(__m128d);

CVTSD2SI int _mm_cvtsd_si32(__m128d a)

SIMD Floating-Point Exceptions

Invalid, Precision.

Other Exceptions

VEX-encoded instructions, see Table 2-20, “Type 3 Class Exception Conditions.”

EVEX-encoded instructions, see Table 2-48, “Type E3NF Class Exception Conditions.”

Additionally:

#UD

If VEX.vvvv != 1111B or EVEX.vvvv != 1111B.

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INSTRUCTION SET REFERENCE, A-L

CVTSD2SS-Convert Scalar Double Precision Floating-Point Value to Scalar Single Precision

Floating-Point Value

Opcode/

Op /

64/32 bit

CPUID

Description

Instruction

Mode

Feature

Support

Flag

F2 0F 5A /r

V/V

SSE2

Convert one double precision floating-point value in

CVTSD2SS xmm1, xmm2/m64

xmm2/m64 to one single precision floating-point value in

xmm1.

VEX.LIG.F2.0F.WIG 5A /r

V/V

AVX

Convert one double precision floating-point value in

VCVTSD2SS xmm1,xmm2, xmm3/m64

xmm3/m64 to one single precision floating-point value

and merge with high bits in xmm2.

EVEX.LLIG.F2.0F.W1 5A /r

V/V

AVX512F

Convert one double precision floating-point value in

VCVTSD2SS xmm1 {k1}{z}, xmm2,

xmm3/m64 to one single precision floating-point value

xmm3/m64{er}

and merge with high bits in xmm2 under writemask k1.

Instruction Operand Encoding

Op/En

Tuple Type

Operand 1

Operand 2

Operand 3

Operand 4

N/A

ModRM:reg (r, w)

ModRM:r/m (r)

N/A

ModRM:reg (w)

VEX.vvvv (r)

ModRM:r/m (r)

N/A

Tuple1 Scalar

ModRM:reg (w)

EVEX.vvvv (r)

ModRM:r/m (r)

N/A

Description

Converts a double precision floating-point value in the “convert-from” source operand (the second operand in SSE2

version, otherwise the third operand) to a single precision floating-point value in the destination operand.

When the “convert-from” operand is an XMM register, the double precision floating-point value is contained in the

low quadword of the register. The result is stored in the low doubleword of the destination operand. When the

conversion is inexact, the value returned is rounded according to the rounding control bits in the MXCSR register.

128-bit Legacy SSE version: The “convert-from” source operand (the second operand) is an XMM register or

memory location. Bits (MAXVL-1:32) of the corresponding destination register remain unchanged. The destination

operand is an XMM register.

VEX.128 and EVEX encoded versions: The “convert-from” source operand (the third operand) can be an XMM

the XMM register destination are copied from the corresponding bits in the first source operand. Bits (MAXVL-

1:128) of the destination register are zeroed.

EVEX encoded version: the converted result in written to the low doubleword element of the destination under the

writemask.

Software should ensure VCVTSD2SS is encoded with VEX.L=0. Encoding VCVTSD2SS with VEX.L=1 may encounter

unpredictable behavior across different processor generations.

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INSTRUCTION SET REFERENCE, A-L

Operation

VCVTSD2SS (EVEX Encoded Version)

IF (SRC2 *is register*) AND (EVEX.b = 1)

THEN

SET_ROUNDING_MODE_FOR_THIS_INSTRUCTION(EVEX.RC);

ELSE

SET_ROUNDING_MODE_FOR_THIS_INSTRUCTION(MXCSR.RC);

FI;

IF k1[0] or *no writemask*

THEN

DEST[31:0] := Convert_Double_Precision_To_Single_Precision_Floating_Point(SRC2[63:0]);

ELSE

IF *merging-masking*

; merging-masking

THEN *DEST[31:0] remains unchanged*

ELSE

; zeroing-masking

THEN DEST[31:0] := 0

FI;

DEST[127:32] := SRC1[127:32]

DEST[MAXVL-1:128] := 0

VCVTSD2SS (VEX.128 Encoded Version)

DEST[31:0] := Convert_Double_Precision_To_Single_Precision_Floating_Point(SRC2[63:0]);

DEST[127:32] := SRC1[127:32]

DEST[MAXVL-1:128] := 0

CVTSD2SS (128-bit Legacy SSE Version)

DEST[31:0] := Convert_Double_Precision_To_Single_Precision_Floating_Point(SRC[63:0]);

(* DEST[MAXVL-1:32] Unmodified *)

Intel C/C++ Compiler Intrinsic Equivalent

VCVTSD2SS __m128 _mm_mask_cvtsd_ss(__m128 s, __mmask8 k, __m128 a, __m128d b);

VCVTSD2SS __m128 _mm_maskz_cvtsd_ss( __mmask8 k, __m128 a,__m128d b);

VCVTSD2SS __m128 _mm_cvt_roundsd_ss(__m128 a, __m128d b, int r);

VCVTSD2SS __m128 _mm_mask_cvt_roundsd_ss(__m128 s, __mmask8 k, __m128 a, __m128d b, int r);

VCVTSD2SS __m128 _mm_maskz_cvt_roundsd_ss( __mmask8 k, __m128 a,__m128d b, int r);

CVTSD2SS __m128_mm_cvtsd_ss(__m128 a, __m128d b)

SIMD Floating-Point Exceptions

Overflow, Underflow, Invalid, Precision, Denormal.

Other Exceptions

VEX-encoded instructions, see Table 2-20, “Type 3 Class Exception Conditions.”

EVEX-encoded instructions, see Table 2-47, “Type E3 Class Exception Conditions.”

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INSTRUCTION SET REFERENCE, A-L

CVTSI2SD-Convert Doubleword Integer to Scalar Double Precision Floating-Point Value

Opcode/

Op /

64/32 bit

CPUID

Description

Instruction

Mode

Feature

Support

Flag

F2 0F 2A /r

V/V

SSE2

Convert one signed doubleword integer from

CVTSI2SD xmm1, r32/m32

r32/m32 to one double precision floating-point

value in xmm1.

F2 REX.W 0F 2A /r

V/N.E.

SSE2

Convert one signed quadword integer from r/m64

CVTSI2SD xmm1, r/m64

to one double precision floating-point value in

xmm1.

VEX.LIG.F2.0F.W0 2A /r

V/V

AVX

Convert one signed doubleword integer from

VCVTSI2SD xmm1, xmm2, r/m32

r/m32 to one double precision floating-point value

in xmm1.

VEX.LIG.F2.0F.W1 2A /r

V/N.E.¹

AVX

Convert one signed quadword integer from r/m64

VCVTSI2SD xmm1, xmm2, r/m64

to one double precision floating-point value in

xmm1.

EVEX.LLIG.F2.0F.W0 2A /r

V/V

AVX512F

Convert one signed doubleword integer from

VCVTSI2SD xmm1, xmm2, r/m32

r/m32 to one double precision floating-point value

in xmm1.

EVEX.LLIG.F2.0F.W1 2A /r

V/N.E.¹

AVX512F

Convert one signed quadword integer from r/m64

VCVTSI2SD xmm1, xmm2, r/m64{er}

to one double precision floating-point value in

xmm1.

NOTES:

1. VEX.W1/EVEX.W1 in non-64 bit is ignored; the instructions behaves as if the W0 version is used.

Instruction Operand Encoding

Op/En

Tuple Type

Operand 1

Operand 2

Operand 3

Operand 4

N/A

ModRM:reg (w)

ModRM:r/m (r)

N/A

ModRM:reg (w)

VEX.vvvv (r)

ModRM:r/m (r)

N/A

Tuple1 Scalar

ModRM:reg (w)

EVEX.vvvv (r)

ModRM:r/m (r)

N/A

Description

Converts a signed doubleword integer (or signed quadword integer if operand size is 64 bits) in the “convert-from”

source operand to a double precision floating-point value in the destination operand. The result is stored in the low

quadword of the destination operand, and the high quadword left unchanged. When conversion is inexact, the

value returned is rounded according to the rounding control bits in the MXCSR register.

The second source operand can be a general-purpose register or a 32/64-bit memory location. The first source and

destination operands are XMM registers.

128-bit Legacy SSE version: Use of the REX.W prefix promotes the instruction to 64-bit operands. The “convert-

from” source operand (the second operand) is a general-purpose register or memory location. The destination is an

XMM register Bits (MAXVL-1:64) of the corresponding destination register remain unchanged.

VEX.128 and EVEX encoded versions: The “convert-from” source operand (the third operand) can be a general-

purpose register or a memory location. The first source and destination operands are XMM registers. Bits (127:64)

of the XMM register destination are copied from the corresponding bits in the first source operand. Bits (MAXVL-

1:128) of the destination register are zeroed.

EVEX.W0 version: attempt to encode this instruction with EVEX embedded rounding is ignored.

VEX.W1 and EVEX.W1 versions: promotes the instruction to use 64-bit input value in 64-bit mode.

Software should ensure VCVTSI2SD is encoded with VEX.L=0. Encoding VCVTSI2SD with VEX.L=1 may encounter

unpredictable behavior across different processor generations.

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INSTRUCTION SET REFERENCE, A-L

Operation

VCVTSI2SD (EVEX Encoded Version)

IF (SRC2 *is register*) AND (EVEX.b = 1)

THEN

SET_ROUNDING_MODE_FOR_THIS_INSTRUCTION(EVEX.RC);

ELSE

SET_ROUNDING_MODE_FOR_THIS_INSTRUCTION(MXCSR.RC);

FI;

IF 64-Bit Mode And OperandSize = 64

THEN

DEST[63:0] := Convert_Integer_To_Double_Precision_Floating_Point(SRC2[63:0]);

ELSE

DEST[63:0] := Convert_Integer_To_Double_Precision_Floating_Point(SRC2[31:0]);

FI;

DEST[127:64] := SRC1[127:64]

DEST[MAXVL-1:128] := 0

VCVTSI2SD (VEX.128 Encoded Version)

IF 64-Bit Mode And OperandSize = 64

THEN

DEST[63:0] := Convert_Integer_To_Double_Precision_Floating_Point(SRC2[63:0]);

ELSE

DEST[63:0] := Convert_Integer_To_Double_Precision_Floating_Point(SRC2[31:0]);

FI;

DEST[127:64] := SRC1[127:64]

DEST[MAXVL-1:128] := 0

CVTSI2SD

IF 64-Bit Mode And OperandSize = 64

THEN

DEST[63:0] := Convert_Integer_To_Double_Precision_Floating_Point(SRC[63:0]);

ELSE

DEST[63:0] := Convert_Integer_To_Double_Precision_Floating_Point(SRC[31:0]);

FI;

DEST[MAXVL-1:64] (Unmodified)

Intel C/C++ Compiler Intrinsic Equivalent

VCVTSI2SD __m128d _mm_cvti32_sd(__m128d s, int a);

VCVTSI2SD __m128d _mm_cvti64_sd(__m128d s, __int64 a);

VCVTSI2SD __m128d _mm_cvt_roundi64_sd(__m128d s, __int64 a, int r);

CVTSI2SD __m128d _mm_cvtsi64_sd(__m128d s, __int64 a);

CVTSI2SD __m128d_mm_cvtsi32_sd(__m128d a, int b)

SIMD Floating-Point Exceptions

Precision.

Other Exceptions

VEX-encoded instructions, see Table 2-20, “Type 3 Class Exception Conditions,” if W1; else see Table 2-22, “Type

5 Class Exception Conditions.”

EVEX-encoded instructions, see Table 2-48, “Type E3NF Class Exception Conditions,” if W1; else see Table 2-59,

“Type E10NF Class Exception Conditions.”

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INSTRUCTION SET REFERENCE, A-L

CVTSI2SS-Convert Doubleword Integer to Scalar Single Precision Floating-Point Value

Opcode/

Op /

64/32 bit

CPUID

Description

Instruction

Mode

Feature

Support

Flag

F3 0F 2A /r

V/V

SSE

Convert one signed doubleword integer from r/m32

CVTSI2SS xmm1, r/m32

to one single precision floating-point value in xmm1.

F3 REX.W 0F 2A /r

V/N.E.

SSE

Convert one signed quadword integer from r/m64 to

CVTSI2SS xmm1, r/m64

one single precision floating-point value in xmm1.

VEX.LIG.F3.0F.W0 2A /r

V/V

AVX

Convert one signed doubleword integer from r/m32

VCVTSI2SS xmm1, xmm2, r/m32

to one single precision floating-point value in xmm1.

VEX.LIG.F3.0F.W1 2A /r

V/N.E.¹

AVX

Convert one signed quadword integer from r/m64 to

VCVTSI2SS xmm1, xmm2, r/m64

one single precision floating-point value in xmm1.

EVEX.LLIG.F3.0F.W0 2A /r

V/V

AVX512F

Convert one signed doubleword integer from r/m32

VCVTSI2SS xmm1, xmm2, r/m32{er}

to one single precision floating-point value in xmm1.

EVEX.LLIG.F3.0F.W1 2A /r

V/N.E.¹

AVX512F

Convert one signed quadword integer from r/m64 to

VCVTSI2SS xmm1, xmm2, r/m64{er}

one single precision floating-point value in xmm1.

NOTES:

1. VEX.W1/EVEX.W1 in non-64 bit is ignored; the instructions behaves as if the W0 version is used.

Instruction Operand Encoding

Op/En

Tuple Type

Operand 1

Operand 2

Operand 3

Operand 4

N/A

ModRM:reg (w)

ModRM:r/m (r)

N/A

ModRM:reg (w)

VEX.vvvv (r)

ModRM:r/m (r)

N/A

Tuple1 Scalar

ModRM:reg (w)

EVEX.vvvv (r)

ModRM:r/m (r)

N/A

Description

Converts a signed doubleword integer (or signed quadword integer if operand size is 64 bits) in the “convert-from”

source operand to a single precision floating-point value in the destination operand (first operand). The “convert-

from” source operand can be a general-purpose register or a memory location. The destination operand is an XMM

are left unchanged. When a conversion is inexact, the value returned is rounded according to the rounding control

bits in the MXCSR register or the embedded rounding control bits.

128-bit Legacy SSE version: In 64-bit mode, Use of the REX.W prefix promotes the instruction to use 64-bit input

value. The “convert-from” source operand (the second operand) is a general-purpose register or memory location.

Bits (MAXVL-1:32) of the corresponding destination register remain unchanged.

VEX.128 and EVEX encoded versions: The “convert-from” source operand (the third operand) can be a general-

purpose register or a memory location. The first source and destination operands are XMM registers. Bits (127:32)

of the XMM register destination are copied from corresponding bits in the first source operand. Bits (MAXVL-1:128)

of the destination register are zeroed.

EVEX encoded version: the converted result in written to the low doubleword element of the destination under the

writemask.

Software should ensure VCVTSI2SS is encoded with VEX.L=0. Encoding VCVTSI2SS with VEX.L=1 may encounter

unpredictable behavior across different processor generations.

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INSTRUCTION SET REFERENCE, A-L

Operation

VCVTSI2SS (EVEX Encoded Version)

IF (SRC2 *is register*) AND (EVEX.b = 1)

THEN

SET_ROUNDING_MODE_FOR_THIS_INSTRUCTION(EVEX.RC);

ELSE

SET_ROUNDING_MODE_FOR_THIS_INSTRUCTION(MXCSR.RC);

FI;

IF 64-Bit Mode And OperandSize = 64

THEN

DEST[31:0] := Convert_Integer_To_Single_Precision_Floating_Point(SRC[63:0]);

ELSE

DEST[31:0] := Convert_Integer_To_Single_Precision_Floating_Point(SRC[31:0]);

FI;

DEST[127:32] := SRC1[127:32]

DEST[MAXVL-1:128] := 0

VCVTSI2SS (VEX.128 Encoded Version)

IF 64-Bit Mode And OperandSize = 64

THEN

DEST[31:0] := Convert_Integer_To_Single_Precision_Floating_Point(SRC[63:0]);

ELSE

DEST[31:0] := Convert_Integer_To_Single_Precision_Floating_Point(SRC[31:0]);

FI;

DEST[127:32] := SRC1[127:32]

DEST[MAXVL-1:128] := 0

CVTSI2SS (128-bit Legacy SSE Version)

IF 64-Bit Mode And OperandSize = 64

THEN

DEST[31:0] := Convert_Integer_To_Single_Precision_Floating_Point(SRC[63:0]);

ELSE

DEST[31:0] :=Convert_Integer_To_Single_Precision_Floating_Point(SRC[31:0]);

FI;

DEST[MAXVL-1:32] (Unmodified)

Intel C/C++ Compiler Intrinsic Equivalent

VCVTSI2SS __m128 _mm_cvti32_ss(__m128 s, int a);

VCVTSI2SS __m128 _mm_cvt_roundi32_ss(__m128 s, int a, int r);

VCVTSI2SS __m128 _mm_cvti64_ss(__m128 s, __int64 a);

VCVTSI2SS __m128 _mm_cvt_roundi64_ss(__m128 s, __int64 a, int r);

CVTSI2SS __m128 _mm_cvtsi64_ss(__m128 s, __int64 a);

CVTSI2SS __m128 _mm_cvtsi32_ss(__m128 a, int b);

SIMD Floating-Point Exceptions

Precision.

Other Exceptions

VEX-encoded instructions, see Table 2-20, “Type 3 Class Exception Conditions.”

EVEX-encoded instructions, see Table 2-48, “Type E3NF Class Exception Conditions.”

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INSTRUCTION SET REFERENCE, A-L

CVTSS2SD-Convert Scalar Single Precision Floating-Point Value to Scalar Double Precision

Floating-Point Value

Opcode/

Op /

64/32 bit

CPUID

Description

Instruction

Mode

Feature

Support

Flag

F3 0F 5A /r

V/V

SSE2

Convert one single precision floating-point value in

CVTSS2SD xmm1, xmm2/m32

xmm2/m32 to one double precision floating-point value in

xmm1.

VEX.LIG.F3.0F.WIG 5A /r

V/V

AVX

Convert one single precision floating-point value in

VCVTSS2SD xmm1, xmm2,

xmm3/m32 to one double precision floating-point value

xmm3/m32

and merge with high bits of xmm2.

EVEX.LLIG.F3.0F.W0 5A /r

V/V

AVX512F

Convert one single precision floating-point value in

VCVTSS2SD xmm1 {k1}{z}, xmm2,

xmm3/m32 to one double precision floating-point value

xmm3/m32{sae}

and merge with high bits of xmm2 under writemask k1.

Instruction Operand Encoding

Op/En

Tuple Type

Operand 1

Operand 2

Operand 3

Operand 4

N/A

ModRM:reg (r, w)

ModRM:r/m (r)

N/A

ModRM:reg (w)

VEX.vvvv (r)

ModRM:r/m (r)

N/A

Tuple1 Scalar

ModRM:reg (w)

EVEX.vvvv (r)

ModRM:r/m (r)

N/A

Description

Converts a single precision floating-point value in the “convert-from” source operand to a double precision floating-

point value in the destination operand. When the “convert-from” source operand is an XMM register, the single

precision floating-point value is contained in the low doubleword of the register. The result is stored in the low

quadword of the destination operand.

128-bit Legacy SSE version: The “convert-from” source operand (the second operand) is an XMM register or

memory location. Bits (MAXVL-1:64) of the corresponding destination register remain unchanged. The destination

operand is an XMM register.

VEX.128 and EVEX encoded versions: The “convert-from” source operand (the third operand) can be an XMM

the XMM register destination are copied from the corresponding bits in the first source operand. Bits (MAXVL-

1:128) of the destination register are zeroed.

Software should ensure VCVTSS2SD is encoded with VEX.L=0. Encoding VCVTSS2SD with VEX.L=1 may encounter

unpredictable behavior across different processor generations.

Operation

VCVTSS2SD (EVEX Encoded Version)

IF k1[0] or *no writemask*

THEN

DEST[63:0] := Convert_Single_Precision_To_Double_Precision_Floating_Point(SRC2[31:0]);

ELSE

IF *merging-masking*

; merging-masking

THEN *DEST[63:0] remains unchanged*

ELSE

; zeroing-masking

THEN DEST[63:0] = 0

FI;

DEST[127:64] := SRC1[127:64]

DEST[MAXVL-1:128] := 0

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INSTRUCTION SET REFERENCE, A-L

VCVTSS2SD (VEX.128 Encoded Version)

DEST[63:0] := Convert_Single_Precision_To_Double_Precision_Floating_Point(SRC2[31:0])

DEST[127:64] := SRC1[127:64]

DEST[MAXVL-1:128] := 0

CVTSS2SD (128-bit Legacy SSE Version)

DEST[63:0] := Convert_Single_Precision_To_Double_Precision_Floating_Point(SRC[31:0]);

DEST[MAXVL-1:64] (Unmodified)

Intel C/C++ Compiler Intrinsic Equivalent

VCVTSS2SD __m128d _mm_cvt_roundss_sd(__m128d a, __m128 b, int r);

VCVTSS2SD __m128d _mm_mask_cvt_roundss_sd(__m128d s, __mmask8 m, __m128d a,__m128 b, int r);

VCVTSS2SD __m128d _mm_maskz_cvt_roundss_sd(__mmask8 k, __m128d a, __m128 a, int r);

VCVTSS2SD __m128d _mm_mask_cvtss_sd(__m128d s, __mmask8 m, __m128d a,__m128 b);

VCVTSS2SD __m128d _mm_maskz_cvtss_sd(__mmask8 m, __m128d a,__m128 b);

CVTSS2SD __m128d_mm_cvtss_sd(__m128d a, __m128 a);

SIMD Floating-Point Exceptions

Invalid, Denormal.

Other Exceptions

VEX-encoded instructions, see Table 2-20, “Type 3 Class Exception Conditions.”

EVEX-encoded instructions, see Table 2-47, “Type E3 Class Exception Conditions.”

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INSTRUCTION SET REFERENCE, A-L

CVTSS2SI-Convert Scalar Single Precision Floating-Point Value to Doubleword Integer

Opcode/

Op /

64/32 bit

CPUID

Description

Instruction

Mode

Feature

Support

Flag

F3 0F 2D /r

V/V

SSE

Convert one single precision floating-point value from

CVTSS2SI r32, xmm1/m32

xmm1/m32 to one signed doubleword integer in r32.

F3 REX.W 0F 2D /r

V/N.E.

SSE

Convert one single precision floating-point value from

CVTSS2SI r64, xmm1/m32

xmm1/m32 to one signed quadword integer in r64.

VEX.LIG.F3.0F.W0 2D /r ¹

V/V

AVX

Convert one single precision floating-point value from

VCVTSS2SI r32, xmm1/m32

xmm1/m32 to one signed doubleword integer in r32.

VEX.LIG.F3.0F.W1 2D /r ¹

V/N.E.²

AVX

Convert one single precision floating-point value from

VCVTSS2SI r64, xmm1/m32

xmm1/m32 to one signed quadword integer in r64.

EVEX.LLIG.F3.0F.W0 2D /r

V/V

AVX512F

Convert one single precision floating-point value from

VCVTSS2SI r32, xmm1/m32{er}

xmm1/m32 to one signed doubleword integer in r32.

EVEX.LLIG.F3.0F.W1 2D /r

V/N.E.²

AVX512F

Convert one single precision floating-point value from

VCVTSS2SI r64, xmm1/m32{er}

xmm1/m32 to one signed quadword integer in r64.

NOTES:

1. Software should ensure VCVTSS2SI is encoded with VEX.L=0. Encoding VCVTSS2SI with VEX.L=1 may

encounter unpredictable behavior across different processor generations.

2. VEX.W1/EVEX.W1 in non-64 bit is ignored; the instructions behaves as if the W0 version is used.

Instruction Operand Encoding

Op/En

Tuple Type

Operand 1

Operand 2

Operand 3

Operand 4

N/A

ModRM:reg (w)

ModRM:r/m (r)

N/A

Tuple1 Fixed

ModRM:reg (w)

ModRM:r/m (r)

N/A

Description

Converts a single precision floating-point value in the source operand (the second operand) to a signed doubleword

integer (or signed quadword integer if operand size is 64 bits) in the destination operand (the first operand). The

source operand can be an XMM register or a memory location. The destination operand is a general-purpose

low doubleword of the register.

When a conversion is inexact, the value returned is rounded according to the rounding control bits in the MXCSR

format, the floating-point invalid exception is raised, and if this exception is masked, the indefinite integer value

(2^w-1, where w represents the number of bits in the destination format) is returned.

Legacy SSE instructions: In 64-bit mode, Use of the REX.W prefix promotes the instruction to produce 64-bit data.

See the summary chart at the beginning of this section for encoding data and limits.

VEX.W1 and EVEX.W1 versions: promotes the instruction to produce 64-bit data in 64-bit mode.

Note: VEX.vvvv and EVEX.vvvv are reserved and must be 1111b, otherwise instructions will #UD.

Software should ensure VCVTSS2SI is encoded with VEX.L=0. Encoding VCVTSS2SI with VEX.L=1 may encounter

unpredictable behavior across different processor generations.

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INSTRUCTION SET REFERENCE, A-L

Operation

VCVTSS2SI (EVEX Encoded Version)

IF (SRC *is register*) AND (EVEX.b = 1)

THEN

SET_ROUNDING_MODE_FOR_THIS_INSTRUCTION(EVEX.RC);

ELSE

SET_ROUNDING_MODE_FOR_THIS_INSTRUCTION(MXCSR.RC);

FI;

IF 64-bit Mode and OperandSize = 64

THEN

DEST[63:0] := Convert_Single_Precision_Floating_Point_To_Integer(SRC[31:0]);

ELSE

DEST[31:0] := Convert_Single_Precision_Floating_Point_To_Integer(SRC[31:0]);

FI;

(V)CVTSS2SI (Legacy and VEX.128 Encoded Version)

IF 64-bit Mode and OperandSize = 64

THEN

DEST[63:0] := Convert_Single_Precision_Floating_Point_To_Integer(SRC[31:0]);

ELSE

DEST[31:0] := Convert_Single_Precision_Floating_Point_To_Integer(SRC[31:0]);

FI;

Intel C/C++ Compiler Intrinsic Equivalent

VCVTSS2SI int _mm_cvtss_i32( __m128 a);

VCVTSS2SI int _mm_cvt_roundss_i32( __m128 a, int r);

VCVTSS2SI __int64 _mm_cvtss_i64( __m128 a);

VCVTSS2SI __int64 _mm_cvt_roundss_i64( __m128 a, int r);

SIMD Floating-Point Exceptions

Invalid, Precision.

Other Exceptions

VEX-encoded instructions, see Table 2-20, “Type 3 Class Exception Conditions,” additionally:

#UD

If VEX.vvvv != 1111B.

EVEX-encoded instructions, see Table 2-48, “Type E3NF Class Exception Conditions.”

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INSTRUCTION SET REFERENCE, A-L

CVTTPD2DQ-Convert with Truncation Packed Double Precision Floating-Point Values to Packed

Doubleword Integers

Opcode/

Op /

64/32 bit

CPUID

Description

Instruction

Mode

Feature

Support

Flag

66 0F E6 /r

V/V

SSE2

Convert two packed double precision floating-point

CVTTPD2DQ xmm1, xmm2/m128

values in xmm2/mem to two signed doubleword integers

in xmm1 using truncation.

VEX.128.66.0F.WIG E6 /r

V/V

AVX

Convert two packed double precision floating-point

VCVTTPD2DQ xmm1, xmm2/m128

values in xmm2/mem to two signed doubleword integers

in xmm1 using truncation.

VEX.256.66.0F.WIG E6 /r

V/V

AVX

Convert four packed double precision floating-point

VCVTTPD2DQ xmm1, ymm2/m256

values in ymm2/mem to four signed doubleword integers

in xmm1 using truncation.

EVEX.128.66.0F.W1 E6 /r

V/V

AVX512VL

Convert two packed double precision floating-point

VCVTTPD2DQ xmm1 {k1}{z},

AVX512F

values in xmm2/m128/m64bcst to two signed

xmm2/m128/m64bcst

doubleword integers in xmm1 using truncation subject to

writemask k1.

EVEX.256.66.0F.W1 E6 /r

V/V

AVX512VL

Convert four packed double precision floating-point

VCVTTPD2DQ xmm1 {k1}{z},

AVX512F

values in ymm2/m256/m64bcst to four signed

ymm2/m256/m64bcst

doubleword integers in xmm1 using truncation subject to

writemask k1.

EVEX.512.66.0F.W1 E6 /r

V/V

AVX512F

Convert eight packed double precision floating-point

VCVTTPD2DQ ymm1 {k1}{z},

values in zmm2/m512/m64bcst to eight signed

zmm2/m512/m64bcst{sae}

doubleword integers in ymm1 using truncation subject to

writemask k1.

Instruction Operand Encoding

Op/En

Tuple Type

Operand 1

Operand 2

Operand 3

Operand 4

N/A

ModRM:reg (w)

ModRM:r/m (r)

N/A

Full

ModRM:reg (w)

ModRM:r/m (r)

N/A

Description

Converts two, four or eight packed double precision floating-point values in the source operand (second operand)

to two, four or eight packed signed doubleword integers in the destination operand (first operand).

When a conversion is inexact, a truncated (round toward zero) value is returned. If a converted result is larger than

the maximum signed doubleword integer, the floating-point invalid exception is raised, and if this exception is

masked, the indefinite integer value (80000000H) is returned.

EVEX encoded versions: The source operand is a ZMM/YMM/XMM register, a 512/256/128-bit memory location, or

a 512/256/128-bit vector broadcasted from a 64-bit memory location. The destination operand is a

YMM/XMM/XMM (low 64 bits) register conditionally updated with writemask k1. The upper bits (MAXVL-1:256) of

the corresponding destination are zeroed.

VEX.256 encoded version: The source operand is a YMM register or 256- bit memory location. The destination

operand is an XMM register. The upper bits (MAXVL-1:128) of the corresponding ZMM register destination are

zeroed.

VEX.128 encoded version: The source operand is an XMM register or 128- bit memory location. The destination

operand is a XMM register. The upper bits (MAXVL-1:64) of the corresponding ZMM register destination are zeroed.

128-bit Legacy SSE version: The source operand is an XMM register or 128- bit memory location. The destination

operand is an XMM register. The upper bits (MAXVL-1:128) of the corresponding ZMM register destination are

unmodified.

Note: VEX.vvvv and EVEX.vvvv are reserved and must be 1111b, otherwise instructions will #UD.

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INSTRUCTION SET REFERENCE, A-L

VCVTTPD2DQ (EVEX Encoded Versions) When SRC Operand is a Memory Source

(KL, VL) = (2, 128), (4, 256), (8, 512)

FOR j := 0 TO KL-1

i := j * 32

k := j * 64

IF k1[j] OR *no writemask*

THEN

IF (EVEX.b = 1)

THEN

DEST[i+31:i] :=

Convert_Double_Precision_Floating_Point_To_Integer_Truncate(SRC[63:0])

ELSE

DEST[i+31:i] :=

Convert_Double_Precision_Floating_Point_To_Integer_Truncate(SRC[k+63:k])

FI;

ELSE

IF *merging-masking*

; merging-masking

THEN *DEST[i+31:i] remains unchanged*

ELSE

; zeroing-masking

DEST[i+31:i] := 0

FI;

ENDFOR

DEST[MAXVL-1:VL/2] := 0

VCVTTPD2DQ (VEX.256 Encoded Version)

DEST[31:0] := Convert_Double_Precision_Floating_Point_To_Integer_Truncate(SRC[63:0])

DEST[63:32] := Convert_Double_Precision_Floating_Point_To_Integer_Truncate(SRC[127:64])

DEST[95:64] := Convert_Double_Precision_Floating_Point_To_Integer_Truncate(SRC[191:128])

DEST[127:96] := Convert_Double_Precision_Floating_Point_To_Integer_Truncate(SRC[255:192)

DEST[MAXVL-1:128] := 0

VCVTTPD2DQ (VEX.128 Encoded Version)

DEST[31:0] := Convert_Double_Precision_Floating_Point_To_Integer_Truncate(SRC[63:0])

DEST[63:32] := Convert_Double_Precision_Floating_Point_To_Integer_Truncate(SRC[127:64])

DEST[MAXVL-1:64] := 0

CVTTPD2DQ (128-bit Legacy SSE Version)

DEST[31:0] := Convert_Double_Precision_Floating_Point_To_Integer_Truncate(SRC[63:0])

DEST[63:32] := Convert_Double_Precision_Floating_Point_To_Integer_Truncate(SRC[127:64])

DEST[127:64] := 0

DEST[MAXVL-1:128] (unmodified)

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INSTRUCTION SET REFERENCE, A-L

Intel C/C++ Compiler Intrinsic Equivalent

VCVTTPD2DQ __m256i _mm512_cvttpd_epi32( __m512d a);

VCVTTPD2DQ __m256i _mm512_mask_cvttpd_epi32( __m256i s, __mmask8 k, __m512d a);

VCVTTPD2DQ __m256i _mm512_maskz_cvttpd_epi32( __mmask8 k, __m512d a);

VCVTTPD2DQ __m256i _mm512_cvtt_roundpd_epi32( __m512d a, int sae);

VCVTTPD2DQ __m256i _mm512_mask_cvtt_roundpd_epi32( __m256i s, __mmask8 k, __m512d a, int sae);

VCVTTPD2DQ __m256i _mm512_maskz_cvtt_roundpd_epi32( __mmask8 k, __m512d a, int sae);

VCVTTPD2DQ __m128i _mm256_mask_cvttpd_epi32( __m128i s, __mmask8 k, __m256d a);

VCVTTPD2DQ __m128i _mm256_maskz_cvttpd_epi32( __mmask8 k, __m256d a);

VCVTTPD2DQ __m128i _mm_mask_cvttpd_epi32( __m128i s, __mmask8 k, __m128d a);

VCVTTPD2DQ __m128i _mm_maskz_cvttpd_epi32( __mmask8 k, __m128d a);

VCVTTPD2DQ __m128i _mm256_cvttpd_epi32 (__m256d src);

CVTTPD2DQ __m128i _mm_cvttpd_epi32 (__m128d src);

SIMD Floating-Point Exceptions

Invalid, Precision.

Other Exceptions

VEX-encoded instructions, see Table 2-19, “Type 2 Class Exception Conditions.”

EVEX-encoded instructions, see Table 2-46, “Type E2 Class Exception Conditions.”

Additionally:

#UD

If VEX.vvvv != 1111B or EVEX.vvvv != 1111B.

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INSTRUCTION SET REFERENCE, A-L

CVTTPD2PI-Convert With Truncation Packed Double Precision Floating-Point Values to Packed

Dword Integers

Opcode/

Op/

64-Bit

Compat/

Description

Instruction

Mode

Leg Mode

66 0F 2C /r

Valid

Convert two packer double precision floating-

point values from xmm/m128 to two packed

CVTTPD2PI mm, xmm/m128

signed doubleword integers in mm using

truncation.

Instruction Operand Encoding

Op/En

Operand 1

Operand 2

Operand 3

Operand 4

ModRM:reg (w)

ModRM:r/m (r)

N/A

Description

Converts two packed double precision floating-point values in the source operand (second operand) to two packed

signed doubleword integers in the destination operand (first operand). The source operand can be an XMM register

or a 128-bit memory location. The destination operand is an MMX technology register.

When a conversion is inexact, a truncated (round toward zero) result is returned. If a converted result is larger than

the maximum signed doubleword integer, the floating-point invalid exception is raised, and if this exception is

masked, the indefinite integer value (80000000H) is returned.

This instruction causes a transition from x87 FPU to MMX technology operation (that is, the x87 FPU top-of-stack

pointer is set to 0 and the x87 FPU tag word is set to all 0s [valid]). If this instruction is executed while an x87 FPU

floating-point exception is pending, the exception is handled before the CVTTPD2PI instruction is executed.

In 64-bit mode, use of the REX.R prefix permits this instruction to access additional registers (XMM8-XMM15).

Operation

DEST[31:0] := Convert_Double_Precision_Floating_Point_To_Integer32_Truncate(SRC[63:0]);

DEST[63:32] := Convert_Double_Precision_Floating_Point_To_Integer32_Truncate(SRC[127:64]);

Intel C/C++ Compiler Intrinsic Equivalent

CVTTPD1PI __m64 _mm_cvttpd_pi32(__m128d a)

SIMD Floating-Point Exceptions

Invalid, Precision.

Other Mode Exceptions

See Table 23-4, “Exception Conditions for Legacy SIMD/MMX Instructions with FP Exception and 16-Byte Align-

ment,” in the Intel^® 64 and IA-32 Architectures Software Developer’s Manual, Volume 3B.

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INSTRUCTION SET REFERENCE, A-L

CVTTPS2DQ-Convert With Truncation Packed Single Precision Floating-Point Values to Packed

Signed Doubleword Integer Values

Opcode/

Op /

64/32 bit

CPUID

Description

Instruction

Mode

Feature Flag

Support

F3 0F 5B /r

V/V

SSE2

Convert four packed single precision floating-point

CVTTPS2DQ xmm1, xmm2/m128

values from xmm2/mem to four packed signed

doubleword values in xmm1 using truncation.

VEX.128.F3.0F.WIG 5B /r

V/V

AVX

Convert four packed single precision floating-point

VCVTTPS2DQ xmm1, xmm2/m128

values from xmm2/mem to four packed signed

doubleword values in xmm1 using truncation.

VEX.256.F3.0F.WIG 5B /r

V/V

AVX

Convert eight packed single precision floating-point

VCVTTPS2DQ ymm1, ymm2/m256

values from ymm2/mem to eight packed signed

doubleword values in ymm1 using truncation.

EVEX.128.F3.0F.W0 5B /r

V/V

AVX512VL

Convert four packed single precision floating-point

VCVTTPS2DQ xmm1 {k1}{z},

AVX512F

values from xmm2/m128/m32bcst to four packed

xmm2/m128/m32bcst

signed doubleword values in xmm1 using truncation

subject to writemask k1.

EVEX.256.F3.0F.W0 5B /r

V/V

AVX512VL

Convert eight packed single precision floating-point

VCVTTPS2DQ ymm1 {k1}{z},

AVX512F

values from ymm2/m256/m32bcst to eight packed

ymm2/m256/m32bcst

signed doubleword values in ymm1 using truncation

subject to writemask k1.

EVEX.512.F3.0F.W0 5B /r

V/V

AVX512F

Convert sixteen packed single precision floating-point

VCVTTPS2DQ zmm1 {k1}{z},

values from zmm2/m512/m32bcst to sixteen packed

zmm2/m512/m32bcst {sae}

signed doubleword values in zmm1 using truncation

subject to writemask k1.

Instruction Operand Encoding

Op/En

Tuple Type

Operand 1

Operand 2

Operand 3

Operand 4

N/A

ModRM:reg (w)

ModRM:r/m (r)

N/A

Full

ModRM:reg (w)

ModRM:r/m (r)

N/A

Description

Converts four, eight or sixteen packed single precision floating-point values in the source operand to four, eight or

sixteen signed doubleword integers in the destination operand.

When a conversion is inexact, a truncated (round toward zero) value is returned. If a converted result is larger than

the maximum signed doubleword integer, the floating-point invalid exception is raised, and if this exception is

masked, the indefinite integer value (80000000H) is returned.

EVEX encoded versions: The source operand is a ZMM/YMM/XMM register, a 512/256/128-bit memory location or

a 512/256/128-bit vector broadcasted from a 32-bit memory location. The destination operand is a

ZMM/YMM/XMM register conditionally updated with writemask k1.

VEX.256 encoded version: The source operand is a YMM register or 256- bit memory location. The destination

operand is a YMM register. The upper bits (MAXVL-1:256) of the corresponding ZMM register destination are

zeroed.

VEX.128 encoded version: The source operand is an XMM register or 128- bit memory location. The destination

operand is a XMM register. The upper bits (MAXVL-1:128) of the corresponding ZMM register destination are

zeroed.

128-bit Legacy SSE version: The source operand is an XMM register or 128- bit memory location. The destination

operand is an XMM register. The upper bits (MAXVL-1:128) of the corresponding ZMM register destination are

unmodified.

Note: VEX.vvvv and EVEX.vvvv are reserved and must be 1111b otherwise instructions will #UD.

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INSTRUCTION SET REFERENCE, A-L

Operation

VCVTTPS2DQ (EVEX Encoded Versions) When SRC Operand is a Register

(KL, VL) = (4, 128), (8, 256), (16, 512)

FOR j := 0 TO KL-1

i := j * 32

IF k1[j] OR *no writemask*

THEN DEST[i+31:i] :=

Convert_Single_Precision_Floating_Point_To_Integer_Truncate(SRC[i+31:i])

ELSE

IF *merging-masking*

; merging-masking

THEN *DEST[i+31:i] remains unchanged*

ELSE

; zeroing-masking

DEST[i+31:i] := 0

FI;

ENDFOR

DEST[MAXVL-1:VL] := 0

VCVTTPS2DQ (EVEX Encoded Versions) When SRC Operand is a Memory Source

(KL, VL) = (4, 128), (8, 256), (16, 512)

FOR j := 0 TO 15

i := j * 32

IF k1[j] OR *no writemask*

THEN

IF (EVEX.b = 1)

THEN

DEST[i+31:i] :=

Convert_Single_Precision_Floating_Point_To_Integer_Truncate(SRC[31:0])

ELSE

DEST[i+31:i] :=

Convert_Single_Precision_Floating_Point_To_Integer_Truncate(SRC[i+31:i])

FI;

ELSE

IF *merging-masking*

; merging-masking

THEN *DEST[i+31:i] remains unchanged*

ELSE

; zeroing-masking

DEST[i+31:i] := 0

FI;

ENDFOR

DEST[MAXVL-1:VL] := 0

VCVTTPS2DQ (VEX.256 Encoded Version)

DEST[31:0] := Convert_Single_Precision_Floating_Point_To_Integer_Truncate(SRC[31:0])

DEST[63:32] := Convert_Single_Precision_Floating_Point_To_Integer_Truncate(SRC[63:32])

DEST[95:64] := Convert_Single_Precision_Floating_Point_To_Integer_Truncate(SRC[95:64])

DEST[127:96] := Convert_Single_Precision_Floating_Point_To_Integer_Truncate(SRC[127:96)

DEST[159:128] := Convert_Single_Precision_Floating_Point_To_Integer_Truncate(SRC[159:128])

DEST[191:160] := Convert_Single_Precision_Floating_Point_To_Integer_Truncate(SRC[191:160])

DEST[223:192] := Convert_Single_Precision_Floating_Point_To_Integer_Truncate(SRC[223:192])

DEST[255:224] := Convert_Single_Precision_Floating_Point_To_Integer_Truncate(SRC[255:224])

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INSTRUCTION SET REFERENCE, A-L

VCVTTPS2DQ (VEX.128 Encoded Version)

DEST[31:0] := Convert_Single_Precision_Floating_Point_To_Integer_Truncate(SRC[31:0])

DEST[63:32] := Convert_Single_Precision_Floating_Point_To_Integer_Truncate(SRC[63:32])

DEST[95:64] := Convert_Single_Precision_Floating_Point_To_Integer_Truncate(SRC[95:64])

DEST[127:96] := Convert_Single_Precision_Floating_Point_To_Integer_Truncate(SRC[127:96])

DEST[MAXVL-1:128] := 0

CVTTPS2DQ (128-bit Legacy SSE Version)

DEST[31:0] := Convert_Single_Precision_Floating_Point_To_Integer_Truncate(SRC[31:0])

DEST[63:32] := Convert_Single_Precision_Floating_Point_To_Integer_Truncate(SRC[63:32])

DEST[95:64] := Convert_Single_Precision_Floating_Point_To_Integer_Truncate(SRC[95:64])

DEST[127:96] := Convert_Single_Precision_Floating_Point_To_Integer_Truncate(SRC[127:96])

DEST[MAXVL-1:128] (unmodified)

Intel C/C++ Compiler Intrinsic Equivalent

VCVTTPS2DQ __m512i _mm512_cvttps_epi32( __m512 a);

VCVTTPS2DQ __m512i _mm512_mask_cvttps_epi32( __m512i s, __mmask16 k, __m512 a);

VCVTTPS2DQ __m512i _mm512_maskz_cvttps_epi32( __mmask16 k, __m512 a);

VCVTTPS2DQ __m512i _mm512_cvtt_roundps_epi32( __m512 a, int sae);

VCVTTPS2DQ __m512i _mm512_mask_cvtt_roundps_epi32( __m512i s, __mmask16 k, __m512 a, int sae);

VCVTTPS2DQ __m512i _mm512_maskz_cvtt_roundps_epi32( __mmask16 k, __m512 a, int sae);

VCVTTPS2DQ __m256i _mm256_mask_cvttps_epi32( __m256i s, __mmask8 k, __m256 a);

VCVTTPS2DQ __m256i _mm256_maskz_cvttps_epi32( __mmask8 k, __m256 a);

VCVTTPS2DQ __m128i _mm_mask_cvttps_epi32( __m128i s, __mmask8 k, __m128 a);

VCVTTPS2DQ __m128i _mm_maskz_cvttps_epi32( __mmask8 k, __m128 a);

VCVTTPS2DQ __m256i _mm256_cvttps_epi32 (__m256 a)

CVTTPS2DQ __m128i _mm_cvttps_epi32 (__m128 a)

SIMD Floating-Point Exceptions

Invalid, Precision.

Other Exceptions

VEX-encoded instructions, see Table 2-19, “Type 2 Class Exception Conditions.”

EVEX-encoded instructions, see Table 2-46, “Type E2 Class Exception Conditions.”

Additionally:

#UD

If VEX.vvvv != 1111B or EVEX.vvvv != 1111B.

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INSTRUCTION SET REFERENCE, A-L

CVTTPS2PI-Convert With Truncation Packed Single Precision Floating-Point Values to Packed

Dword Integers

Opcode/

Op/

64-Bit

Compat/

Description

Instruction

Mode

Leg Mode

NP 0F 2C /r

Valid

Convert two single precision floating-point

values from xmm/m64 to two signed

CVTTPS2PI mm, xmm/m64

doubleword signed integers in mm using

truncation.

Instruction Operand Encoding

Op/En

Operand 1

Operand 2

Operand 3

Operand 4

ModRM:reg (w)

ModRM:r/m (r)

N/A

Description

Converts two packed single precision floating-point values in the source operand (second operand) to two packed

signed doubleword integers in the destination operand (first operand). The source operand can be an XMM register

or a 64-bit memory location. The destination operand is an MMX technology register. When the source operand is

an XMM register, the two single precision floating-point values are contained in the low quadword of the register.

When a conversion is inexact, a truncated (round toward zero) result is returned. If a converted result is larger than

the maximum signed doubleword integer, the floating-point invalid exception is raised, and if this exception is

masked, the indefinite integer value (80000000H) is returned.

This instruction causes a transition from x87 FPU to MMX technology operation (that is, the x87 FPU top-of-stack

pointer is set to 0 and the x87 FPU tag word is set to all 0s [valid]). If this instruction is executed while an x87 FPU

floating-point exception is pending, the exception is handled before the CVTTPS2PI instruction is executed.

In 64-bit mode, use of the REX.R prefix permits this instruction to access additional registers (XMM8-XMM15).

Operation

DEST[31:0] := Convert_Single_Precision_Floating_Point_To_Integer_Truncate(SRC[31:0]);

DEST[63:32] := Convert_Single_Precision_Floating_Point_To_Integer_Truncate(SRC[63:32]);

Intel C/C++ Compiler Intrinsic Equivalent

CVTTPS2PI __m64 _mm_cvttps_pi32(__m128 a)

SIMD Floating-Point Exceptions

Invalid, Precision.

Other Exceptions

See Table 23-5, “Exception Conditions for Legacy SIMD/MMX Instructions with XMM and FP Exception,” in the

Intel^® 64 and IA-32 Architectures Software Developer’s Manual, Volume 3B.

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Intel 64 and IA-32 Architectures. Software Developer’s Manual (Collection, 2023) - page 21