Intel 64 and IA-32 Architectures. Software Developer’s Manual (2026) - page 46
INSTRUCTION FORMATS AND ENCODINGS
Instruction and Format
Encoding
xmmreglo2 with mem to xmmreg1
C5: r_xmmreglo2 001:E4:mod xmmreg1 r/m
VPMULHW - Multiply Packed Signed Integers and Store High Result
xmmreg2 with xmmreg3 to xmmreg1
C4: rxb0_1: w xmmreg2 001:E5:11 xmmreg1 xmmreg3
xmmreg2 with mem to xmmreg1
C4: rxb0_1: w xmmreg2 001:E5:mod xmmreg1 r/m
xmmreglo2 with xmmreglo3 to xmmreg1
C5: r_xmmreglo2 001:E5:11 xmmreg1 xmmreglo3
xmmreglo2 with mem to xmmreg1
C5: r_xmmreglo2 001:E5:mod xmmreg1 r/m
VPMULLW - Multiply Packed Signed Integers and Store Low Result
xmmreg2 with xmmreg3 to xmmreg1
C4: rxb0_1: w xmmreg2 001:D5:11 xmmreg1 xmmreg3
xmmreg2 with mem to xmmreg1
C4: rxb0_1: w xmmreg2 001:D5:mod xmmreg1 r/m
xmmreglo2 with xmmreglo3 to xmmreg1
C5: r_xmmreglo2 001:D5:11 xmmreg1 xmmreglo3
xmmreglo2 with mem to xmmreg1
C5: r_xmmreglo2 001:D5:mod xmmreg1 r/m
VPMULUDQ - Multiply Packed Unsigned Doubleword Integers
xmmreg2 with xmmreg3 to xmmreg1
C4: rxb0_1: w xmmreg2 001:F4:11 xmmreg1 xmmreg3
xmmreg2 with mem to xmmreg1
C4: rxb0_1: w xmmreg2 001:F4:mod xmmreg1 r/m
xmmreglo2 with xmmreglo3 to xmmreg1
C5: r_xmmreglo2 001:F4:11 xmmreg1 xmmreglo3
xmmreglo2 with mem to xmmreg1
C5: r_xmmreglo2 001:F4:mod xmmreg1 r/m
VPOR - Bitwise Logical OR
xmmreg2 with xmmreg3 to xmmreg1
C4: rxb0_1: w xmmreg2 001:EB:11 xmmreg1 xmmreg3
xmmreg2 with mem to xmmreg1
C4: rxb0_1: w xmmreg2 001:EB:mod xmmreg1 r/m
xmmreglo2 with xmmreglo3 to xmmreg1
C5: r_xmmreglo2 001:EB:11 xmmreg1 xmmreglo3
xmmreglo2 with mem to xmmreg1
C5: r_xmmreglo2 001:EB:mod xmmreg1 r/m
VPSADBW - Compute Sum of Absolute Differences
xmmreg2 with xmmreg3 to xmmreg1
C4: rxb0_1: w xmmreg2 001:F6:11 xmmreg1 xmmreg3
xmmreg2 with mem to xmmreg1
C4: rxb0_1: w xmmreg2 001:F6:mod xmmreg1 r/m
xmmreglo2 with xmmreglo3 to xmmreg1
C5: r_xmmreglo2 001:F6:11 xmmreg1 xmmreglo3
xmmreglo2 with mem to xmmreg1
C5: r_xmmreglo2 001:F6:mod xmmreg1 r/m
VPSHUFD - Shuffle Packed Doublewords
xmmreg2 to xmmreg1 using imm
C4: rxb0_1: w_F 001:70:11 xmmreg1 xmmreg2: imm
mem to xmmreg1 using imm
C4: rxb0_1: w_F 001:70:mod xmmreg1 r/m: imm
xmmreglo to xmmreg1 using imm
C5: r_F 001:70:11 xmmreg1 xmmreglo: imm
mem to xmmreg1 using imm
C5: r_F 001:70:mod xmmreg1 r/m: imm
VPSHUFHW - Shuffle Packed High Words
xmmreg2 to xmmreg1 using imm
C4: rxb0_1: w_F 010:70:11 xmmreg1 xmmreg2: imm
mem to xmmreg1 using imm
C4: rxb0_1: w_F 010:70:mod xmmreg1 r/m: imm
xmmreglo to xmmreg1 using imm
C5: r_F 010:70:11 xmmreg1 xmmreglo: imm
mem to xmmreg1 using imm
C5: r_F 010:70:mod xmmreg1 r/m: imm
VPSHUFLW - Shuffle Packed Low Words
xmmreg2 to xmmreg1 using imm
C4: rxb0_1: w_F 011:70:11 xmmreg1 xmmreg2: imm
mem to xmmreg1 using imm
C4: rxb0_1: w_F 011:70:mod xmmreg1 r/m: imm
B-92
Vol. 2D
INSTRUCTION FORMATS AND ENCODINGS
Instruction and Format
Encoding
xmmreglo to xmmreg1 using imm
C5: r_F 011:70:11 xmmreg1 xmmreglo: imm
mem to xmmreg1 using imm
C5: r_F 011:70:mod xmmreg1 r/m: imm
VPSLLDQ - Shift Double Quadword Left Logical
xmmreg2 to xmmreg1 using imm
C4: rxb0_1: w_F 001:73:11 xmmreg1 xmmreg2: imm
xmmreglo to xmmreg1 using imm
C5: r_F 001:73:11 xmmreg1 xmmreglo: imm
VPSLLW - Shift Packed Data Left Logical
xmmreg2 with xmmreg3 to xmmreg1
C4: rxb0_1: w xmmreg2 001:F1:11 xmmreg1 xmmreg3
xmmreg2 with mem to xmmreg1
C4: rxb0_1: w xmmreg2 001:F1:mod xmmreg1 r/m
xmmreglo2 with xmmreglo3 to xmmreg1
C5: r_xmmreglo2 001:F1:11 xmmreg1 xmmreglo3
xmmreglo2 with mem to xmmreg1
C5: r_xmmreglo2 001:F1:mod xmmreg1 r/m
xmmreg2 to xmmreg1 using imm8
C4: rxb0_1: w_F 001:71:11 xmmreg1 xmmreg2: imm
xmmreglo to xmmreg1 using imm8
C5: r_F 001:71:11 xmmreg1 xmmreglo: imm
VPSLLD - Shift Packed Data Left Logical
xmmreg2 with xmmreg3 to xmmreg1
C4: rxb0_1: w xmmreg2 001:F2:11 xmmreg1 xmmreg3
xmmreg2 with mem to xmmreg1
C4: rxb0_1: w xmmreg2 001:F2:mod xmmreg1 r/m
xmmreglo2 with xmmreglo3 to xmmreg1
C5: r_xmmreglo2 001:F2:11 xmmreg1 xmmreglo3
xmmreglo2 with mem to xmmreg1
C5: r_xmmreglo2 001:F2:mod xmmreg1 r/m
xmmreg2 to xmmreg1 using imm8
C4: rxb0_1: w_F 001:72:11 xmmreg1 xmmreg2: imm
xmmreglo to xmmreg1 using imm8
C5: r_F 001:72:11 xmmreg1 xmmreglo: imm
VPSLLQ - Shift Packed Data Left Logical
xmmreg2 with xmmreg3 to xmmreg1
C4: rxb0_1: w xmmreg2 001:F3:11 xmmreg1 xmmreg3
xmmreg2 with mem to xmmreg1
C4: rxb0_1: w xmmreg2 001:F3:mod xmmreg1 r/m
xmmreglo2 with xmmreglo3 to xmmreg1
C5: r_xmmreglo2 001:F3:11 xmmreg1 xmmreglo3
xmmreglo2 with mem to xmmreg1
C5: r_xmmreglo2 001:F3:mod xmmreg1 r/m
xmmreg2 to xmmreg1 using imm8
C4: rxb0_1: w_F 001:73:11 xmmreg1 xmmreg2: imm
xmmreglo to xmmreg1 using imm8
C5: r_F 001:73:11 xmmreg1 xmmreglo: imm
VPSRAW - Shift Packed Data Right Arithmetic
xmmreg2 with xmmreg3 to xmmreg1
C4: rxb0_1: w xmmreg2 001:E1:11 xmmreg1 xmmreg3
xmmreg2 with mem to xmmreg1
C4: rxb0_1: w xmmreg2 001:E1:mod xmmreg1 r/m
xmmreglo2 with xmmreglo3 to xmmreg1
C5: r_xmmreglo2 001:E1:11 xmmreg1 xmmreglo3
xmmreglo2 with mem to xmmreg1
C5: r_xmmreglo2 001:E1:mod xmmreg1 r/m
xmmreg2 to xmmreg1 using imm8
C4: rxb0_1: w_F 001:71:11 xmmreg1 xmmreg2: imm
xmmreglo to xmmreg1 using imm8
C5: r_F 001:71:11 xmmreg1 xmmreglo: imm
VPSRAD - Shift Packed Data Right Arithmetic
xmmreg2 with xmmreg3 to xmmreg1
C4: rxb0_1: w xmmreg2 001:E2:11 xmmreg1 xmmreg3
xmmreg2 with mem to xmmreg1
C4: rxb0_1: w xmmreg2 001:E2:mod xmmreg1 r/m
xmmreglo2 with xmmreglo3 to xmmreg1
C5: r_xmmreglo2 001:E2:11 xmmreg1 xmmreglo3
xmmreglo2 with mem to xmmreg1
C5: r_xmmreglo2 001:E2:mod xmmreg1 r/m
xmmreg2 to xmmreg1 using imm8
C4: rxb0_1: w_F 001:72:11 xmmreg1 xmmreg2: imm
Vol. 2D B-93
INSTRUCTION FORMATS AND ENCODINGS
Instruction and Format
Encoding
xmmreglo to xmmreg1 using imm8
C5: r_F 001:72:11 xmmreg1 xmmreglo: imm
VPSRLDQ - Shift Double Quadword Right Logical
xmmreg2 to xmmreg1 using imm8
C4: rxb0_1: w_F 001:73:11 xmmreg1 xmmreg2: imm
xmmreglo to xmmreg1 using imm8
C5: r_F 001:73:11 xmmreg1 xmmreglo: imm
VPSRLW - Shift Packed Data Right Logical
xmmreg2 with xmmreg3 to xmmreg1
C4: rxb0_1: w xmmreg2 001:D1:11 xmmreg1 xmmreg3
xmmreg2 with mem to xmmreg1
C4: rxb0_1: w xmmreg2 001:D1:mod xmmreg1 r/m
xmmreglo2 with xmmreglo3 to xmmreg1
C5: r_xmmreglo2 001:D1:11 xmmreg1 xmmreglo3
xmmreglo2 with mem to xmmreg1
C5: r_xmmreglo2 001:D1:mod xmmreg1 r/m
xmmreg2 to xmmreg1 using imm8
C4: rxb0_1: w_F 001:71:11 xmmreg1 xmmreg2: imm
xmmreglo to xmmreg1 using imm8
C5: r_F 001:71:11 xmmreg1 xmmreglo: imm
VPSRLD - Shift Packed Data Right Logical
xmmreg2 with xmmreg3 to xmmreg1
C4: rxb0_1: w xmmreg2 001:D2:11 xmmreg1 xmmreg3
xmmreg2 with mem to xmmreg1
C4: rxb0_1: w xmmreg2 001:D2:mod xmmreg1 r/m
xmmreglo2 with xmmreglo3 to xmmreg1
C5: r_xmmreglo2 001:D2:11 xmmreg1 xmmreglo3
xmmreglo2 with mem to xmmreg1
C5: r_xmmreglo2 001:D2:mod xmmreg1 r/m
xmmreg2 to xmmreg1 using imm8
C4: rxb0_1: w_F 001:72:11 xmmreg1 xmmreg2: imm
xmmreglo to xmmreg1 using imm8
C5: r_F 001:72:11 xmmreg1 xmmreglo: imm
VPSRLQ - Shift Packed Data Right Logical
xmmreg2 with xmmreg3 to xmmreg1
C4: rxb0_1: w xmmreg2 001:D3:11 xmmreg1 xmmreg3
xmmreg2 with mem to xmmreg1
C4: rxb0_1: w xmmreg2 001:D3:mod xmmreg1 r/m
xmmreglo2 with xmmreglo3 to xmmreg1
C5: r_xmmreglo2 001:D3:11 xmmreg1 xmmreglo3
xmmreglo2 with mem to xmmreg1
C5: r_xmmreglo2 001:D3:mod xmmreg1 r/m
xmmreg2 to xmmreg1 using imm8
C4: rxb0_1: w_F 001:73:11 xmmreg1 xmmreg2: imm
xmmreglo to xmmreg1 using imm8
C5: r_F 001:73:11 xmmreg1 xmmreglo: imm
VPSUBB - Subtract Packed Integers
xmmreg2 with xmmreg3 to xmmreg1
C4: rxb0_1: w xmmreg2 001:F8:11 xmmreg1 xmmreg3
xmmreg2 with mem to xmmreg1
C4: rxb0_1: w xmmreg2 001:F8:mod xmmreg1 r/m
xmmreglo2 with xmmreglo3 to xmmreg1
C5: r_xmmreglo2 001:F8:11 xmmreg1 xmmreglo3
xmmreglo2 with mem to xmmreg1
C5: r_xmmreglo2 001:F8:mod xmmreg1 r/m
VPSUBW - Subtract Packed Integers
xmmreg2 with xmmreg3 to xmmreg1
C4: rxb0_1: w xmmreg2 001:F9:11 xmmreg1 xmmreg3
xmmreg2 with mem to xmmreg1
C4: rxb0_1: w xmmreg2 001:F9:mod xmmreg1 r/m
xmmreglo2 with xmmreglo3 to xmmreg1
C5: r_xmmreglo2 001:F9:11 xmmreg1 xmmreglo3
xmmrelog2 with mem to xmmreg1
C5: r_xmmreglo2 001:F9:mod xmmreg1 r/m
VPSUBD - Subtract Packed Integers
xmmreg2 with xmmreg3 to xmmreg1
C4: rxb0_1: w xmmreg2 001:FA:11 xmmreg1 xmmreg3
xmmreg2 with mem to xmmreg1
C4: rxb0_1: w xmmreg2 001:FA:mod xmmreg1 r/m
xmmreglo2 with xmmreglo3 to xmmreg1
C5: r_xmmreglo2 001:FA:11 xmmreg1 xmmreglo3
B-94
Vol. 2D
INSTRUCTION FORMATS AND ENCODINGS
Instruction and Format
Encoding
xmmreglo2 with mem to xmmreg1
C5: r_xmmreglo2 001:FA:mod xmmreg1 r/m
VPSUBQ - Subtract Packed Quadword Integers
xmmreg2 with xmmreg3 to xmmreg1
C4: rxb0_1: w xmmreg2 001:FB:11 xmmreg1 xmmreg3
xmmreg2 with mem to xmmreg1
C4: rxb0_1: w xmmreg2 001:FB:mod xmmreg1 r/m
xmmreglo2 with xmmreglo3 to xmmreg1
C5: r_xmmreglo2 001:FB:11 xmmreg1 xmmreglo3
xmmreglo2 with mem to xmmreg1
C5: r_xmmreglo2 001:FB:mod xmmreg1 r/m
VPSUBSB - Subtract Packed Signed Integers with Signed Saturation
xmmreg2 with xmmreg3 to xmmreg1
C4: rxb0_1: w xmmreg2 001:E8:11 xmmreg1 xmmreg3
xmmreg2 with mem to xmmreg1
C4: rxb0_1: w xmmreg2 001:E8:mod xmmreg1 r/m
xmmreglo2 with xmmreglo3 to xmmreg1
C5: r_xmmreglo2 001:E8:11 xmmreg1 xmmreglo3
xmmreglo2 with mem to xmmreg1
C5: r_xmmreglo2 001:E8:mod xmmreg1 r/m
VPSUBSW - Subtract Packed Signed Integers with Signed Saturation
xmmreg2 with xmmreg3 to xmmreg1
C4: rxb0_1: w xmmreg2 001:E9:11 xmmreg1 xmmreg3
xmmreg2 with mem to xmmreg1
C4: rxb0_1: w xmmreg2 001:E9:mod xmmreg1 r/m
xmmreglo2 with xmmreglo3 to xmmreg1
C5: r_xmmreglo2 001:E9:11 xmmreg1 xmmreglo3
xmmreglo2 with mem to xmmreg1
C5: r_xmmreglo2 001:E9:mod xmmreg1 r/m
VPSUBUSB - Subtract Packed Unsigned Integers with Unsigned Saturation
xmmreg2 with xmmreg3 to xmmreg1
C4: rxb0_1: w xmmreg2 001:D8:11 xmmreg1 xmmreg3
xmmreg2 with mem to xmmreg1
C4: rxb0_1: w xmmreg2 001:D8:mod xmmreg1 r/m
xmmreglo2 with xmmreglo3 to xmmreg1
C5: r_xmmreglo2 001:D8:11 xmmreg1 xmmreglo3
xmmreglo2 with mem to xmmreg1
C5: r_xmmreglo2 001:D8:mod xmmreg1 r/m
VPSUBUSW - Subtract Packed Unsigned Integers with Unsigned Saturation
xmmreg2 with xmmreg3 to xmmreg1
C4: rxb0_1: w xmmreg2 001:D9:11 xmmreg1 xmmreg3
xmmreg2 with mem to xmmreg1
C4: rxb0_1: w xmmreg2 001:D9:mod xmmreg1 r/m
xmmreglo2 with xmmreglo3 to xmmreg1
C5: r_xmmreglo2 001:D9:11 xmmreg1 xmmreglo3
xmmreglo2 with mem to xmmreg1
C5: r_xmmreglo2 001:D9:mod xmmreg1 r/m
VPUNPCKHBW - Unpack High Data
xmmreg2 with xmmreg3 to xmmreg1
C4: rxb0_1: w xmmreg2 001:68:11 xmmreg1 xmmreg3
xmmreg2 with mem to xmmreg1
C4: rxb0_1: w xmmreg2 001:68:mod xmmreg1 r/m
xmmreglo2 with xmmreglo3 to xmmreg1
C5: r_xmmreglo2 001:68:11 xmmreg1 xmmreglo3
xmmreglo2 with mem to xmmreg1
C5: r_xmmreglo2 001:68:mod xmmreg1 r/m
VPUNPCKHWD - Unpack High Data
xmmreg2 with xmmreg3 to xmmreg1
C4: rxb0_1: w xmmreg2 001:69:11 xmmreg1 xmmreg3
xmmreg2 with mem to xmmreg1
C4: rxb0_1: w xmmreg2 001:69:mod xmmreg1 r/m
xmmreglo2 with xmmreglo3 to xmmreg1
C5: r_xmmreglo2 001:69:11 xmmreg1 xmmreglo3
xmmreglo2 with mem to xmmreg1
C5: r_xmmreglo2 001:69:mod xmmreg1 r/m
VPUNPCKHDQ - Unpack High Data
xmmreg2 with xmmreg3 to xmmreg1
C4: rxb0_1: w xmmreg2 001:6A:11 xmmreg1 xmmreg3
xmmreg2 with mem to xmmreg1
C4: rxb0_1: w xmmreg2 001:6A:mod xmmreg1 r/m
Vol. 2D B-95
INSTRUCTION FORMATS AND ENCODINGS
Instruction and Format
Encoding
xmmreglo2 with xmmreglo3 to xmmreg1
C5: r_xmmreglo2 001:6A:11 xmmreg1 xmmreglo3
xmmreglo2 with mem to xmmreg1
C5: r_xmmreglo2 001:6A:mod xmmreg1 r/m
VPUNPCKHQDQ - Unpack High Data
xmmreg2 with xmmreg3 to xmmreg1
C4: rxb0_1: w xmmreg2 001:6D:11 xmmreg1 xmmreg3
xmmreg2 with mem to xmmreg1
C4: rxb0_1: w xmmreg2 001:6D:mod xmmreg1 r/m
xmmreglo2 with xmmreglo3 to xmmreg1
C5: r_xmmreglo2 001:6D:11 xmmreg1 xmmreglo3
xmmreglo2 with mem to xmmreg1
C5: r_xmmreglo2 001:6D:mod xmmreg1 r/m
VPUNPCKLBW - Unpack Low Data
xmmreg2 with xmmreg3 to xmmreg1
C4: rxb0_1: w xmmreg2 001:60:11 xmmreg1 xmmreg3
xmmreg2 with mem to xmmreg1
C4: rxb0_1: w xmmreg2 001:60:mod xmmreg1 r/m
xmmreglo2 with xmmreglo3 to xmmreg1
C5: r_xmmreglo2 001:60:11 xmmreg1 xmmreglo3
xmmreglo2 with mem to xmmreg1
C5: r_xmmreglo2 001:60:mod xmmreg1 r/m
VPUNPCKLWD - Unpack Low Data
xmmreg2 with xmmreg3 to xmmreg1
C4: rxb0_1: w xmmreg2 001:61:11 xmmreg1 xmmreg3
xmmreg2 with mem to xmmreg1
C4: rxb0_1: w xmmreg2 001:61:mod xmmreg1 r/m
xmmreglo2 with xmmreglo3 to xmmreg1
C5: r_xmmreglo2 001:61:11 xmmreg1 xmmreglo3
xmmreglo2 with mem to xmmreg1
C5: r_xmmreglo2 001:61:mod xmmreg1 r/m
VPUNPCKLDQ - Unpack Low Data
xmmreg2 with xmmreg3 to xmmreg1
C4: rxb0_1: w xmmreg2 001:62:11 xmmreg1 xmmreg3
xmmreg2 with mem to xmmreg1
C4: rxb0_1: w xmmreg2 001:62:mod xmmreg1 r/m
xmmreglo2 with xmmreglo3 to xmmreg1
C5: r_xmmreglo2 001:62:11 xmmreg1 xmmreglo3
xmmreglo2 with mem to xmmreg1
C5: r_xmmreglo2 001:62:mod xmmreg1 r/m
VPUNPCKLQDQ - Unpack Low Data
xmmreg2 with xmmreg3 to xmmreg1
C4: rxb0_1: w xmmreg2 001:6C:11 xmmreg1 xmmreg3
xmmreg2 with mem to xmmreg1
C4: rxb0_1: w xmmreg2 001:6C:mod xmmreg1 r/m
xmmreglo2 with xmmreglo3 to xmmreg1
C5: r_xmmreglo2 001:6C:11 xmmreg1 xmmreglo3
xmmreglo2 with mem to xmmreg1
C5: r_xmmreglo2 001:6C:mod xmmreg1 r/m
VPXOR - Logical Exclusive OR
xmmreg2 with xmmreg3 to xmmreg1
C4: rxb0_1: w xmmreg2 001:EF:11 xmmreg1 xmmreg3
xmmreg2 with mem to xmmreg1
C4: rxb0_1: w xmmreg2 001:EF:mod xmmreg1 r/m
xmmreglo2 with xmmreglo3 to xmmreg1
C5: r_xmmreglo2 001:EF:11 xmmreg1 xmmreglo3
xmmreglo2 with mem to xmmreg1
C5: r_xmmreglo2 001:EF:mod xmmreg1 r/m
VSHUFPD - Shuffle Packed Double Precision Floating-Point Values
xmmreg2 with xmmreg3 to xmmreg1 using imm8
C4: rxb0_1: w xmmreg2 001:C6:11 xmmreg1 xmmreg3: imm
xmmreg2 with mem to xmmreg1 using imm8
C4: rxb0_1: w xmmreg2 001:C6:mod xmmreg1 r/m: imm
xmmreglo2 with xmmreglo3 to xmmreg1 using imm8
C5: r_xmmreglo2 001:C6:11 xmmreg1 xmmreglo3: imm
xmmreglo2 with mem to xmmreg1 using imm8
C5: r_xmmreglo2 001:C6:mod xmmreg1 r/m: imm
ymmreg2 with ymmreg3 to ymmreg1 using imm8
C4: rxb0_1: w ymmreg2 101:C6:11 ymmreg1 ymmreg3: imm
ymmreg2 with mem to ymmreg1 using imm8
C4: rxb0_1: w ymmreg2 101:C6:mod ymmreg1 r/m: imm
B-96
Vol. 2D
INSTRUCTION FORMATS AND ENCODINGS
Instruction and Format
Encoding
ymmreglo2 with ymmreglo3 to ymmreg1 using imm8
C5: r_ymmreglo2 101:C6:11 ymmreg1 ymmreglo3: imm
ymmreglo2 with mem to ymmreg1 using imm8
C5: r_ymmreglo2 101:C6:mod ymmreg1 r/m: imm
VSQRTPD - Compute Square Roots of Packed Double Precision Floating-Point Values
xmmreg2 to xmmreg1
C4: rxb0_1: w_F 001:51:11 xmmreg1 xmmreg2
mem to xmmreg1
C4: rxb0_1: w_F 001:51:mod xmmreg1 r/m
xmmreglo to xmmreg1
C5: r_F 001:51:11 xmmreg1 xmmreglo
mem to xmmreg1
C5: r_F 001:51:mod xmmreg1 r/m
ymmreg2 to ymmreg1
C4: rxb0_1: w_F 101:51:11 ymmreg1 ymmreg2
mem to ymmreg1
C4: rxb0_1: w_F 101:51:mod ymmreg1 r/m
ymmreglo to ymmreg1
C5: r_F 101:51:11 ymmreg1 ymmreglo
mem to ymmreg1
C5: r_F 101:51:mod ymmreg1 r/m
VSQRTSD - Compute Square Root of Scalar Double Precision Floating-Point Value
xmmreg2 with xmmreg3 to xmmreg1
C4: rxb0_1: w xmmreg2 011:51:11 xmmreg1 xmmreg3
xmmreg2 with mem to xmmreg1
C4: rxb0_1: w xmmreg2 011:51:mod xmmreg1 r/m
xmmreglo2 with xmmreglo3 to xmmreg1
C5: r_xmmreglo2 011:51:11 xmmreg1 xmmreglo3
xmmreglo2 with mem to xmmreg1
C5: r_xmmreglo2 011:51:mod xmmreg1 r/m
VSUBPD - Subtract Packed Double Precision Floating-Point Values
xmmreg2 with xmmreg3 to xmmreg1
C4: rxb0_1: w xmmreg2 001:5C:11 xmmreg1 xmmreg3
xmmreg2 with mem to xmmreg1
C4: rxb0_1: w xmmreg2 001:5C:mod xmmreg1 r/m
xmmreglo2 with xmmreglo3 to xmmreg1
C5: r_xmmreglo2 001:5C:11 xmmreg1 xmmreglo3
xmmreglo2 with mem to xmmreg1
C5: r_xmmreglo2 001:5C:mod xmmreg1 r/m
ymmreg2 with ymmreg3 to ymmreg1
C4: rxb0_1: w ymmreg2 101:5C:11 ymmreg1 ymmreg3
ymmreg2 with mem to ymmreg1
C4: rxb0_1: w ymmreg2 101:5C:mod ymmreg1 r/m
ymmreglo2 with ymmreglo3 to ymmreg1
C5: r_ymmreglo2 101:5C:11 ymmreg1 ymmreglo3
ymmreglo2 with mem to ymmreg1
C5: r_ymmreglo2 101:5C:mod ymmreg1 r/m
VSUBSD - Subtract Scalar Double Precision Floating-Point Values
xmmreg2 with xmmreg3 to xmmreg1
C4: rxb0_1: w xmmreg2 011:5C:11 xmmreg1 xmmreg3
xmmreg2 with mem to xmmreg1
C4: rxb0_1: w xmmreg2 011:5C:mod xmmreg1 r/m
xmmreglo2 with xmmreglo3 to xmmreg1
C5: r_xmmreglo2 011:5C:11 xmmreg1 xmmreglo3
xmmreglo2 with mem to xmmreg1
C5: r_xmmreglo2 011:5C:mod xmmreg1 r/m
VUCOMISD - Unordered Compare Scalar Double Precision Floating-Point Values and Set EFLAGS
xmmreg2 with xmmreg1, set EFLAGS
C4: rxb0_1: w_F xmmreg1 001:2E:11 xmmreg2
mem with xmmreg1, set EFLAGS
C4: rxb0_1: w_F xmmreg1 001:2E:mod r/m
xmmreglo with xmmreg1, set EFLAGS
C5: r_F xmmreg1 001:2E:11 xmmreglo
mem with xmmreg1, set EFLAGS
C5: r_F xmmreg1 001:2E:mod r/m
VUNPCKHPD - Unpack and Interleave High Packed Double Precision Floating-Point Values
xmmreg2 with xmmreg3 to xmmreg1
C4: rxb0_1: w xmmreg2 001:15:11 xmmreg1 xmmreg3
xmmreg2 with mem to xmmreg1
C4: rxb0_1: w xmmreg2 001:15:mod xmmreg1 r/m
xmmreglo2 with xmmreglo3 to xmmreg1
C5: r_xmmreglo2 001:15:11 xmmreg1 xmmreglo3
Vol. 2D B-97
INSTRUCTION FORMATS AND ENCODINGS
Instruction and Format
Encoding
xmmreglo2 with mem to xmmreg1
C5: r_xmmreglo2 001:15:mod xmmreg1 r/m
ymmreg2 with ymmreg3 to ymmreg1
C4: rxb0_1: w ymmreg2 101:15:11 ymmreg1 ymmreg3
ymmreg2 with mem to ymmreg1
C4: rxb0_1: w ymmreg2 101:15:mod ymmreg1 r/m
ymmreglo2 with ymmreglo3 to ymmreg1
C5: r_ymmreglo2 101:15:11 ymmreg1 ymmreglo3
ymmreglo2 with mem to ymmreg1
C5: r_ymmreglo2 101:15:mod ymmreg1 r/m
VUNPCKHPS - Unpack and Interleave High Packed Single Precision Floating-Point Values
xmmreg2 with xmmreg3 to xmmreg1
C4: rxb0_1: w xmmreg2 000:15:11 xmmreg1 xmmreg3
xmmreg2 with mem to xmmreg1
C4: rxb0_1: w xmmreg2 000:15:mod xmmreg1 r/m
xmmreglo2 with xmmreglo3 to xmmreg1
C5: r_xmmreglo2 000:15:11 xmmreg1 xmmreglo3
xmmreglo2 with mem to xmmreg1
C5: r_xmmreglo2 000:15:mod xmmreg1 r/m
ymmreg2 with ymmreg3 to ymmreg1
C4: rxb0_1: w ymmreg2 100:15:11 ymmreg1 ymmreg3
ymmreg2 with mem to ymmreg1
C4: rxb0_1: w ymmreg2 100:15:mod ymmreg1 r/m
ymmreglo2 with ymmreglo3 to ymmreg1
C5: r_ymmreglo2 100:15:11 ymmreg1 ymmreglo3
ymmreglo2 with mem to ymmreg1
C5: r_ymmreglo2 100:15:mod ymmreg1 r/m
VUNPCKLPD - Unpack and Interleave Low Packed Double Precision Floating-Point Values
xmmreg2 with xmmreg3 to xmmreg1
C4: rxb0_1: w xmmreg2 001:14:11 xmmreg1 xmmreg3
xmmreg2 with mem to xmmreg1
C4: rxb0_1: w xmmreg2 001:14:mod xmmreg1 r/m
xmmreglo2 with xmmreglo3 to xmmreg1
C5: r_xmmreglo2 001:14:11 xmmreg1 xmmreglo3
xmmreglo2 with mem to xmmreg1
C5: r_xmmreglo2 001:14:mod xmmreg1 r/m
ymmreg2 with ymmreg3 to ymmreg1
C4: rxb0_1: w ymmreg2 101:14:11 ymmreg1 ymmreg3
ymmreg2 with mem to ymmreg1
C4: rxb0_1: w ymmreg2 101:14:mod ymmreg1 r/m
ymmreglo2 with ymmreglo3 to ymmreg1
C5: r_ymmreglo2 101:14:11 ymmreg1 ymmreglo3
ymmreglo2 with mem to ymmreg1
C5: r_ymmreglo2 101:14:mod ymmreg1 r/m
VUNPCKLPS - Unpack and Interleave Low Packed Single Precision Floating-Point Values
xmmreg2 with xmmreg3 to xmmreg1
C4: rxb0_1: w xmmreg2 000:14:11 xmmreg1 xmmreg3
xmmreg2 with mem to xmmreg1
C4: rxb0_1: w xmmreg2 000:14:mod xmmreg1 r/m
xmmreglo2 with xmmreglo3 to xmmreg1
C5: r_xmmreglo2 000:14:11 xmmreg1 xmmreglo3
xmmreglo2 with mem to xmmreg1
C5: r_xmmreglo2 000:14:mod xmmreg1 r/m
ymmreg2 with ymmreg3 to ymmreg1
C4: rxb0_1: w ymmreg2 100:14:11 ymmreg1 ymmreg3
ymmreg2 with mem to ymmreg1
C4: rxb0_1: w ymmreg2 100:14:mod ymmreg1 r/m
ymmreglo2 with ymmreglo3 to ymmreg1
C5: r_ymmreglo2 100:14:11 ymmreg1 ymmreglo3
ymmreglo2 with mem to ymmreg1
C5: r_ymmreglo2 100:14:mod ymmreg1 r/m
VXORPD - Bitwise Logical XOR for Double Precision Floating-Point Values
xmmreg2 with xmmreg3 to xmmreg1
C4: rxb0_1: w xmmreg2 001:57:11 xmmreg1 xmmreg3
xmmreg2 with mem to xmmreg1
C4: rxb0_1: w xmmreg2 001:57:mod xmmreg1 r/m
xmmreglo2 with xmmreglo3 to xmmreg1
C5: r_xmmreglo2 001:57:11 xmmreg1 xmmreglo3
xmmreglo2 with mem to xmmreg1
C5: r_xmmreglo2 001:57:mod xmmreg1 r/m
ymmreg2 with ymmreg3 to ymmreg1
C4: rxb0_1: w ymmreg2 101:57:11 ymmreg1 ymmreg3
ymmreg2 with mem to ymmreg1
C4: rxb0_1: w ymmreg2 101:57:mod ymmreg1 r/m
B-98
Vol. 2D
INSTRUCTION FORMATS AND ENCODINGS
Instruction and Format
Encoding
ymmreglo2 with ymmreglo3 to ymmreg1
C5: r_ymmreglo2 101:57:11 ymmreg1 ymmreglo3
ymmreglo2 with mem to ymmreg1
C5: r_ymmreglo2 101:57:mod ymmreg1 r/m
VADDPS - Add Packed Single Precision Floating-Point Values
xmmreg2 with xmmreg3 to xmmreg1
C4: rxb0_1: w xmmreg2 000:58:11 xmmreg1 xmmreg3
xmmreg2 with mem to xmmreg1
C4: rxb0_1: w xmmreg2 000:58:mod xmmreg1 r/m
xmmreglo2 with xmmreglo3 to xmmreg1
C5: r_xmmreglo2 000:58:11 xmmreg1 xmmreglo3
xmmreglo2 with mem to xmmreg1
C5: r_xmmreglo2 000:58:mod xmmreg1 r/m
ymmreg2 with ymmreg3 to ymmreg1
C4: rxb0_1: w ymmreg2 100:58:11 ymmreg1 ymmreg3
ymmreg2 with mem to ymmreg1
C4: rxb0_1: w ymmreg2 100:58:mod ymmreg1 r/m
ymmreglo2 with ymmreglo3 to ymmreg1
C5: r_ymmreglo2 100:58:11 ymmreg1 ymmreglo3
ymmreglo2 with mem to ymmreg1
C5: r_ymmreglo2 100:58:mod ymmreg1 r/m
VADDSS - Add Scalar Single Precision Floating-Point Values
xmmreg2 with xmmreg3 to xmmreg1
C4: rxb0_1: w xmmreg2 010:58:11 xmmreg1 xmmreg3
xmmreg2 with mem to xmmreg1
C4: rxb0_1: w xmmreg2 010:58:mod xmmreg1 r/m
xmmreglo2 with xmmreglo3 to xmmreg1
C5: r_xmmreglo2 010:58:11 xmmreg1 xmmreglo3
xmmreglo2 with mem to xmmreg1
C5: r_xmmreglo2 010:58:mod xmmreg1 r/m
VANDPS - Bitwise Logical AND of Packed Single Precision Floating-Point Values
xmmreg2 with xmmreg3 to xmmreg1
C4: rxb0_1: w xmmreg2 000:54:11 xmmreg1 xmmreg3
xmmreg2 with mem to xmmreg1
C4: rxb0_1: w xmmreg2 000:54:mod xmmreg1 r/m
xmmreglo2 with xmmreglo3 to xmmreg1
C5: r_xmmreglo2 000:54:11 xmmreg1 xmmreglo3
xmmreglo2 with mem to xmmreg1
C5: r_xmmreglo2 000:54:mod xmmreg1 r/m
ymmreg2 with ymmreg3 to ymmreg1
C4: rxb0_1: w ymmreg2 100:54:11 ymmreg1 ymmreg3
ymmreg2 with mem to ymmreg1
C4: rxb0_1: w ymmreg2 100:54:mod ymmreg1 r/m
ymmreglo2 with ymmreglo3 to ymmreg1
C5: r_ymmreglo2 100:54:11 ymmreg1 ymmreglo3
ymmreglo2 with mem to ymmreg1
C5: r_ymmreglo2 100:54:mod ymmreg1 r/m
VANDNPS - Bitwise Logical AND NOT of Packed Single Precision Floating-Point Values
xmmreg2 with xmmreg3 to xmmreg1
C4: rxb0_1: w xmmreg2 000:55:11 xmmreg1 xmmreg3
xmmreg2 with mem to xmmreg1
C4: rxb0_1: w xmmreg2 000:55:mod xmmreg1 r/m
xmmreglo2 with xmmreglo3 to xmmreg1
C5: r_xmmreglo2 000:55:11 xmmreg1 xmmreglo3
xmmreglo2 with mem to xmmreg1
C5: r_xmmreglo2 000:55:mod xmmreg1 r/m
ymmreg2 with ymmreg3 to ymmreg1
C4: rxb0_1: w ymmreg2 100:55:11 ymmreg1 ymmreg3
ymmreg2 with mem to ymmreg1
C4: rxb0_1: w ymmreg2 100:55:mod ymmreg1 r/m
ymmreglo2 with ymmreglo3 to ymmreg1
C5: r_ymmreglo2 100:55:11 ymmreg1 ymmreglo3
ymmreglo2 with mem to ymmreg1
C5: r_ymmreglo2 100:55:mod ymmreg1 r/m
VCMPPS - Compare Packed Single Precision Floating-Point Values
xmmreg2 with xmmreg3 to xmmreg1
C4: rxb0_1: w xmmreg2 000:C2:11 xmmreg1 xmmreg3: imm
xmmreg2 with mem to xmmreg1
C4: rxb0_1: w xmmreg2 000:C2:mod xmmreg1 r/m: imm
xmmreglo2 with xmmreglo3 to xmmreg1
C5: r_xmmreglo2 000:C2:11 xmmreg1 xmmreglo3: imm
xmmreglo2 with mem to xmmreg1
C5: r_xmmreglo2 000:C2:mod xmmreg1 r/m: imm
Vol. 2D B-99
INSTRUCTION FORMATS AND ENCODINGS
Instruction and Format
Encoding
ymmreg2 with ymmreg3 to ymmreg1
C4: rxb0_1: w ymmreg2 100:C2:11 ymmreg1 ymmreg3: imm
ymmreg2 with mem to ymmreg1
C4: rxb0_1: w ymmreg2 100:C2:mod ymmreg1 r/m: imm
ymmreglo2 with ymmreglo3 to ymmreg1
C5: r_ymmreglo2 100:C2:11 ymmreg1 ymmreglo3: imm
ymmreglo2 with mem to ymmreg1
C5: r_ymmreglo2 100:C2:mod ymmreg1 r/m: imm
VCMPSS - Compare Scalar Single Precision Floating-Point Values
xmmreg2 with xmmreg3 to xmmreg1
C4: rxb0_1: w xmmreg2 010:C2:11 xmmreg1 xmmreg3: imm
xmmreg2 with mem to xmmreg1
C4: rxb0_1: w xmmreg2 010:C2:mod xmmreg1 r/m: imm
xmmreglo2 with xmmreglo3 to xmmreg1
C5: r_xmmreglo2 010:C2:11 xmmreg1 xmmreglo3: imm
xmmreglo2 with mem to xmmreg1
C5: r_xmmreglo2 010:C2:mod xmmreg1 r/m: imm
VCOMISS - Compare Scalar Ordered Single Precision Floating-Point Values and Set EFLAGS
xmmreg2 with xmmreg1
C4: rxb0_1: w_F 000:2F:11 xmmreg1 xmmreg2
mem with xmmreg1
C4: rxb0_1: w_F 000:2F:mod xmmreg1 r/m
xmmreglo with xmmreg1
C5: r_F 000:2F:11 xmmreg1 xmmreglo
mem with xmmreg1
C5: r_F 000:2F:mod xmmreg1 r/m
VCVTSI2SS - Convert Signed Integer to Scalar Single Precision FP Value
xmmreg2 with reg to xmmreg1
C4: rxb0_1: 0 xmmreg2 010:2A:11 xmmreg1 reg
xmmreg2 with mem to xmmreg1
C4: rxb0_1: 0 xmmreg2 010:2A:mod xmmreg1 r/m
xmmreglo2 with reglo to xmmreg1
C5: r_xmmreglo2 010:2A:11 xmmreg1 reglo
xmmreglo2 with mem to xmmreg1
C5: r_xmmreglo2 010:2A:mod xmmreg1 r/m
xmmreg2 with reg to xmmreg1
C4: rxb0_1: 1 xmmreg2 010:2A:11 xmmreg1 reg
xmmreg2 with mem to xmmreg1
C4: rxb0_1: 1 xmmreg2 010:2A:mod xmmreg1 r/m
VCVTSS2SI - Convert Scalar Single Precision FP Value to Signed Integer
xmmreg1 to reg
C4: rxb0_1: 0_F 010:2D:11 reg xmmreg1
mem to reg
C4: rxb0_1: 0_F 010:2D:mod reg r/m
xmmreglo to reg
C5: r_F 010:2D:11 reg xmmreglo
mem to reg
C5: r_F 010:2D:mod reg r/m
xmmreg1 to reg
C4: rxb0_1: 1_F 010:2D:11 reg xmmreg1
mem to reg
C4: rxb0_1: 1_F 010:2D:mod reg r/m
VCVTTSS2SI - Convert with Truncation Scalar Single Precision FP Value to Signed Integer
xmmreg1 to reg
C4: rxb0_1: 0_F 010:2C:11 reg xmmreg1
mem to reg
C4: rxb0_1: 0_F 010:2C:mod reg r/m
xmmreglo to reg
C5: r_F 010:2C:11 reg xmmreglo
mem to reg
C5: r_F 010:2C:mod reg r/m
xmmreg1 to reg
C4: rxb0_1: 1_F 010:2C:11 reg xmmreg1
mem to reg
C4: rxb0_1: 1_F 010:2C:mod reg r/m
VDIVPS - Divide Packed Single Precision Floating-Point Values
xmmreg2 with xmmreg3 to xmmreg1
C4: rxb0_1: w xmmreg2 000:5E:11 xmmreg1 xmmreg3
xmmreg2 with mem to xmmreg1
C4: rxb0_1: w xmmreg2 000:5E:mod xmmreg1 r/m
xmmreglo2 with xmmreglo3 to xmmreg1
C5: r_xmmreglo2 000:5E:11 xmmreg1 xmmreglo3
B-100
Vol. 2D
INSTRUCTION FORMATS AND ENCODINGS
Instruction and Format
Encoding
xmmreglo2 with mem to xmmreg1
C5: r_xmmreglo2 000:5E:mod xmmreg1 r/m
ymmreg2 with ymmreg3 to ymmreg1
C4: rxb0_1: w ymmreg2 100:5E:11 ymmreg1 ymmreg3
ymmreg2 with mem to ymmreg1
C4: rxb0_1: w ymmreg2 100:5E:mod ymmreg1 r/m
ymmreglo2 with ymmreglo3 to ymmreg1
C5: r_ymmreglo2 100:5E:11 ymmreg1 ymmreglo3
ymmreglo2 with mem to ymmreg1
C5: r_ymmreglo2 100:5E:mod ymmreg1 r/m
VDIVSS - Divide Scalar Single Precision Floating-Point Values
xmmreg2 with xmmreg3 to xmmreg1
C4: rxb0_1: w xmmreg2 010:5E:11 xmmreg1 xmmreg3
xmmreg2 with mem to xmmreg1
C4: rxb0_1: w xmmreg2 010:5E:mod xmmreg1 r/m
xmmreglo2 with xmmreglo3 to xmmreg1
C5: r_xmmreglo2 010:5E:11 xmmreg1 xmmreglo3
xmmreglo2 with mem to xmmreg1
C5: r_xmmreglo2 010:5E:mod xmmreg1 r/m
VLDMXCSR - Load MXCSR Register
mem to MXCSR reg
C4: rxb0_1: w_F 000:AEmod 011 r/m
mem to MXCSR reg
C5: r_F 000:AEmod 011 r/m
VMAXPS - Return Maximum Packed Single Precision Floating-Point Values
xmmreg2 with xmmreg3 to xmmreg1
C4: rxb0_1: w xmmreg2 000:5F:11 xmmreg1 xmmreg3
xmmreg2 with mem to xmmreg1
C4: rxb0_1: w xmmreg2 000:5F:mod xmmreg1 r/m
xmmreglo2 with xmmreglo3 to xmmreg1
C5: r_xmmreglo2 000:5F:11 xmmreg1 xmmreglo3
xmmreglo2 with mem to xmmreg1
C5: r_xmmreglo2 000:5F:mod xmmreg1 r/m
ymmreg2 with ymmreg3 to ymmreg1
C4: rxb0_1: w ymmreg2 100:5F:11 ymmreg1 ymmreg3
ymmreg2 with mem to ymmreg1
C4: rxb0_1: w ymmreg2 100:5F:mod ymmreg1 r/m
ymmreglo2 with ymmreglo3 to ymmreg1
C5: r_ymmreglo2 100:5F:11 ymmreg1 ymmreglo3
ymmreglo2 with mem to ymmreg1
C5: r_ymmreglo2 100:5F:mod ymmreg1 r/m
VMAXSS - Return Maximum Scalar Single Precision Floating-Point Value
xmmreg2 with xmmreg3 to xmmreg1
C4: rxb0_1: w xmmreg2 010:5F:11 xmmreg1 xmmreg3
xmmreg2 with mem to xmmreg1
C4: rxb0_1: w xmmreg2 010:5F:mod xmmreg1 r/m
xmmreglo2 with xmmreglo3 to xmmreg1
C5: r_xmmreglo2 010:5F:11 xmmreg1 xmmreglo3
xmmreglo2 with mem to xmmreg1
C5: r_xmmreglo2 010:5F:mod xmmreg1 r/m
VMINPS - Return Minimum Packed Single Precision Floating-Point Values
xmmreg2 with xmmreg3 to xmmreg1
C4: rxb0_1: w xmmreg2 000:5D:11 xmmreg1 xmmreg3
xmmreg2 with mem to xmmreg1
C4: rxb0_1: w xmmreg2 000:5D:mod xmmreg1 r/m
xmmreglo2 with xmmreglo3 to xmmreg1
C5: r_xmmreglo2 000:5D:11 xmmreg1 xmmreglo3
xmmreglo2 with mem to xmmreg1
C5: r_xmmreglo2 000:5D:mod xmmreg1 r/m
ymmreg2 with ymmreg3 to ymmreg1
C4: rxb0_1: w ymmreg2 100:5D:11 ymmreg1 ymmreg3
ymmreg2 with mem to ymmreg1
C4: rxb0_1: w ymmreg2 100:5D:mod ymmreg1 r/m
ymmreglo2 with ymmreglo3 to ymmreg1
C5: r_ymmreglo2 100:5D:11 ymmreg1 ymmreglo3
ymmreglo2 with mem to ymmreg1
C5: r_ymmreglo2 100:5D:mod ymmreg1 r/m
VMINSS - Return Minimum Scalar Single Precision Floating-Point Value
xmmreg2 with xmmreg3 to xmmreg1
C4: rxb0_1: w xmmreg2 010:5D:11 xmmreg1 xmmreg3
xmmreg2 with mem to xmmreg1
C4: rxb0_1: w xmmreg2 010:5D:mod xmmreg1 r/m
Vol. 2D B-101
INSTRUCTION FORMATS AND ENCODINGS
Instruction and Format
Encoding
xmmreglo2 with xmmreglo3 to xmmreg1
C5: r_xmmreglo2 010:5D:11 xmmreg1 xmmreglo3
xmmreglo2 with mem to xmmreg1
C5: r_xmmreglo2 010:5D:mod xmmreg1 r/m
VMOVAPS- Move Aligned Packed Single Precision Floating-Point Values
xmmreg2 to xmmreg1
C4: rxb0_1: w_F 000:28:11 xmmreg1 xmmreg2
mem to xmmreg1
C4: rxb0_1: w_F 000:28:mod xmmreg1 r/m
xmmreglo to xmmreg1
C5: r_F 000:28:11 xmmreg1 xmmreglo
mem to xmmreg1
C5: r_F 000:28:mod xmmreg1 r/m
xmmreg1 to xmmreg2
C4: rxb0_1: w_F 000:29:11 xmmreg2 xmmreg1
xmmreg1 to mem
C4: rxb0_1: w_F 000:29:mod r/m xmmreg1
xmmreg1 to xmmreglo
C5: r_F 000:29:11 xmmreglo xmmreg1
xmmreg1 to mem
C5: r_F 000:29:mod r/m xmmreg1
ymmreg2 to ymmreg1
C4: rxb0_1: w_F 100:28:11 ymmreg1 ymmreg2
mem to ymmreg1
C4: rxb0_1: w_F 100:28:mod ymmreg1 r/m
ymmreglo to ymmreg1
C5: r_F 100:28:11 ymmreg1 ymmreglo
mem to ymmreg1
C5: r_F 100:28:mod ymmreg1 r/m
ymmreg1 to ymmreg2
C4: rxb0_1: w_F 100:29:11 ymmreg2 ymmreg1
ymmreg1 to mem
C4: rxb0_1: w_F 100:29:mod r/m ymmreg1
ymmreg1 to ymmreglo
C5: r_F 100:29:11 ymmreglo ymmreg1
ymmreg1 to mem
C5: r_F 100:29:mod r/m ymmreg1
VMOVHPS - Move High Packed Single Precision Floating-Point Values
xmmreg1 with mem to xmmreg2
C4: rxb0_1: w xmmreg1 000:16:mod xmmreg2 r/m
xmmreg1 with mem to xmmreglo2
C5: r_xmmreg1 000:16:mod xmmreglo2 r/m
xmmreg1 to mem
C4: rxb0_1: w_F 000:17:mod r/m xmmreg1
xmmreglo to mem
C5: r_F 000:17:mod r/m xmmreglo
VMOVLHPS - Move Packed Single Precision Floating-Point Values Low to High
xmmreg2 with xmmreg3 to xmmreg1
C4: rxb0_1: w xmmreg2 000:16:11 xmmreg1 xmmreg3
xmmreglo2 with xmmreglo3 to xmmreg1
C5: r_xmmreglo2 000:16:11 xmmreg1 xmmreglo3
VMOVLPS - Move Low Packed Single Precision Floating-Point Values
xmmreg1 with mem to xmmreg2
C4: rxb0_1: w xmmreg1 000:12:mod xmmreg2 r/m
xmmreg1 with mem to xmmreglo2
C5: r_xmmreg1 000:12:mod xmmreglo2 r/m
xmmreg1 to mem
C4: rxb0_1: w_F 000:13:mod r/m xmmreg1
xmmreglo to mem
C5: r_F 000:13:mod r/m xmmreglo
VMOVMSKPS - Extract Packed Single Precision Floating-Point Sign Mask
xmmreg2 to reg
C4: rxb0_1: w_F 000:50:11 reg xmmreg2
xmmreglo to reg
C5: r_F 000:50:11 reg xmmreglo
ymmreg2 to reg
C4: rxb0_1: w_F 100:50:11 reg ymmreg2
ymmreglo to reg
C5: r_F 100:50:11 reg ymmreglo
VMOVNTPS - Store Packed Single Precision Floating-Point Values Using Non-Temporal Hint
xmmreg1 to mem
C4: rxb0_1: w_F 000:2B:mod r/m xmmreg1
B-102
Vol. 2D
INSTRUCTION FORMATS AND ENCODINGS
Instruction and Format
Encoding
xmmreglo to mem
C5: r_F 000:2B:mod r/m xmmreglo
ymmreg1 to mem
C4: rxb0_1: w_F 100:2B:mod r/m ymmreg1
ymmreglo to mem
C5: r_F 100:2B:mod r/m ymmreglo
VMOVSS - Move Scalar Single Precision Floating-Point Values
xmmreg2 with xmmreg3 to xmmreg1
C4: rxb0_1: w xmmreg2 010:10:11 xmmreg1 xmmreg3
mem to xmmreg1
C4: rxb0_1: w_F 010:10:mod xmmreg1 r/m
xmmreg2 with xmmreg3 to xmmreg1
C5: r_xmmreg2 010:10:11 xmmreg1 xmmreg3
mem to xmmreg1
C5: r_F 010:10:mod xmmreg1 r/m
xmmreg2 with xmmreg3 to xmmreg1
C4: rxb0_1: w xmmreg2 010:11:11 xmmreg1 xmmreg3
xmmreg1 to mem
C4: rxb0_1: w_F 010:11:mod r/m xmmreg1
xmmreglo2 with xmmreglo3 to xmmreg1
C5: r_xmmreglo2 010:11:11 xmmreg1 xmmreglo3
xmmreglo to mem
C5: r_F 010:11:mod r/m xmmreglo
VMOVUPS- Move Unaligned Packed Single Precision Floating-Point Values
xmmreg2 to xmmreg1
C4: rxb0_1: w_F 000:10:11 xmmreg1 xmmreg2
mem to xmmreg1
C4: rxb0_1: w_F 000:10:mod xmmreg1 r/m
xmmreglo to xmmreg1
C5: r_F 000:10:11 xmmreg1 xmmreglo
mem to xmmreg1
C5: r_F 000:10:mod xmmreg1 r/m
ymmreg2 to ymmreg1
C4: rxb0_1: w_F 100:10:11 ymmreg1 ymmreg2
mem to ymmreg1
C4: rxb0_1: w_F 100:10:mod ymmreg1 r/m
ymmreglo to ymmreg1
C5: r_F 100:10:11 ymmreg1 ymmreglo
mem to ymmreg1
C5: r_F 100:10:mod ymmreg1 r/m
xmmreg1 to xmmreg2
C4: rxb0_1: w_F 000:11:11 xmmreg2 xmmreg1
xmmreg1 to mem
C4: rxb0_1: w_F 000:11:mod r/m xmmreg1
xmmreg1 to xmmreglo
C5: r_F 000:11:11 xmmreglo xmmreg1
xmmreg1 to mem
C5: r_F 000:11:mod r/m xmmreg1
ymmreg1 to ymmreg2
C4: rxb0_1: w_F 100:11:11 ymmreg2 ymmreg1
ymmreg1 to mem
C4: rxb0_1: w_F 100:11:mod r/m ymmreg1
ymmreg1 to ymmreglo
C5: r_F 100:11:11 ymmreglo ymmreg1
ymmreg1 to mem
C5: r_F 100:11:mod r/m ymmreg1
VMULPS - Multiply Packed Single Precision Floating-Point Values
xmmreg2 with xmmreg3 to xmmreg1
C4: rxb0_1: w xmmreg2 000:59:11 xmmreg1 xmmreg3
xmmreg2 with mem to xmmreg1
C4: rxb0_1: w xmmreg2 000:59:mod xmmreg1 r/m
xmmreglo2 with xmmreglo3 to xmmreg1
C5: r_xmmreglo2 000:59:11 xmmreg1 xmmreglo3
xmmreglo2 with mem to xmmreg1
C5: r_xmmreglo2 000:59:mod xmmreg1 r/m
ymmreg2 with ymmreg3 to ymmreg1
C4: rxb0_1: w ymmreg2 100:59:11 ymmreg1 ymmreg3
ymmreg2 with mem to ymmreg1
C4: rxb0_1: w ymmreg2 100:59:mod ymmreg1 r/m
ymmreglo2 with ymmreglo3 to ymmreg1
C5: r_ymmreglo2 100:59:11 ymmreg1 ymmreglo3
ymmreglo2 with mem to ymmreg1
C5: r_ymmreglo2 100:59:mod ymmreg1 r/m
VMULSS - Multiply Scalar Single Precision Floating-Point Values
Vol. 2D B-103
INSTRUCTION FORMATS AND ENCODINGS
Instruction and Format
Encoding
xmmreg2 with xmmreg3 to xmmreg1
C4: rxb0_1: w xmmreg2 010:59:11 xmmreg1 xmmreg3
xmmreg2 with mem to xmmreg1
C4: rxb0_1: w xmmreg2 010:59:mod xmmreg1 r/m
xmmreglo2 with xmmreglo3 to xmmreg1
C5: r_xmmreglo2 010:59:11 xmmreg1 xmmreglo3
xmmreglo2 with mem to xmmreg1
C5: r_xmmreglo2 010:59:mod xmmreg1 r/m
VORPS - Bitwise Logical OR of Single Precision Floating-Point Values
xmmreg2 with xmmreg3 to xmmreg1
C4: rxb0_1: w xmmreg2 000:56:11 xmmreg1 xmmreg3
xmmreg2 with mem to xmmreg1
C4: rxb0_1: w xmmreg2 000:56:mod xmmreg1 r/m
xmmreglo2 with xmmreglo3 to xmmreg1
C5: r_xmmreglo2 000:56:11 xmmreg1 xmmreglo3
xmmreglo2 with mem to xmmreg1
C5: r_xmmreglo2 000:56:mod xmmreg1 r/m
ymmreg2 with ymmreg3 to ymmreg1
C4: rxb0_1: w ymmreg2 100:56:11 ymmreg1 ymmreg3
ymmreg2 with mem to ymmreg1
C4: rxb0_1: w ymmreg2 100:56:mod ymmreg1 r/m
ymmreglo2 with ymmreglo3 to ymmreg1
C5: r_ymmreglo2 100:56:11 ymmreg1 ymmreglo3
ymmreglo2 with mem to ymmreg1
C5: r_ymmreglo2 100:56:mod ymmreg1 r/m
VRCPPS - Compute Reciprocals of Packed Single Precision Floating-Point Values
xmmreg2 to xmmreg1
C4: rxb0_1: w_F 000:53:11 xmmreg1 xmmreg2
mem to xmmreg1
C4: rxb0_1: w_F 000:53:mod xmmreg1 r/m
xmmreglo to xmmreg1
C5: r_F 000:53:11 xmmreg1 xmmreglo
mem to xmmreg1
C5: r_F 000:53:mod xmmreg1 r/m
ymmreg2 to ymmreg1
C4: rxb0_1: w_F 100:53:11 ymmreg1 ymmreg2
mem to ymmreg1
C4: rxb0_1: w_F 100:53:mod ymmreg1 r/m
ymmreglo to ymmreg1
C5: r_F 100:53:11 ymmreg1 ymmreglo
mem to ymmreg1
C5: r_F 100:53:mod ymmreg1 r/m
VRCPSS - Compute Reciprocal of Scalar Single Precision Floating-Point Values
xmmreg2 with xmmreg3 to xmmreg1
C4: rxb0_1: w xmmreg2 010:53:11 xmmreg1 xmmreg3
xmmreg2 with mem to xmmreg1
C4: rxb0_1: w xmmreg2 010:53:mod xmmreg1 r/m
xmmreglo2 with xmmreglo3 to xmmreg1
C5: r_xmmreglo2 010:53:11 xmmreg1 xmmreglo3
xmmreglo2 with mem to xmmreg1
C5: r_xmmreglo2 010:53:mod xmmreg1 r/m
VRSQRTPS - Compute Reciprocals of Square Roots of Packed Single Precision Floating-Point Values
xmmreg2 to xmmreg1
C4: rxb0_1: w_F 000:52:11 xmmreg1 xmmreg2
mem to xmmreg1
C4: rxb0_1: w_F 000:52:mod xmmreg1 r/m
xmmreglo to xmmreg1
C5: r_F 000:52:11 xmmreg1 xmmreglo
mem to xmmreg1
C5: r_F 000:52:mod xmmreg1 r/m
ymmreg2 to ymmreg1
C4: rxb0_1: w_F 100:52:11 ymmreg1 ymmreg2
mem to ymmreg1
C4: rxb0_1: w_F 100:52:mod ymmreg1 r/m
ymmreglo to ymmreg1
C5: r_F 100:52:11 ymmreg1 ymmreglo
mem to ymmreg1
C5: r_F 100:52:mod ymmreg1 r/m
VRSQRTSS - Compute Reciprocal of Square Root of Scalar Single Precision Floating-Point Value
xmmreg2 with xmmreg3 to xmmreg1
C4: rxb0_1: w xmmreg2 010:52:11 xmmreg1 xmmreg3
xmmreg2 with mem to xmmreg1
C4: rxb0_1: w xmmreg2 010:52:mod xmmreg1 r/m
B-104
Vol. 2D
INSTRUCTION FORMATS AND ENCODINGS
Instruction and Format
Encoding
xmmreglo2 with xmmreglo3 to xmmreg1
C5: r_xmmreglo2 010:52:11 xmmreg1 xmmreglo3
xmmreglo2 with mem to xmmreg1
C5: r_xmmreglo2 010:52:mod xmmreg1 r/m
VSHUFPS - Shuffle Packed Single Precision Floating-Point Values
xmmreg2 with xmmreg3 to xmmreg1, imm8
C4: rxb0_1: w xmmreg2 000:C6:11 xmmreg1 xmmreg3: imm
xmmreg2 with mem to xmmreg1, imm8
C4: rxb0_1: w xmmreg2 000:C6:mod xmmreg1 r/m: imm
xmmreglo2 with xmmreglo3 to xmmreg1, imm8
C5: r_xmmreglo2 000:C6:11 xmmreg1 xmmreglo3: imm
xmmreglo2 with mem to xmmreg1, imm8
C5: r_xmmreglo2 000:C6:mod xmmreg1 r/m: imm
ymmreg2 with ymmreg3 to ymmreg1, imm8
C4: rxb0_1: w ymmreg2 100:C6:11 ymmreg1 ymmreg3: imm
ymmreg2 with mem to ymmreg1, imm8
C4: rxb0_1: w ymmreg2 100:C6:mod ymmreg1 r/m: imm
ymmreglo2 with ymmreglo3 to ymmreg1, imm8
C5: r_ymmreglo2 100:C6:11 ymmreg1 ymmreglo3: imm
ymmreglo2 with mem to ymmreg1, imm8
C5: r_ymmreglo2 100:C6:mod ymmreg1 r/m: imm
VSQRTPS - Compute Square Roots of Packed Single Precision Floating-Point Values
xmmreg2 to xmmreg1
C4: rxb0_1: w_F 000:51:11 xmmreg1 xmmreg2
mem to xmmreg1
C4: rxb0_1: w_F 000:51:mod xmmreg1 r/m
xmmreglo to xmmreg1
C5: r_F 000:51:11 xmmreg1 xmmreglo
mem to xmmreg1
C5: r_F 000:51:mod xmmreg1 r/m
ymmreg2 to ymmreg1
C4: rxb0_1: w_F 100:51:11 ymmreg1 ymmreg2
mem to ymmreg1
C4: rxb0_1: w_F 100:51:mod ymmreg1 r/m
ymmreglo to ymmreg1
C5: r_F 100:51:11 ymmreg1 ymmreglo
mem to ymmreg1
C5: r_F 100:51:mod ymmreg1 r/m
VSQRTSS - Compute Square Root of Scalar Single Precision Floating-Point Value
xmmreg2 with xmmreg3 to xmmreg1
C4: rxb0_1: w xmmreg2 010:51:11 xmmreg1 xmmreg3
xmmreg2 with mem to xmmreg1
C4: rxb0_1: w xmmreg2 010:51:mod xmmreg1 r/m
xmmreglo2 with xmmreglo3 to xmmreg1
C5: r_xmmreglo2 010:51:11 xmmreg1 xmmreglo3
xmmreglo2 with mem to xmmreg1
C5: r_xmmreglo2 010:51:mod xmmreg1 r/m
VSTMXCSR - Store MXCSR Register State
MXCSR to mem
C4: rxb0_1: w_F 000:AE:mod 011 r/m
MXCSR to mem
C5: r_F 000:AE:mod 011 r/m
VSUBPS - Subtract Packed Single Precision Floating-Point Values
xmmreg2 with xmmreg3 to xmmreg1
C4: rxb0_1: w xmmreg2 000:5C:11 xmmreg1 xmmreg3
xmmreg2 with mem to xmmreg1
C4: rxb0_1: w xmmreg2 000:5C:mod xmmreg1 r/m
xmmreglo2 with xmmreglo3 to xmmreg1
C5: r_xmmreglo2 000:5C:11 xmmreg1 xmmreglo3
xmmreglo2 with mem to xmmreg1
C5: r_xmmreglo2 000:5C:mod xmmreg1 r/m
ymmreg2 with ymmreg3 to ymmreg1
C4: rxb0_1: w ymmreg2 100:5C:11 ymmreg1 ymmreg3
ymmreg2 with mem to ymmreg1
C4: rxb0_1: w ymmreg2 100:5C:mod ymmreg1 r/m
ymmreglo2 with ymmreglo3 to ymmreg1
C5: r_ymmreglo2 100:5C:11 ymmreg1 ymmreglo3
ymmreglo2 with mem to ymmreg1
C5: r_ymmreglo2 100:5C:mod ymmreg1 r/m
VSUBSS - Subtract Scalar Single Precision Floating-Point Values
xmmreg2 with xmmreg3 to xmmreg1
C4: rxb0_1: w xmmreg2 010:5C:11 xmmreg1 xmmreg3
Vol. 2D B-105
INSTRUCTION FORMATS AND ENCODINGS
Instruction and Format
Encoding
xmmreg2 with mem to xmmreg1
C4: rxb0_1: w xmmreg2 010:5C:mod xmmreg1 r/m
xmmreglo2 with xmmreglo3 to xmmreg1
C5: r_xmmreglo2 010:5C:11 xmmreg1 xmmreglo3
xmmreglo2 with mem to xmmreg1
C5: r_xmmreglo2 010:5C:mod xmmreg1 r/m
VUCOMISS - Unordered Compare Scalar Single Precision Floating-Point Values and Set EFLAGS
xmmreg2 with xmmreg1
C4: rxb0_1: w_F 000:2E:11 xmmreg1 xmmreg2
mem with xmmreg1
C4: rxb0_1: w_F 000:2E:mod xmmreg1 r/m
xmmreglo with xmmreg1
C5: r_F 000:2E:11 xmmreg1 xmmreglo
mem with xmmreg1
C5: r_F 000:2E:mod xmmreg1 r/m
UNPCKHPS - Unpack and Interleave High Packed Single Precision Floating-Point Values
xmmreg2 with xmmreg3 to xmmreg1
C4: rxb0_1: w xmmreg2 000:15:11 xmmreg1 xmmreg3
xmmreg2 with mem to xmmreg1
C4: rxb0_1: w xmmreg2 000:15mod xmmreg1 r/m
ymmreg2 with ymmreg3 to ymmreg1
C4: rxb0_1: w ymmreg2 100:15:11 ymmreg1 ymmreg3
ymmreg2 with mem to ymmreg1
C4: rxb0_1: w ymmreg2 100:15mod ymmreg1 r/m
UNPCKLPS - Unpack and Interleave Low Packed Single Precision Floating-Point Value
xmmreg2 with xmmreg3 to xmmreg1
C4: rxb0_1: w xmmreg2 000:14:11 xmmreg1 xmmreg3
xmmreg2 with mem to xmmreg1
C4: rxb0_1: w xmmreg2 000:14mod xmmreg1 r/m
ymmreg2 with ymmreg3 to ymmreg1
C4: rxb0_1: w ymmreg2 100:14:11 ymmreg1 ymmreg3
ymmreg2 with mem to ymmreg1
C4: rxb0_1: w ymmreg2 100:14mod ymmreg1 r/m
VXORPS - Bitwise Logical XOR for Single Precision Floating-Point Values
xmmreg2 with xmmreg3 to xmmreg1
C4: rxb0_1: w xmmreg2 000:57:11 xmmreg1 xmmreg3
xmmreg2 with mem to xmmreg1
C4: rxb0_1: w xmmreg2 000:57:mod xmmreg1 r/m
xmmreglo2 with xmmreglo3 to xmmreg1
C5: r_xmmreglo2 000:57:11 xmmreg1 xmmreglo3
xmmreglo2 with mem to xmmreg1
C5: r_xmmreglo2 000:57:mod xmmreg1 r/m
ymmreg2 with ymmreg3 to ymmreg1
C4: rxb0_1: w ymmreg2 100:57:11 ymmreg1 ymmreg3
ymmreg2 with mem to ymmreg1
C4: rxb0_1: w ymmreg2 100:57:mod ymmreg1 r/m
ymmreglo2 with ymmreglo3 to ymmreg1
C5: r_ymmreglo2 100:57:11 ymmreg1 ymmreglo3
ymmreglo2 with mem to ymmreg1
C5: r_ymmreglo2 100:57:mod ymmreg1 r/m
VBROADCAST -Load with Broadcast
mem to xmmreg1
C4: rxb0_2: 0_F 001:18:mod xmmreg1 r/m
mem to ymmreg1
C4: rxb0_2: 0_F 101:18:mod ymmreg1 r/m
mem to ymmreg1
C4: rxb0_2: 0_F 101:19:mod ymmreg1 r/m
mem to ymmreg1
C4: rxb0_2: 0_F 101:1A:mod ymmreg1 r/m
VEXTRACTF128 - Extract Packed Floating-Point Values
ymmreg2 to xmmreg1, imm8
C4: rxb0_3: 0_F 001:19:11 xmmreg1 ymmreg2: imm
ymmreg2 to mem, imm8
C4: rxb0_3: 0_F 001:19:mod r/m ymmreg2: imm
VINSERTF128 - Insert Packed Floating-Point Values
xmmreg3 and merge with ymmreg2 to ymmreg1, imm8
C4: rxb0_3: 0 ymmreg2101:18:11 ymmreg1 xmmreg3: imm
mem and merge with ymmreg2 to ymmreg1, imm8
C4: rxb0_3: 0 ymmreg2 101:18:mod ymmreg1 r/m: imm
VPERMILPD - Permute Double Precision Floating-Point Values
B-106
Vol. 2D
INSTRUCTION FORMATS AND ENCODINGS
Instruction and Format
Encoding
xmmreg2 with xmmreg3 to xmmreg1
C4: rxb0_2: 0 xmmreg2 001:0D:11 xmmreg1 xmmreg3
xmmreg2 with mem to xmmreg1
C4: rxb0_2: 0 xmmreg2 001:0D:mod xmmreg1 r/m
ymmreg2 with ymmreg3 to ymmreg1
C4: rxb0_2: 0 ymmreg2 101:0D:11 ymmreg1 ymmreg3
ymmreg2 with mem to ymmreg1
C4: rxb0_2: 0 ymmreg2 101:0D:mod ymmreg1 r/m
xmmreg2 to xmmreg1, imm
C4: rxb0_3: 0_F 001:05:11 xmmreg1 xmmreg2: imm
mem to xmmreg1, imm
C4: rxb0_3: 0_F 001:05:mod xmmreg1 r/m: imm
ymmreg2 to ymmreg1, imm
C4: rxb0_3: 0_F 101:05:11 ymmreg1 ymmreg2: imm
mem to ymmreg1, imm
C4: rxb0_3: 0_F 101:05:mod ymmreg1 r/m: imm
VPERMILPS - Permute Single Precision Floating-Point Values
xmmreg2 with xmmreg3 to xmmreg1
C4: rxb0_2: 0 xmmreg2 001:0C:11 xmmreg1 xmmreg3
xmmreg2 with mem to xmmreg1
C4: rxb0_2: 0 xmmreg2 001:0C:mod xmmreg1 r/m
xmmreg2 to xmmreg1, imm
C4: rxb0_3: 0_F 001:04:11 xmmreg1 xmmreg2: imm
mem to xmmreg1, imm
C4: rxb0_3: 0_F 001:04:mod xmmreg1 r/m: imm
ymmreg2 with ymmreg3 to ymmreg1
C4: rxb0_2: 0 ymmreg2 101:0C:11 ymmreg1 ymmreg3
ymmreg2 with mem to ymmreg1
C4: rxb0_2: 0 ymmreg2 101:0C:mod ymmreg1 r/m
ymmreg2 to ymmreg1, imm
C4: rxb0_3: 0_F 101:04:11 ymmreg1 ymmreg2: imm
mem to ymmreg1, imm
C4: rxb0_3: 0_F 101:04:mod ymmreg1 r/m: imm
VPERM2F128 - Permute Floating-Point Values
ymmreg2 with ymmreg3 to ymmreg1
C4: rxb0_3: 0 ymmreg2 101:06:11 ymmreg1 ymmreg3: imm
ymmreg2 with mem to ymmreg1
C4: rxb0_3: 0 ymmreg2 101:06:mod ymmreg1 r/m: imm
VTESTPD/VTESTPS - Packed Bit Test
xmmreg2 to xmmreg1
C4: rxb0_2: 0_F 001:0E:11 xmmreg2 xmmreg1
mem to xmmreg1
C4: rxb0_2: 0_F 001:0E:mod xmmreg2 r/m
ymmreg2 to ymmreg1
C4: rxb0_2: 0_F 101:0E:11 ymmreg2 ymmreg1
mem to ymmreg1
C4: rxb0_2: 0_F 101:0E:mod ymmreg2 r/m
xmmreg2 to xmmreg1
C4: rxb0_2: 0_F 001:0F:11 xmmreg1 xmmreg2: imm
mem to xmmreg1
C4: rxb0_2: 0_F 001:0F:mod xmmreg1 r/m: imm
ymmreg2 to ymmreg1
C4: rxb0_2: 0_F 101:0F:11 ymmreg1 ymmreg2: imm
mem to ymmreg1
C4: rxb0_2: 0_F 101:0F:mod ymmreg1 r/m: imm
NOTES:
1. The term “lo” refers to the lower eight registers, 0-7
Vol. 2D B-107
INSTRUCTION FORMATS AND ENCODINGS
B.17
FLOATING-POINT INSTRUCTION FORMATS AND ENCODINGS
Table B-38 shows the five different formats used for floating-point instructions. In all cases, instructions are at
least two bytes long and begin with the bit pattern 11011.
Table B-38. General Floating-Point Instruction Formats
Instruction
First Byte
Second Byte
Optional Fields
1
11011
OPA
1
mod
1
OPB
r/m
s-i-b
disp
2
11011
MF
OPA
mod
OPB
r/m
s-i-b
disp
3
11011
d
P
OPA
1
1
OPB
R
ST(i)
4
11011
0
0
1
1
1
1
OP
5
11011
0
1
1
1
1
1
OP
15-11
10
9
8
7
6
5
4
3
2
1
0
MF = Memory Format
R XOR d = 0 - Destination OP Source
00 - 32-bit real
R XOR d = 1 - Source OP Destination
01 - 32-bit integer
10 - 64-bit real
ST(i) = Register stack element i
11 - 16-bit integer
000 = Stack Top
P = Pop
001 = Second stack element
0 - Do not pop stack
⋅
1 - Pop stack after operation
⋅
d = Destination
⋅
0 - Destination is ST(0)
111 = Eighth stack element
1 - Destination is ST(i)
The Mod and R/M fields of the ModR/M byte have the same interpretation as the corresponding fields of the integer
instructions. The SIB byte and disp (displacement) are optionally present in instructions that have Mod and R/M
fields. Their presence depends on the values of Mod and R/M, as for integer instructions.
Table B-39 shows the formats and encodings of the floating-point instructions.
Table B-39. Floating-Point Instruction Formats and Encodings
Instruction and Format
Encoding
F2XM1 - Compute 2ST(0) - 1
11011 001 : 1111 0000
FABS - Absolute Value
11011 001 : 1110 0001
FADD - Add
ST(0) := ST(0) + 32-bit memory
11011 000 : mod 000 r/m
ST(0) := ST(0) + 64-bit memory
11011 100 : mod 000 r/m
ST(d) := ST(0) + ST(i)
11011 d00 : 11 000 ST(i)
FADDP - Add and Pop
ST(0) := ST(0) + ST(i)
11011 110 : 11 000 ST(i)
FBLD - Load Binary Coded Decimal
11011 111 : mod 100 r/m
FBSTP - Store Binary Coded Decimal and Pop
11011 111 : mod 110 r/m
FCHS - Change Sign
11011 001 : 1110 0000
FCLEX - Clear Exceptions
11011 011 : 1110 0010
FCOM - Compare Real
B-108
Vol. 2D
INSTRUCTION FORMATS AND ENCODINGS
Table B-39. Floating-Point Instruction Formats and Encodings (Contd.)
Instruction and Format
Encoding
32-bit memory
11011 000 : mod 010 r/m
64-bit memory
11011 100 : mod 010 r/m
ST(i)
11011 000 : 11 010 ST(i)
FCOMP - Compare Real and Pop
32-bit memory
11011 000 : mod 011 r/m
64-bit memory
11011 100 : mod 011 r/m
ST(i)
11011 000 : 11 011 ST(i)
FCOMPP - Compare Real and Pop Twice
11011 110 : 11 011 001
FCOMIP - Compare Real, Set EFLAGS, and Pop
11011 111 : 11 110 ST(i)
FCOS - Cosine of ST(0)
11011 001 : 1111 1111
FDECSTP - Decrement Stack-Top Pointer
11011 001 : 1111 0110
FDIV - Divide
ST(0) := ST(0) ÷ 32-bit memory
11011 000 : mod 110 r/m
ST(0) := ST(0) ÷ 64-bit memory
11011 100 : mod 110 r/m
ST(d) := ST(0) ÷ ST(i)
11011 d00 : 1111 R ST(i)
FDIVP - Divide and Pop
ST(0) := ST(0) ÷ ST(i)
11011 110 : 1111 1 ST(i)
FDIVR - Reverse Divide
ST(0) := 32-bit memory ÷ ST(0)
11011 000 : mod 111 r/m
ST(0) := 64-bit memory ÷ ST(0)
11011 100 : mod 111 r/m
ST(d) := ST(i) ÷ ST(0)
11011 d00 : 1111 R ST(i)
FDIVRP - Reverse Divide and Pop
ST(0) := ST(i) ÷ ST(0)
11011 110 : 1111 0 ST(i)
FFREE - Free ST(i) Register
11011 101 : 1100 0 ST(i)
FIADD - Add Integer
ST(0) := ST(0) + 16-bit memory
11011 110 : mod 000 r/m
ST(0) := ST(0) + 32-bit memory
11011 010 : mod 000 r/m
FICOM - Compare Integer
16-bit memory
11011 110 : mod 010 r/m
32-bit memory
11011 010 : mod 010 r/m
FICOMP - Compare Integer and Pop
16-bit memory
11011 110 : mod 011 r/m
32-bit memory
11011 010 : mod 011 r/m
FIDIV - Divide
ST(0) := ST(0) ÷ 16-bit memory
11011 110 : mod 110 r/m
ST(0) := ST(0) ÷ 32-bit memory
11011 010 : mod 110 r/m
FIDIVR - Reverse Divide
ST(0) := 16-bit memory ÷ ST(0)
11011 110 : mod 111 r/m
Vol. 2D B-109
INSTRUCTION FORMATS AND ENCODINGS
Table B-39. Floating-Point Instruction Formats and Encodings (Contd.)
Instruction and Format
Encoding
ST(0) := 32-bit memory ÷ ST(0)
11011 010 : mod 111 r/m
FILD - Load Integer
16-bit memory
11011 111 : mod 000 r/m
32-bit memory
11011 011 : mod 000 r/m
64-bit memory
11011 111 : mod 101 r/m
FIMUL- Multiply
ST(0) := ST(0) × 16-bit memory
11011 110 : mod 001 r/m
ST(0) := ST(0) × 32-bit memory
11011 010 : mod 001 r/m
FINCSTP - Increment Stack Pointer
11011 001 : 1111 0111
FINIT - Initialize Floating-Point Unit
FIST - Store Integer
16-bit memory
11011 111 : mod 010 r/m
32-bit memory
11011 011 : mod 010 r/m
FISTP - Store Integer and Pop
16-bit memory
11011 111 : mod 011 r/m
32-bit memory
11011 011 : mod 011 r/m
64-bit memory
11011 111 : mod 111 r/m
FISUB - Subtract
ST(0) := ST(0) - 16-bit memory
11011 110 : mod 100 r/m
ST(0) := ST(0) - 32-bit memory
11011 010 : mod 100 r/m
FISUBR - Reverse Subtract
ST(0) := 16-bit memory - ST(0)
11011 110 : mod 101 r/m
ST(0) := 32-bit memory - ST(0)
11011 010 : mod 101 r/m
FLD - Load Real
32-bit memory
11011 001 : mod 000 r/m
64-bit memory
11011 101 : mod 000 r/m
80-bit memory
11011 011 : mod 101 r/m
ST(i)
11011 001 : 11 000 ST(i)
FLD1 - Load +1.0 into ST(0)
11011 001 : 1110 1000
FLDCW - Load Control Word
11011 001 : mod 101 r/m
FLDENV - Load FPU Environment
11011 001 : mod 100 r/m
FLDL2E - Load log2(ε) into ST(0)
11011 001 : 1110 1010
FLDL2T - Load log2(10) into ST(0)
11011 001 : 1110 1001
FLDLG2 - Load log10(2) into ST(0)
11011 001 : 1110 1100
FLDLN2 - Load logε(2) into ST(0)
11011 001 : 1110 1101
FLDPI - Load π into ST(0)
11011 001 : 1110 1011
FLDZ - Load +0.0 into ST(0)
11011 001 : 1110 1110
FMUL - Multiply
B-110
Vol. 2D
INSTRUCTION FORMATS AND ENCODINGS
Table B-39. Floating-Point Instruction Formats and Encodings (Contd.)
Instruction and Format
Encoding
ST(0) := ST(0) × 32-bit memory
11011 000 : mod 001 r/m
ST(0) := ST(0) × 64-bit memory
11011 100 : mod 001 r/m
ST(d) := ST(0) × ST(i)
11011 d00 : 1100 1 ST(i)
FMULP - Multiply
ST(i) := ST(0) × ST(i)
11011 110 : 1100 1 ST(i)
FNOP - No Operation
11011 001 : 1101 0000
FPATAN - Partial Arctangent
11011 001 : 1111 0011
FPREM - Partial Remainder
11011 001 : 1111 1000
FPREM1 - Partial Remainder (IEEE)
11011 001 : 1111 0101
FPTAN - Partial Tangent
11011 001 : 1111 0010
FRNDINT - Round to Integer
11011 001 : 1111 1100
FRSTOR - Restore FPU State
11011 101 : mod 100 r/m
FSAVE - Store FPU State
11011 101 : mod 110 r/m
FSCALE - Scale
11011 001 : 1111 1101
FSIN - Sine
11011 001 : 1111 1110
FSINCOS - Sine and Cosine
11011 001 : 1111 1011
FSQRT - Square Root
11011 001 : 1111 1010
FST - Store Real
32-bit memory
11011 001 : mod 010 r/m
64-bit memory
11011 101 : mod 010 r/m
ST(i)
11011 101 : 11 010 ST(i)
FSTCW - Store Control Word
11011 001 : mod 111 r/m
FSTENV - Store FPU Environment
11011 001 : mod 110 r/m
FSTP - Store Real and Pop
32-bit memory
11011 001 : mod 011 r/m
64-bit memory
11011 101 : mod 011 r/m
80-bit memory
11011 011 : mod 111 r/m
ST(i)
11011 101 : 11 011 ST(i)
FSTSW - Store Status Word into AX
11011 111 : 1110 0000
FSTSW - Store Status Word into Memory
11011 101 : mod 111 r/m
FSUB - Subtract
ST(0) := ST(0) - 32-bit memory
11011 000 : mod 100 r/m
ST(0) := ST(0) - 64-bit memory
11011 100 : mod 100 r/m
ST(d) := ST(0) - ST(i)
11011 d00 : 1110 R ST(i)
FSUBP - Subtract and Pop
ST(0) := ST(0) - ST(i)
11011 110 : 1110 1 ST(i)
FSUBR - Reverse Subtract
ST(0) := 32-bit memory - ST(0)
11011 000 : mod 101 r/m
Vol. 2D B-111
INSTRUCTION FORMATS AND ENCODINGS
Table B-39. Floating-Point Instruction Formats and Encodings (Contd.)
Instruction and Format
Encoding
ST(0) := 64-bit memory - ST(0)
11011 100 : mod 101 r/m
ST(d) := ST(i) - ST(0)
11011 d00 : 1110 R ST(i)
FSUBRP - Reverse Subtract and Pop
ST(i) := ST(i) - ST(0)
11011 110 : 1110 0 ST(i)
FTST - Test
11011 001 : 1110 0100
FUCOM - Unordered Compare Real
11011 101 : 1110 0 ST(i)
FUCOMP - Unordered Compare Real and Pop
11011 101 : 1110 1 ST(i)
FUCOMPP - Unordered Compare Real and Pop Twice
11011 010 : 1110 1001
FUCOMI - Unorderd Compare Real and Set EFLAGS
11011 011 : 11 101 ST(i)
FUCOMIP - Unorderd Compare Real, Set EFLAGS, and Pop
11011 111 : 11 101 ST(i)
FXAM - Examine
11011 001 : 1110 0101
FXCH - Exchange ST(0) and ST(i)
11011 001 : 1100 1 ST(i)
FXTRACT - Extract Exponent and Significand
11011 001 : 1111 0100
FYL2X - ST(1) × log2(ST(0))
11011 001 : 1111 0001
FYL2XP1 - ST(1) × log2(ST(0) + 1.0)
11011 001 : 1111 1001
FWAIT - Wait until FPU Ready
1001 1011 (same instruction as WAIT)
B.18
VMX INSTRUCTIONS
Table B-40 describes virtual-machine extensions (VMX).
Table B-40. Encodings for VMX Instructions
Instruction and Format
Encoding
INVEPT-Invalidate Cached EPT Mappings
Descriptor m128 according to reg
01100110 00001111 00111000 10000000: mod reg r/m
INVVPID-Invalidate Cached VPID Mappings
Descriptor m128 according to reg
01100110 00001111 00111000 10000001: mod reg r/m
VMCALL-Call to VM Monitor
Call VMM: causes VM exit
00001111 00000001 11000001
VMCLEAR-Clear Virtual-Machine Control Structure
mem32:VMCS_data_ptr
01100110 00001111 11000111: mod 110 r/m
mem64:VMCS_data_ptr
01100110 00001111 11000111: mod 110 r/m
VMFUNC-Invoke VM Function
Invoke VM function specified in EAX
00001111 00000001 11010100
VMLAUNCH-Launch Virtual Machine
Launch VM managed by Current_VMCS
00001111 00000001 11000010
VMRESUME-Resume Virtual Machine
Resume VM managed by Current_VMCS
00001111 00000001 11000011
VMPTRLD-Load Pointer to Virtual-Machine Control Structure
mem32 to Current_VMCS_ptr
00001111 11000111: mod 110 r/m
B-112
Vol. 2D
INSTRUCTION FORMATS AND ENCODINGS
Table B-40. Encodings for VMX Instructions
Instruction and Format
Encoding
mem64 to Current_VMCS_ptr
00001111 11000111: mod 110 r/m
VMPTRST-Store Pointer to Virtual-Machine Control Structure
Current_VMCS_ptr to mem32
00001111 11000111: mod 111 r/m
Current_VMCS_ptr to mem64
00001111 11000111: mod 111 r/m
VMREAD-Read Field from Virtual-Machine Control Structure
r32 (VMCS_fieldn) to r32
00001111 01111000: 11 reg2 reg1
r32 (VMCS_fieldn) to mem32
00001111 01111000: mod r32 r/m
r64 (VMCS_fieldn) to r64
00001111 01111000: 11 reg2 reg1
r64 (VMCS_fieldn) to mem64
00001111 01111000: mod r64 r/m
VMWRITE-Write Field to Virtual-Machine Control Structure
r32 to r32 (VMCS_fieldn)
00001111 01111001: 11 reg1 reg2
mem32 to r32 (VMCS_fieldn)
00001111 01111001: mod r32 r/m
r64 to r64 (VMCS_fieldn)
00001111 01111001: 11 reg1 reg2
mem64 to r64 (VMCS_fieldn)
00001111 01111001: mod r64 r/m
VMXOFF-Leave VMX Operation
Leave VMX.
00001111 00000001 11000100
VMXON-Enter VMX Operation
Enter VMX.
11110011 000011111 11000111: mod 110 r/m
B.19
SMX INSTRUCTIONS
Table B-41 describes Safer Mode Extensions (SMX). GETSEC leaf functions are selected by a valid value in EAX on input.
Table B-41. Encodings for SMX Instructions
Instruction and Format
Encoding
GETSEC-GETSEC leaf functions are selected by the value in EAX on input
GETSEC[CAPABILITIES]
00001111 00110111 (EAX= 0)
GETSEC[ENTERACCS]
00001111 00110111 (EAX= 2)
GETSEC[EXITAC]
00001111 00110111 (EAX= 3)
GETSEC[SENTER]
00001111 00110111 (EAX= 4)
GETSEC[SEXIT]
00001111 00110111 (EAX= 5)
GETSEC[PARAMETERS]
00001111 00110111 (EAX= 6)
GETSEC[SMCTRL]
00001111 00110111 (EAX= 7)
GETSEC[WAKEUP]
00001111 00110111 (EAX= 8)
Vol. 2D B-113
INSTRUCTION FORMATS AND ENCODINGS
B-114
Vol. 2D
APPENDIX C
INTEL® C/C++ COMPILER INTRINSICS AND FUNCTIONAL EQUIVALENTS
The two tables in this appendix itemize the Intel C/C++ compiler intrinsics and functional equivalents for the Intel
MMX technology, SSE, SSE2, SSE3, and SSSE3 instructions.
There may be additional intrinsics that do not have an instruction equivalent. It is strongly recommended that the
reader reference the compiler documentation for the complete list of supported intrinsics. Please refer to
Table C-1 presents simple intrinsics and Table C-2 presents composite intrinsics. Some intrinsics are “composites”
because they require more than one instruction to implement them.
Intel C/C++ Compiler intrinsic names reflect the following naming conventions:
_mm_<intrin_op>_<suffix>
where:
<intrin_op>
Indicates the intrinsics basic operation; for example, add for addition and sub for subtrac-
tion
<suffix>
Denotes the type of data operated on by the instruction. The first one or two letters of
each suffix denotes whether the data is packed (p), extended packed (ep), or scalar (s).
The remaining letters denote the type:
s
single precision floating-point
d
double precision floating-point
i128
signed 128-bit integer
i64
signed 64-bit integer
u64
unsigned 64-bit integer
i32
signed 32-bit integer
u32
unsigned 32-bit integer
i16
signed 16-bit integer
u16
unsigned 16-bit integer
i8
signed 8-bit integer
u8
unsigned 8-bit integer
The variable r is generally used for the intrinsic's return value. A number appended to a variable name indicates the
element of a packed object. For example, r0 is the lowest word of r.
The packed values are represented in right-to-left order, with the lowest value being used for scalar operations.
Consider the following example operation:
double a[2] = {1.0, 2.0};
__m128d t = _mm_load_pd(a);
The result is the same as either of the following:
__m128d t = _mm_set_pd(2.0, 1.0);
__m128d t = _mm_setr_pd(1.0, 2.0);
In other words, the XMM register that holds the value t will look as follows:
2.0
1.0
127
6463
0
Vol. 2D C-1
INTEL® C/C++ COMPILER INTRINSICS AND FUNCTIONAL EQUIVALENTS
The “scalar” element is 1.0. Due to the nature of the instruction, some intrinsics require their arguments to be
immediates (constant integer literals).
To use an intrinsic in your code, insert a line with the following syntax:
data_type intrinsic_name (parameters)
Where:
data_type
Is the return data type, which can be either void, int, __m64, __m128, __m128d, or
__m128i. Only the _mm_empty intrinsic returns void.
intrinsic_name
Is the name of the intrinsic, which behaves like a function that you can use in your C/C++
code instead of in-lining the actual instruction.
parameters
Represents the parameters required by each intrinsic.
C.1
SIMPLE INTRINSICS
NOTE
For detailed descriptions of the intrinsics in Table C-1, see the corresponding mnemonic in Chapter
3, “Instruction Set Reference, A-L‚” of the Intel® 64 and IA-32 Architectures Software Developer’s
Manual, Volume 2A; Chapter 4, “Instruction Set Reference, M-U‚” of the Intel® 64 and IA-32 Archi-
tectures Software Developer’s Manual, Volume 2B; Chapter 5, “Instruction Set Reference, V,” of the
Intel® 64 and IA-32 Architectures Software Developer’s Manual, Volume 2C; or Chapter 6,
“Instruction Set Reference, W-Z,” of the Intel® 64 and IA-32 Architectures Software Developer’s
Manual, Volume 2D.
Table C-1. Simple Intrinsics
Mnemonic
Intrinsic
ADDPD
__m128d _mm_add_pd(__m128d a, __m128d b)
ADDPS
__m128 _mm_add_ps(__m128 a, __m128 b)
ADDSD
__m128d _mm_add_sd(__m128d a, __m128d b)
ADDSS
__m128 _mm_add_ss(__m128 a, __m128 b)
ADDSUBPD
__m128d _mm_addsub_pd(__m128d a, __m128d b)
ADDSUBPS
__m128 _mm_addsub_ps(__m128 a, __m128 b)
AESDEC
__m128i _mm_aesdec (__m128i, __m128i)
AESDECLAST
__m128i _mm_aesdeclast (__m128i, __m128i)
AESENC
__m128i _mm_aesenc (__m128i, __m128i)
AESENCLAST
__m128i _mm_aesenclast (__m128i, __m128i)
AESIMC
__m128i _mm_aesimc (__m128i)
AESKEYGENASSIST
__m128i _mm_aesimc (__m128i, const int)
ANDNPD
__m128d _mm_andnot_pd(__m128d a, __m128d b)
ANDNPS
__m128 _mm_andnot_ps(__m128 a, __m128 b)
ANDPD
__m128d _mm_and_pd(__m128d a, __m128d b)
ANDPS
__m128 _mm_and_ps(__m128 a, __m128 b)
BLENDPD
__m128d _mm_blend_pd(__m128d v1, __m128d v2, const int mask)
BLENDPS
__m128 _mm_blend_ps(__m128 v1, __m128 v2, const int mask)
BLENDVPD
__m128d _mm_blendv_pd(__m128d v1, __m128d v2, __m128d v3)
BLENDVPS
__m128 _mm_blendv_ps(__m128 v1, __m128 v2, __m128 v3)
CLFLUSH
void _mm_clflush(void const *p)
C-2
Vol. 2D
INTEL® C/C++ COMPILER INTRINSICS AND FUNCTIONAL EQUIVALENTS
Table C-1. Simple Intrinsics (Contd.)
Mnemonic
Intrinsic
CMPPD
__m128d _mm_cmpeq_pd(__m128d a, __m128d b)
__m128d _mm_cmplt_pd(__m128d a, __m128d b)
__m128d _mm_cmple_pd(__m128d a, __m128d b)
__m128d _mm_cmpgt_pd(__m128d a, __m128d b)
__m128d _mm_cmpge_pd(__m128d a, __m128d b)
__m128d _mm_cmpneq_pd(__m128d a, __m128d b)
__m128d _mm_cmpnlt_pd(__m128d a, __m128d b)
__m128d _mm_cmpngt_pd(__m128d a, __m128d b)
__m128d _mm_cmpnge_pd(__m128d a, __m128d b)
__m128d _mm_cmpord_pd(__m128d a, __m128d b)
__m128d _mm_cmpunord_pd(__m128d a, __m128d b)
__m128d _mm_cmpnle_pd(__m128d a, __m128d b)
CMPPS
__m128 _mm_cmpeq_ps(__m128 a, __m128 b)
__m128 _mm_cmplt_ps(__m128 a, __m128 b)
__m128 _mm_cmple_ps(__m128 a, __m128 b)
__m128 _mm_cmpgt_ps(__m128 a, __m128 b)
__m128 _mm_cmpge_ps(__m128 a, __m128 b)
__m128 _mm_cmpneq_ps(__m128 a, __m128 b)
__m128 _mm_cmpnlt_ps(__m128 a, __m128 b)
__m128 _mm_cmpngt_ps(__m128 a, __m128 b)
__m128 _mm_cmpnge_ps(__m128 a, __m128 b)
__m128 _mm_cmpord_ps(__m128 a, __m128 b)
__m128 _mm_cmpunord_ps(__m128 a, __m128 b)
__m128 _mm_cmpnle_ps(__m128 a, __m128 b)
CMPSD
__m128d _mm_cmpeq_sd(__m128d a, __m128d b)
__m128d _mm_cmplt_sd(__m128d a, __m128d b)
__m128d _mm_cmple_sd(__m128d a, __m128d b)
__m128d _mm_cmpgt_sd(__m128d a, __m128d b)
__m128d _mm_cmpge_sd(__m128d a, __m128d b)
__m128 _mm_cmpneq_sd(__m128d a, __m128d b)
__m128 _mm_cmpnlt_sd(__m128d a, __m128d b)
__m128d _mm_cmpnle_sd(__m128d a, __m128d b)
__m128d _mm_cmpngt_sd(__m128d a, __m128d b)
__m128d _mm_cmpnge_sd(__m128d a, __m128d b)
__m128d _mm_cmpord_sd(__m128d a, __m128d b)
__m128d _mm_cmpunord_sd(__m128d a, __m128d b)
CMPSS
__m128 _mm_cmpeq_ss(__m128 a, __m128 b)
__m128 _mm_cmplt_ss(__m128 a, __m128 b)
__m128 _mm_cmple_ss(__m128 a, __m128 b)
__m128 _mm_cmpgt_ss(__m128 a, __m128 b)
__m128 _mm_cmpge_ss(__m128 a, __m128 b)
Vol. 2D C-3
INTEL® C/C++ COMPILER INTRINSICS AND FUNCTIONAL EQUIVALENTS
Table C-1. Simple Intrinsics (Contd.)
Mnemonic
Intrinsic
__m128 _mm_cmpneq_ss(__m128 a, __m128 b)
__m128 _mm_cmpnlt_ss(__m128 a, __m128 b)
__m128 _mm_cmpnle_ss(__m128 a, __m128 b)
__m128 _mm_cmpngt_ss(__m128 a, __m128 b)
__m128 _mm_cmpnge_ss(__m128 a, __m128 b)
__m128 _mm_cmpord_ss(__m128 a, __m128 b)
__m128 _mm_cmpunord_ss(__m128 a, __m128 b)
COMISD
int _mm_comieq_sd(__m128d a, __m128d b)
int _mm_comilt_sd(__m128d a, __m128d b)
int _mm_comile_sd(__m128d a, __m128d b)
int _mm_comigt_sd(__m128d a, __m128d b)
int _mm_comige_sd(__m128d a, __m128d b)
int _mm_comineq_sd(__m128d a, __m128d b)
COMISS
int _mm_comieq_ss(__m128 a, __m128 b)
int _mm_comilt_ss(__m128 a, __m128 b)
int _mm_comile_ss(__m128 a, __m128 b)
int _mm_comigt_ss(__m128 a, __m128 b)
int _mm_comige_ss(__m128 a, __m128 b)
int _mm_comineq_ss(__m128 a, __m128 b)
CRC32
unsigned int _mm_crc32_u8(unsigned int crc, unsigned char data)
unsigned int _mm_crc32_u16(unsigned int crc, unsigned short data)
unsigned int _mm_crc32_u32(unsigned int crc, unsigned int data)
unsigned __int64 _mm_crc32_u64(unsigned __int64 crc, unsigned __int64 data)
CVTDQ2PD
__m128d _mm_cvtepi32_pd(__m128i a)
CVTDQ2PS
__m128 _mm_cvtepi32_ps(__m128i a)
CVTPD2DQ
__m128i _mm_cvtpd_epi32(__m128d a)
CVTPD2PI
__m64 _mm_cvtpd_pi32(__m128d a)
CVTPD2PS
__m128 _mm_cvtpd_ps(__m128d a)
CVTPI2PD
__m128d _mm_cvtpi32_pd(__m64 a)
CVTPI2PS
__m128 _mm_cvt_pi2ps(__m128 a, __m64 b)
__m128 _mm_cvtpi32_ps(__m128 a, __m64 b)
CVTPS2DQ
__m128i _mm_cvtps_epi32(__m128 a)
CVTPS2PD
__m128d _mm_cvtps_pd(__m128 a)
CVTPS2PI
__m64 _mm_cvt_ps2pi(__m128 a)
__m64 _mm_cvtps_pi32(__m128 a)
CVTSD2SI
int _mm_cvtsd_si32(__m128d a)
CVTSD2SS
__m128 _mm_cvtsd_ss(__m128 a, __m128d b)
CVTSI2SD
__m128d _mm_cvtsi32_sd(__m128d a, int b)
CVTSI2SS
__m128 _mm_cvt_si2ss(__m128 a, int b)
__m128 _mm_cvtsi32_ss(__m128 a, int b)
__m128 _mm_cvtsi64_ss(__m128 a, __int64 b)
CVTSS2SD
__m128d _mm_cvtss_sd(__m128d a, __m128 b)
C-4
Vol. 2D
INTEL® C/C++ COMPILER INTRINSICS AND FUNCTIONAL EQUIVALENTS
Table C-1. Simple Intrinsics (Contd.)
Mnemonic
Intrinsic
CVTSS2SI
int _mm_cvt_ss2si(__m128 a)
int _mm_cvtss_si32(__m128 a)
CVTTPD2DQ
__m128i _mm_cvttpd_epi32(__m128d a)
CVTTPD2PI
__m64 _mm_cvttpd_pi32(__m128d a)
CVTTPS2DQ
__m128i _mm_cvttps_epi32(__m128 a)
CVTTPS2PI
__m64 _mm_cvtt_ps2pi(__m128 a)
__m64 _mm_cvttps_pi32(__m128 a)
CVTTSD2SI
int _mm_cvttsd_si32(__m128d a)
CVTTSS2SI
int _mm_cvtt_ss2si(__m128 a)
int _mm_cvttss_si32(__m128 a)
__m64 _mm_cvtsi32_si64(int i)
int _mm_cvtsi64_si32(__m64 m)
DIVPD
__m128d _mm_div_pd(__m128d a, __m128d b)
DIVPS
__m128 _mm_div_ps(__m128 a, __m128 b)
DIVSD
__m128d _mm_div_sd(__m128d a, __m128d b)
DIVSS
__m128 _mm_div_ss(__m128 a, __m128 b)
DPPD
__m128d _mm_dp_pd(__m128d a, __m128d b, const int mask)
DPPS
__m128 _mm_dp_ps(__m128 a, __m128 b, const int mask)
EMMS
void _mm_empty()
EXTRACTPS
int _mm_extract_ps(__m128 src, const int ndx)
HADDPD
__m128d _mm_hadd_pd(__m128d a, __m128d b)
HADDPS
__m128 _mm_hadd_ps(__m128 a, __m128 b)
HSUBPD
__m128d _mm_hsub_pd(__m128d a, __m128d b)
HSUBPS
__m128 _mm_hsub_ps(__m128 a, __m128 b)
INSERTPS
__m128 _mm_insert_ps(__m128 dst, __m128 src, const int ndx)
LDDQU
__m128i _mm_lddqu_si128(__m128i const *p)
LDMXCSR
__mm_setcsr(unsigned int i)
LFENCE
void _mm_lfence(void)
MASKMOVDQU
void _mm_maskmoveu_si128(__m128i d, __m128i n, char *p)
MASKMOVQ
void _mm_maskmove_si64(__m64 d, __m64 n, char *p)
MAXPD
__m128d _mm_max_pd(__m128d a, __m128d b)
MAXPS
__m128 _mm_max_ps(__m128 a, __m128 b)
MAXSD
__m128d _mm_max_sd(__m128d a, __m128d b)
MAXSS
__m128 _mm_max_ss(__m128 a, __m128 b)
MFENCE
void _mm_mfence(void)
MINPD
__m128d _mm_min_pd(__m128d a, __m128d b)
MINPS
__m128 _mm_min_ps(__m128 a, __m128 b)
MINSD
__m128d _mm_min_sd(__m128d a, __m128d b)
MINSS
__m128 _mm_min_ss(__m128 a, __m128 b)
MONITOR
void _mm_monitor(void const *p, unsigned extensions, unsigned hints)
MOVAPD
__m128d _mm_load_pd(double * p)
void_mm_store_pd(double *p, __m128d a)
Vol. 2D C-5
INTEL® C/C++ COMPILER INTRINSICS AND FUNCTIONAL EQUIVALENTS
Table C-1. Simple Intrinsics (Contd.)
Mnemonic
Intrinsic
MOVAPS
__m128 _mm_load_ps(float * p)
void_mm_store_ps(float *p, __m128 a)
MOVD
__m128i _mm_cvtsi32_si128(int a)
int _mm_cvtsi128_si32(__m128i a)
__m64 _mm_cvtsi32_si64(int a)
int _mm_cvtsi64_si32(__m64 a)
MOVDDUP
__m128d _mm_movedup_pd(__m128d a)
__m128d _mm_loaddup_pd(double const * dp)
MOVDQA
__m128i _mm_load_si128(__m128i * p)
void_mm_store_si128(__m128i *p, __m128i a)
MOVDQU
__m128i _mm_loadu_si128(__m128i * p)
void_mm_storeu_si128(__m128i *p, __m128i a)
MOVDQ2Q
__m64 _mm_movepi64_pi64(__m128i a)
MOVHLPS
__m128 _mm_movehl_ps(__m128 a, __m128 b)
MOVHPD
__m128d _mm_loadh_pd(__m128d a, double * p)
void _mm_storeh_pd(double * p, __m128d a)
MOVHPS
__m128 _mm_loadh_pi(__m128 a, __m64 * p)
void _mm_storeh_pi(__m64 * p, __m128 a)
MOVLPD
__m128d _mm_loadl_pd(__m128d a, double * p)
void _mm_storel_pd(double * p, __m128d a)
MOVLPS
__m128 _mm_loadl_pi(__m128 a, __m64 *p)
void_mm_storel_pi(__m64 * p, __m128 a)
MOVLHPS
__m128 _mm_movelh_ps(__m128 a, __m128 b)
MOVMSKPD
int _mm_movemask_pd(__m128d a)
MOVMSKPS
int _mm_movemask_ps(__m128 a)
MOVNTDQA
__m128i _mm_stream_load_si128(__m128i *p)
MOVNTDQ
void_mm_stream_si128(__m128i * p, __m128i a)
MOVNTPD
void_mm_stream_pd(double * p, __m128d a)
MOVNTPS
void_mm_stream_ps(float * p, __m128 a)
MOVNTI
void_mm_stream_si32(int * p, int a)
MOVNTQ
void_mm_stream_pi(__m64 * p, __m64 a)
MOVQ
__m128i _mm_loadl_epi64(__m128i * p)
void_mm_storel_epi64(_m128i * p, __m128i a)
__m128i _mm_move_epi64(__m128i a)
MOVQ2DQ
__m128i _mm_movpi64_epi64(__m64 a)
MOVSD
__m128d _mm_load_sd(double * p)
void_mm_store_sd(double * p, __m128d a)
__m128d _mm_move_sd(__m128d a, __m128d b)
MOVSHDUP
__m128 _mm_movehdup_ps(__m128 a)
MOVSLDUP
__m128 _mm_moveldup_ps(__m128 a)
MOVSS
__m128 _mm_load_ss(float * p)
C-6
Vol. 2D
INTEL® C/C++ COMPILER INTRINSICS AND FUNCTIONAL EQUIVALENTS
Table C-1. Simple Intrinsics (Contd.)
Mnemonic
Intrinsic
void_mm_store_ss(float * p, __m128 a)
__m128 _mm_move_ss(__m128 a, __m128 b)
MOVUPD
__m128d _mm_loadu_pd(double * p)
void_mm_storeu_pd(double *p, __m128d a)
MOVUPS
__m128 _mm_loadu_ps(float * p)
void_mm_storeu_ps(float *p, __m128 a)
MPSADBW
__m128i _mm_mpsadbw_epu8(__m128i s1, __m128i s2, const int mask)
MULPD
__m128d _mm_mul_pd(__m128d a, __m128d b)
MULPS
__m128 _mm_mul_ss(__m128 a, __m128 b)
MULSD
__m128d _mm_mul_sd(__m128d a, __m128d b)
MULSS
__m128 _mm_mul_ss(__m128 a, __m128 b)
MWAIT
void _mm_mwait(unsigned extensions, unsigned hints)
ORPD
__m128d _mm_or_pd(__m128d a, __m128d b)
ORPS
__m128 _mm_or_ps(__m128 a, __m128 b)
PABSB
__m64 _mm_abs_pi8 (__m64 a)
__m128i _mm_abs_epi8 (__m128i a)
PABSD
__m64 _mm_abs_pi32 (__m64 a)
__m128i _mm_abs_epi32 (__m128i a)
PABSW
__m64 _mm_abs_pi16 (__m64 a)
__m128i _mm_abs_epi16 (__m128i a)
PACKSSWB
__m128i _mm_packs_epi16(__m128i m1, __m128i m2)
PACKSSWB
__m64 _mm_packs_pi16(__m64 m1, __m64 m2)
PACKSSDW
__m128i _mm_packs_epi32 (__m128i m1, __m128i m2)
PACKSSDW
__m64 _mm_packs_pi32 (__m64 m1, __m64 m2)
PACKUSDW
__m128i _mm_packus_epi32(__m128i m1, __m128i m2)
PACKUSWB
__m128i _mm_packus_epi16(__m128i m1, __m128i m2)
PACKUSWB
__m64 _mm_packs_pu16(__m64 m1, __m64 m2)
PADDB
__m128i _mm_add_epi8(__m128i m1, __m128i m2)
PADDB
__m64 _mm_add_pi8(__m64 m1, __m64 m2)
PADDW
__m128i _mm_add_epi16(__m128i m1, __m128i m2)
PADDW
__m64 _mm_add_pi16(__m64 m1, __m64 m2)
PADDD
__m128i _mm_add_epi32(__m128i m1, __m128i m2)
PADDD
__m64 _mm_add_pi32(__m64 m1, __m64 m2)
PADDQ
__m128i _mm_add_epi64(__m128i m1, __m128i m2)
PADDQ
__m64 _mm_add_si64(__m64 m1, __m64 m2)
PADDSB
__m128i _mm_adds_epi8(__m128i m1, __m128i m2)
PADDSB
__m64 _mm_adds_pi8(__m64 m1, __m64 m2)
PADDSW
__m128i _mm_adds_epi16(__m128i m1, __m128i m2)
PADDSW
__m64 _mm_adds_pi16(__m64 m1, __m64 m2)
PADDUSB
__m128i _mm_adds_epu8(__m128i m1, __m128i m2)
PADDUSB
__m64 _mm_adds_pu8(__m64 m1, __m64 m2)
Vol. 2D C-7
INTEL® C/C++ COMPILER INTRINSICS AND FUNCTIONAL EQUIVALENTS
Table C-1. Simple Intrinsics (Contd.)
Mnemonic
Intrinsic
PADDUSW
__m128i _mm_adds_epu16(__m128i m1, __m128i m2)
PADDUSW
__m64 _mm_adds_pu16(__m64 m1, __m64 m2)
PALIGNR
__m64 _mm_alignr_pi8 (__m64 a, __m64 b, int n)
__m128i _mm_alignr_epi8 (__m128i a, __m128i b, int n)
PAND
__m128i _mm_and_si128(__m128i m1, __m128i m2)
PAND
__m64 _mm_and_si64(__m64 m1, __m64 m2)
PANDN
__m128i _mm_andnot_si128(__m128i m1, __m128i m2)
PANDN
__m64 _mm_andnot_si64(__m64 m1, __m64 m2)
PAUSE
void _mm_pause(void)
PAVGB
__m128i _mm_avg_epu8(__m128i a, __m128i b)
PAVGB
__m64 _mm_avg_pu8(__m64 a, __m64 b)
PAVGW
__m128i _mm_avg_epu16(__m128i a, __m128i b)
PAVGW
__m64 _mm_avg_pu16(__m64 a, __m64 b)
PBLENDVB
__m128i _mm_blendv_epi (__m128i v1, __m128i v2, __m128i mask)
PBLENDW
__m128i _mm_blend_epi16(__m128i v1, __m128i v2, const int mask)
PCLMULQDQ
__m128i _mm_clmulepi64_si128 (__m128i, __m128i, const int)
PCMPEQB
__m128i _mm_cmpeq_epi8(__m128i m1, __m128i m2)
PCMPEQB
__m64 _mm_cmpeq_pi8(__m64 m1, __m64 m2)
PCMPEQQ
__m128i _mm_cmpeq_epi64(__m128i a, __m128i b)
PCMPEQW
__m128i _mm_cmpeq_epi16 (__m128i m1, __m128i m2)
PCMPEQW
__m64 _mm_cmpeq_pi16 (__m64 m1, __m64 m2)
PCMPEQD
__m128i _mm_cmpeq_epi32(__m128i m1, __m128i m2)
PCMPEQD
__m64 _mm_cmpeq_pi32(__m64 m1, __m64 m2)
PCMPESTRI
int _mm_cmpestri (__m128i a, int la, __m128i b, int lb, const int mode)
int _mm_cmpestra (__m128i a, int la, __m128i b, int lb, const int mode)
int _mm_cmpestrc (__m128i a, int la, __m128i b, int lb, const int mode)
int _mm_cmpestro (__m128i a, int la, __m128i b, int lb, const int mode)
int _mm_cmpestrs (__m128i a, int la, __m128i b, int lb, const int mode)
int _mm_cmpestrz (__m128i a, int la, __m128i b, int lb, const int mode)
PCMPESTRM
__m128i _mm_cmpestrm (__m128i a, int la, __m128i b, int lb, const int mode)
int _mm_cmpestra (__m128i a, int la, __m128i b, int lb, const int mode)
int _mm_cmpestrc (__m128i a, int la, __m128i b, int lb, const int mode)
int _mm_cmpestro (__m128i a, int la, __m128i b, int lb, const int mode)
int _mm_cmpestrs (__m128i a, int la, __m128i b, int lb, const int mode)
int _mm_cmpestrz (__m128i a, int la, __m128i b, int lb, const int mode)
PCMPGTB
__m128i _mm_cmpgt_epi8 (__m128i m1, __m128i m2)
PCMPGTB
__m64 _mm_cmpgt_pi8 (__m64 m1, __m64 m2)
PCMPGTW
__m128i _mm_cmpgt_epi16(__m128i m1, __m128i m2)
PCMPGTW
__m64 _mm_cmpgt_pi16 (__m64 m1, __m64 m2)
PCMPGTD
__m128i _mm_cmpgt_epi32(__m128i m1, __m128i m2)
PCMPGTD
__m64 _mm_cmpgt_pi32(__m64 m1, __m64 m2)
C-8
Vol. 2D
INTEL® C/C++ COMPILER INTRINSICS AND FUNCTIONAL EQUIVALENTS
Table C-1. Simple Intrinsics (Contd.)
Mnemonic
Intrinsic
PCMPISTRI
__m128i _mm_cmpestrm (__m128i a, int la, __m128i b, int lb, const int mode)
int _mm_cmpestra (__m128i a, int la, __m128i b, int lb, const int mode)
int _mm_cmpestrc (__m128i a, int la, __m128i b, int lb, const int mode)
int _mm_cmpestro (__m128i a, int la, __m128i b, int lb, const int mode)
int _mm_cmpestrs (__m128i a, int la, __m128i b, int lb, const int mode)
int _mm_cmpistrz (__m128i a, __m128i b, const int mode)
PCMPISTRM
__m128i _mm_cmpistrm (__m128i a, __m128i b, const int mode)
int _mm_cmpistra (__m128i a, __m128i b, const int mode)
int _mm_cmpistrc (__m128i a, __m128i b, const int mode)
int _mm_cmpistro (__m128i a, __m128i b, const int mode)
int _mm_cmpistrs (__m128i a, __m128i b, const int mode)
int _mm_cmpistrz (__m128i a, __m128i b, const int mode)
PCMPGTQ
__m128i _mm_cmpgt_epi64(__m128i a, __m128i b)
PEXTRB
int _mm_extract_epi8 (__m128i src, const int ndx)
PEXTRD
int _mm_extract_epi32 (__m128i src, const int ndx)
PEXTRQ
__int64 _mm_extract_epi64 (__m128i src, const int ndx)
PEXTRW
int _mm_extract_epi16(__m128i a, int n)
PEXTRW
int _mm_extract_pi16(__m64 a, int n)
int _mm_extract_epi16 (__m128i src, int ndx)
PHADDD
__m64 _mm_hadd_pi32 (__m64 a, __m64 b)
__m128i _mm_hadd_epi32 (__m128i a, __m128i b)
PHADDSW
__m64 _mm_hadds_pi16 (__m64 a, __m64 b)
__m128i _mm_hadds_epi16 (__m128i a, __m128i b)
PHADDW
__m64 _mm_hadd_pi16 (__m64 a, __m64 b)
__m128i _mm_hadd_epi16 (__m128i a, __m128i b)
PHMINPOSUW
__m128i _mm_minpos_epu16( __m128i packed_words)
PHSUBD
__m64 _mm_hsub_pi32 (__m64 a, __m64 b)
__m128i _mm_hsub_epi32 (__m128i a, __m128i b)
PHSUBSW
__m64 _mm_hsubs_pi16 (__m64 a, __m64 b)
__m128i _mm_hsubs_epi16 (__m128i a, __m128i b)
PHSUBW
__m64 _mm_hsub_pi16 (__m64 a, __m64 b)
__m128i _mm_hsub_epi16 (__m128i a, __m128i b)
PINSRB
__m128i _mm_insert_epi8(__m128i s1, int s2, const int ndx)
PINSRD
__m128i _mm_insert_epi32(__m128i s2, int s, const int ndx)
PINSRQ
__m128i _mm_insert_epi64(__m128i s2, __int64 s, const int ndx)
PINSRW
__m128i _mm_insert_epi16(__m128i a, int d, int n)
PINSRW
__m64 _mm_insert_pi16(__m64 a, int d, int n)
PMADDUBSW
__m64 _mm_maddubs_pi16 (__m64 a, __m64 b)
__m128i _mm_maddubs_epi16 (__m128i a, __m128i b)
PMADDWD
__m128i _mm_madd_epi16(__m128i m1 __m128i m2)
PMADDWD
__m64 _mm_madd_pi16(__m64 m1, __m64 m2)
Vol. 2D C-9
INTEL® C/C++ COMPILER INTRINSICS AND FUNCTIONAL EQUIVALENTS
Table C-1. Simple Intrinsics (Contd.)
Mnemonic
Intrinsic
PMAXSB
__m128i _mm_max_epi8( __m128i a, __m128i b)
PMAXSD
__m128i _mm_max_epi32( __m128i a, __m128i b)
PMAXSW
__m128i _mm_max_epi16(__m128i a, __m128i b)
PMAXSW
__m64 _mm_max_pi16(__m64 a, __m64 b)
PMAXUB
__m128i _mm_max_epu8(__m128i a, __m128i b)
PMAXUB
__m64 _mm_max_pu8(__m64 a, __m64 b)
PMAXUD
__m128i _mm_max_epu32( __m128i a, __m128i b)
PMAXUW
__m128i _mm_max_epu16( __m128i a, __m128i b)
PMINSB
_m128i _mm_min_epi8( __m128i a, __m128i b)
PMINSD
__m128i _mm_min_epi32( __m128i a, __m128i b)
PMINSW
__m128i _mm_min_epi16(__m128i a, __m128i b)
PMINSW
__m64 _mm_min_pi16(__m64 a, __m64 b)
PMINUB
__m128i _mm_min_epu8(__m128i a, __m128i b)
PMINUB
__m64 _mm_min_pu8(__m64 a, __m64 b)
PMINUD
__m128i _mm_min_epu32 ( __m128i a, __m128i b)
PMINUW
__m128i _mm_min_epu16 ( __m128i a, __m128i b)
PMOVMSKB
int _mm_movemask_epi8(__m128i a)
PMOVMSKB
int _mm_movemask_pi8(__m64 a)
PMOVSXBW
__m128i _mm_ cvtepi8_epi16( __m128i a)
PMOVSXBD
__m128i _mm_ cvtepi8_epi32( __m128i a)
PMOVSXBQ
__m128i _mm_ cvtepi8_epi64( __m128i a)
PMOVSXWD
__m128i _mm_ cvtepi16_epi32( __m128i a)
PMOVSXWQ
__m128i _mm_ cvtepi16_epi64( __m128i a)
PMOVSXDQ
__m128i _mm_ cvtepi32_epi64( __m128i a)
PMOVZXBW
__m128i _mm_ cvtepu8_epi16( __m128i a)
PMOVZXBD
__m128i _mm_ cvtepu8_epi32( __m128i a)
PMOVZXBQ
__m128i _mm_ cvtepu8_epi64( __m128i a)
PMOVZXWD
__m128i _mm_ cvtepu16_epi32( __m128i a)
PMOVZXWQ
__m128i _mm_ cvtepu16_epi64( __m128i a)
PMOVZXDQ
__m128i _mm_ cvtepu32_epi64( __m128i a)
PMULDQ
__m128i _mm_mul_epi32( __m128i a, __m128i b)
PMULHRSW
__m64 _mm_mulhrs_pi16 (__m64 a, __m64 b)
__m128i _mm_mulhrs_epi16 (__m128i a, __m128i b)
PMULHUW
__m128i _mm_mulhi_epu16(__m128i a, __m128i b)
PMULHUW
__m64 _mm_mulhi_pu16(__m64 a, __m64 b)
PMULHW
__m128i _mm_mulhi_epi16(__m128i m1, __m128i m2)
PMULHW
__m64 _mm_mulhi_pi16(__m64 m1, __m64 m2)
PMULLUD
__m128i _mm_mullo_epi32(__m128i a, __m128i b)
PMULLW
__m128i _mm_mullo_epi16(__m128i m1, __m128i m2)
PMULLW
__m64 _mm_mullo_pi16(__m64 m1, __m64 m2)
C-10
Vol. 2D
INTEL® C/C++ COMPILER INTRINSICS AND FUNCTIONAL EQUIVALENTS
Table C-1. Simple Intrinsics (Contd.)
Mnemonic
Intrinsic
PMULUDQ
__m64 _mm_mul_su32(__m64 m1, __m64 m2)
__m128i _mm_mul_epu32(__m128i m1, __m128i m2)
POPCNT
int _mm_popcnt_u32(unsigned int a)
int64_t _mm_popcnt_u64(unsigned __int64 a)
POR
__m64 _mm_or_si64(__m64 m1, __m64 m2)
POR
__m128i _mm_or_si128(__m128i m1, __m128i m2)
PREFETCHh
void _mm_prefetch(char *a, int sel)
PSADBW
__m128i _mm_sad_epu8(__m128i a, __m128i b)
PSADBW
__m64 _mm_sad_pu8(__m64 a, __m64 b)
PSHUFB
__m64 _mm_shuffle_pi8 (__m64 a, __m64 b)
__m128i _mm_shuffle_epi8 (__m128i a, __m128i b)
PSHUFD
__m128i _mm_shuffle_epi32(__m128i a, int n)
PSHUFHW
__m128i _mm_shufflehi_epi16(__m128i a, int n)
PSHUFLW
__m128i _mm_shufflelo_epi16(__m128i a, int n)
PSHUFW
__m64 _mm_shuffle_pi16(__m64 a, int n)
PSIGNB
__m64 _mm_sign_pi8 (__m64 a, __m64 b)
__m128i _mm_sign_epi8 (__m128i a, __m128i b)
PSIGND
__m64 _mm_sign_pi32 (__m64 a, __m64 b)
__m128i _mm_sign_epi32 (__m128i a, __m128i b)
PSIGNW
__m64 _mm_sign_pi16 (__m64 a, __m64 b)
__m128i _mm_sign_epi16 (__m128i a, __m128i b)
PSLLW
__m128i _mm_sll_epi16(__m128i m, __m128i count)
PSLLW
__m128i _mm_slli_epi16(__m128i m, int count)
PSLLW
__m64 _mm_sll_pi16(__m64 m, __m64 count)
__m64 _mm_slli_pi16(__m64 m, int count)
PSLLD
__m128i _mm_slli_epi32(__m128i m, int count)
__m128i _mm_sll_epi32(__m128i m, __m128i count)
PSLLD
__m64 _mm_slli_pi32(__m64 m, int count)
__m64 _mm_sll_pi32(__m64 m, __m64 count)
PSLLQ
__m64 _mm_sll_si64(__m64 m, __m64 count)
__m64 _mm_slli_si64(__m64 m, int count)
PSLLQ
__m128i _mm_sll_epi64(__m128i m, __m128i count)
__m128i _mm_slli_epi64(__m128i m, int count)
PSLLDQ
__m128i _mm_slli_si128(__m128i m, int imm)
PSRAW
__m128i _mm_sra_epi16(__m128i m, __m128i count)
__m128i _mm_srai_epi16(__m128i m, int count)
PSRAW
__m64 _mm_sra_pi16(__m64 m, __m64 count)
__m64 _mm_srai_pi16(__m64 m, int count)
PSRAD
__m128i _mm_sra_epi32 (__m128i m, __m128i count)
__m128i _mm_srai_epi32 (__m128i m, int count)
PSRAD
__m64 _mm_sra_pi32 (__m64 m, __m64 count)
Vol. 2D C-11
INTEL® C/C++ COMPILER INTRINSICS AND FUNCTIONAL EQUIVALENTS
Table C-1. Simple Intrinsics (Contd.)
Mnemonic
Intrinsic
__m64 _mm_srai_pi32 (__m64 m, int count)
PSRLW
_m128i _mm_srl_epi16 (__m128i m, __m128i count)
__m128i _mm_srli_epi16 (__m128i m, int count)
__m64 _mm_srl_pi16 (__m64 m, __m64 count)
__m64 _mm_srli_pi16(__m64 m, int count)
PSRLD
__m128i _mm_srl_epi32 (__m128i m, __m128i count)
__m128i _mm_srli_epi32 (__m128i m, int count)
PSRLD
__m64 _mm_srl_pi32 (__m64 m, __m64 count)
__m64 _mm_srli_pi32 (__m64 m, int count)
PSRLQ
__m128i _mm_srl_epi64 (__m128i m, __m128i count)
__m128i _mm_srli_epi64 (__m128i m, int count)
PSRLQ
__m64 _mm_srl_si64 (__m64 m, __m64 count)
__m64 _mm_srli_si64 (__m64 m, int count)
PSRLDQ
__m128i _mm_srli_si128(__m128i m, int imm)
PSUBB
__m128i _mm_sub_epi8(__m128i m1, __m128i m2)
PSUBB
__m64 _mm_sub_pi8(__m64 m1, __m64 m2)
PSUBW
__m128i _mm_sub_epi16(__m128i m1, __m128i m2)
PSUBW
__m64 _mm_sub_pi16(__m64 m1, __m64 m2)
PSUBD
__m128i _mm_sub_epi32(__m128i m1, __m128i m2)
PSUBD
__m64 _mm_sub_pi32(__m64 m1, __m64 m2)
PSUBQ
__m128i _mm_sub_epi64(__m128i m1, __m128i m2)
PSUBQ
__m64 _mm_sub_si64(__m64 m1, __m64 m2)
PSUBSB
__m128i _mm_subs_epi8(__m128i m1, __m128i m2)
PSUBSB
__m64 _mm_subs_pi8(__m64 m1, __m64 m2)
PSUBSW
__m128i _mm_subs_epi16(__m128i m1, __m128i m2)
PSUBSW
__m64 _mm_subs_pi16(__m64 m1, __m64 m2)
PSUBUSB
__m128i _mm_subs_epu8(__m128i m1, __m128i m2)
PSUBUSB
__m64 _mm_subs_pu8(__m64 m1, __m64 m2)
PSUBUSW
__m128i _mm_subs_epu16(__m128i m1, __m128i m2)
PSUBUSW
__m64 _mm_subs_pu16(__m64 m1, __m64 m2)
PTEST
int _mm_testz_si128(__m128i s1, __m128i s2)
int _mm_testc_si128(__m128i s1, __m128i s2)
int _mm_testnzc_si128(__m128i s1, __m128i s2)
PUNPCKHBW
__m64 _mm_unpackhi_pi8(__m64 m1, __m64 m2)
PUNPCKHBW
__m128i _mm_unpackhi_epi8(__m128i m1, __m128i m2)
PUNPCKHWD
__m64 _mm_unpackhi_pi16(__m64 m1,__m64 m2)
PUNPCKHWD
__m128i _mm_unpackhi_epi16(__m128i m1, __m128i m2)
PUNPCKHDQ
___m64 _mm_unpackhi_pi32(__m64 m1, __m64 m2)
PUNPCKHDQ
__m128i _mm_unpackhi_epi32(__m128i m1, __m128i m2)
PUNPCKHQDQ
__m128i _mm_unpackhi_epi64(__m128i m1, __m128i m2)
PUNPCKLBW
__m64 _mm_unpacklo_pi8 (__m64 m1, __m64 m2)
C-12
Vol. 2D
INTEL® C/C++ COMPILER INTRINSICS AND FUNCTIONAL EQUIVALENTS
Table C-1. Simple Intrinsics (Contd.)
Mnemonic
Intrinsic
PUNPCKLBW
__m128i _mm_unpacklo_epi8 (__m128i m1, __m128i m2)
PUNPCKLWD
__m64 _mm_unpacklo_pi16(__m64 m1, __m64 m2)
PUNPCKLWD
__m128i _mm_unpacklo_epi16(__m128i m1, __m128i m2)
PUNPCKLDQ
__m64 _mm_unpacklo_pi32(__m64 m1, __m64 m2)
PUNPCKLDQ
__m128i _mm_unpacklo_epi32(__m128i m1, __m128i m2)
PUNPCKLQDQ
__m128i _mm_unpacklo_epi64(__m128i m1, __m128i m2)
PXOR
__m64 _mm_xor_si64(__m64 m1, __m64 m2)
PXOR
__m128i _mm_xor_si128(__m128i m1, __m128i m2)
RCPPS
__m128 _mm_rcp_ps(__m128 a)
RCPSS
__m128 _mm_rcp_ss(__m128 a)
ROUNDPD
__m128 mm_round_pd(__m128d s1, int iRoundMode)
__m128 mm_floor_pd(__m128d s1)
__m128 mm_ceil_pd(__m128d s1)
ROUNDPS
__m128 mm_round_ps(__m128 s1, int iRoundMode)
__m128 mm_floor_ps(__m128 s1)
__m128 mm_ceil_ps(__m128 s1)
ROUNDSD
__m128d mm_round_sd(__m128d dst, __m128d s1, int iRoundMode)
__m128d mm_floor_sd(__m128d dst, __m128d s1)
__m128d mm_ceil_sd(__m128d dst, __m128d s1)
ROUNDSS
__m128 mm_round_ss(__m128 dst, __m128 s1, int iRoundMode)
__m128 mm_floor_ss(__m128 dst, __m128 s1)
__m128 mm_ceil_ss(__m128 dst, __m128 s1)
RSQRTPS
__m128 _mm_rsqrt_ps(__m128 a)
RSQRTSS
__m128 _mm_rsqrt_ss(__m128 a)
SFENCE
void_mm_sfence(void)
SHUFPD
__m128d _mm_shuffle_pd(__m128d a, __m128d b, unsigned int imm8)
SHUFPS
__m128 _mm_shuffle_ps(__m128 a, __m128 b, unsigned int imm8)
SQRTPD
__m128d _mm_sqrt_pd(__m128d a)
SQRTPS
__m128 _mm_sqrt_ps(__m128 a)
SQRTSD
__m128d _mm_sqrt_sd(__m128d a)
SQRTSS
__m128 _mm_sqrt_ss(__m128 a)
STMXCSR
_mm_getcsr(void)
SUBPD
__m128d _mm_sub_pd(__m128d a, __m128d b)
SUBPS
__m128 _mm_sub_ps(__m128 a, __m128 b)
SUBSD
__m128d _mm_sub_sd(__m128d a, __m128d b)
SUBSS
__m128 _mm_sub_ss(__m128 a, __m128 b)
UCOMISD
int _mm_ucomieq_sd(__m128d a, __m128d b)
int _mm_ucomilt_sd(__m128d a, __m128d b)
int _mm_ucomile_sd(__m128d a, __m128d b)
int _mm_ucomigt_sd(__m128d a, __m128d b)
int _mm_ucomige_sd(__m128d a, __m128d b)
Vol. 2D C-13
INTEL® C/C++ COMPILER INTRINSICS AND FUNCTIONAL EQUIVALENTS
Table C-1. Simple Intrinsics (Contd.)
Mnemonic
Intrinsic
int _mm_ucomineq_sd(__m128d a, __m128d b)
UCOMISS
int _mm_ucomieq_ss(__m128 a, __m128 b)
int _mm_ucomilt_ss(__m128 a, __m128 b)
int _mm_ucomile_ss(__m128 a, __m128 b)
int _mm_ucomigt_ss(__m128 a, __m128 b)
int _mm_ucomige_ss(__m128 a, __m128 b)
int _mm_ucomineq_ss(__m128 a, __m128 b)
UNPCKHPD
__m128d _mm_unpackhi_pd(__m128d a, __m128d b)
UNPCKHPS
__m128 _mm_unpackhi_ps(__m128 a, __m128 b)
UNPCKLPD
__m128d _mm_unpacklo_pd(__m128d a, __m128d b)
UNPCKLPS
__m128 _mm_unpacklo_ps(__m128 a, __m128 b)
XORPD
__m128d _mm_xor_pd(__m128d a, __m128d b)
XORPS
__m128 _mm_xor_ps(__m128 a, __m128 b)
C.2
COMPOSITE INTRINSICS
Table C-2. Composite Intrinsics
Mnemonic
Intrinsic
(composite)
__m128i _mm_set_epi64(__m64 q1, __m64 q0)
(composite)
__m128i _mm_set_epi32(int i3, int i2, int i1, int i0)
(composite)
__m128i _mm_set_epi16(short w7,short w6, short w5, short w4, short w3, short w2,
short w1,short w0)
(composite)
__m128i _mm_set_epi8(char w15,char w14, char w13, char w12, char w11, char w10,
char w9, char w8, char w7,char w6, char w5, char w4, char w3, char w2,char w1, char w0)
(composite)
__m128i _mm_set1_epi64(__m64 q)
(composite)
__m128i _mm_set1_epi32(int a)
(composite)
__m128i _mm_set1_epi16(short a)
(composite)
__m128i _mm_set1_epi8(char a)
(composite)
__m128i _mm_setr_epi64(__m64 q1, __m64 q0)
(composite)
__m128i _mm_setr_epi32(int i3, int i2, int i1, int i0)
(composite)
__m128i _mm_setr_epi16(short w7,short w6, short w5, short w4, short w3, short w2, short w,
short w0)
(composite)
__m128i _mm_setr_epi8(char w15,char w14, char w13, char w12, char w11, char w10,
char w9, char w8,char w7, char w6,char w5, char w4, char w3, char w2,char w1,char w0)
(composite)
__m128i _mm_setzero_si128()
(composite)
__m128 _mm_set_ps1(float w)
__m128 _mm_set1_ps(float w)
(composite)
__m128cmm_set1_pd(double w)
(composite)
__m128d _mm_set_sd(double w)
(composite)
__m128d _mm_set_pd(double z, double y)
(composite)
__m128 _mm_set_ps(float z, float y, float x, float w)
(composite)
__m128d _mm_setr_pd(double z, double y)
(composite)
__m128 _mm_setr_ps(float z, float y, float x, float w)
C-14
Vol. 2D
INTEL® C/C++ COMPILER INTRINSICS AND FUNCTIONAL EQUIVALENTS
Table C-2. Composite Intrinsics (Contd.)
Mnemonic
Intrinsic
(composite)
__m128d _mm_setzero_pd(void)
(composite)
__m128 _mm_setzero_ps(void)
MOVSD + shuffle
__m128d _mm_load_pd(double * p)
__m128d _mm_load1_pd(double *p)
MOVSS + shuffle
__m128 _mm_load_ps1(float * p)
__m128 _mm_load1_ps(float *p)
MOVAPD + shuffle
__m128d _mm_loadr_pd(double * p)
MOVAPS + shuffle
__m128 _mm_loadr_ps(float * p)
MOVSD + shuffle
void _mm_store1_pd(double *p, __m128d a)
MOVSS + shuffle
void _mm_store_ps1(float * p, __m128 a)
void _mm_store1_ps(float *p, __m128 a)
MOVAPD + shuffle
_mm_storer_pd(double * p, __m128d a)
MOVAPS + shuffle
_mm_storer_ps(float * p, __m128 a)
Vol. 2D C-15
INTEL® C/C++ COMPILER INTRINSICS AND FUNCTIONAL EQUIVALENTS
C-16
Vol. 2D
Intel® 64 and IA-32 Architectures
Software Developer’s Manual
Volume 3 (3A, 3B, 3C, & 3D):
System Programming Guide
NOTE: The Intel 64 and IA-32 Architectures Software Developer's Manual consists of four volumes:
Basic Architecture, Order Number 253665; Instruction Set Reference A-Z, Order Number 325383;
System Programming Guide, Order Number 325384; Model-Specific Registers, Order Number 335592.
Refer to all four volumes when evaluating your design needs.
Order Number: 325384-092US
June 2026
Notices & Disclaimers
Intel technologies may require enabled hardware, software or service activation.
No product or component can be absolutely secure.
Your costs and results may vary.
You may not use or facilitate the use of this document in connection with any infringement or other legal analysis concerning
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drafted which includes subject matter disclosed herein.
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available. These are not “commercial” names and not intended to function as trademarks.
No license (express or implied, by estoppel or otherwise) to any intellectual property rights is granted by this document, with
the sole exception that a) you may publish an unmodified copy and b) code, identified as Sample Code in this document is
licensed subject to the Zero-Clause BSD open source license (0BSD), https://opensource.org/licenses/0BSD. You may create
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© Intel Corporation. Intel, the Intel logo, and other Intel marks are trademarks of Intel Corporation or its subsidiaries. Other
names and brands may be claimed as the property of others.
CONTENTS
PAGE
CHAPTER 1
ABOUT THIS MANUAL
1.1
OVERVIEW OF THE SYSTEM PROGRAMMING GUIDE
1-1
CHAPTER 2
SYSTEM ARCHITECTURE OVERVIEW
2.1
OVERVIEW OF THE SYSTEM-LEVEL ARCHITECTURE
2-1
2.1.1
Global and Local Descriptor Tables
2-3
2.1.1.1
Global and Local Descriptor Tables in IA-32e Mode
2-4
2.1.2
System Segments, Segment Descriptors, and Gates
2-4
2.1.2.1
Gates in IA-32e Mode
2-4
2.1.3
Task-State Segments and Task Gates
2-5
2.1.3.1
Task-State Segments in IA-32e Mode
2-5
2.1.4
Interrupt and Exception Handling
2-5
2.1.4.1
Interrupt and Exception Handling IA-32e Mode
2-6
2.1.5
Memory Management
2-6
2.1.5.1
Memory Management in IA-32e Mode
2-6
2.1.6
System Registers
2-6
2.1.6.1
System Registers in IA-32e Mode
2-7
2.1.7
Other System Resources
2-7
2.2
MODES OF OPERATION
2-7
2.2.1
Extended Feature Enable Register
2-9
2.3
SYSTEM FLAGS AND FIELDS IN THE EFLAGS REGISTER
2-9
2.3.1
System Flags and Fields in IA-32e Mode
2-11
2.4
MEMORY-MANAGEMENT REGISTERS
2-11
2.4.1
Global Descriptor Table Register (GDTR)
2-12
2.4.2
Local Descriptor Table Register (LDTR)
2-12
2.4.3
IDTR Interrupt Descriptor Table Register
2-12
2.4.4
Task Register (TR)
2-13
2.5
CONTROL REGISTERS
2-13
2.5.1
CPUID Qualification of Control Register Flags
2-21
2.6
EXTENDED CONTROL REGISTERS (INCLUDING XCR0)
2-21
2.7
PROTECTION-KEY RIGHTS REGISTERS (PKRU AND IA32_PKRS)
2-23
2.8
SYSTEM INSTRUCTION SUMMARY
2-24
2.8.1
Loading and Storing System Registers
2-25
2.8.2
Modifying Kernel GS
2-26
2.8.3
Reading and Writing Protection Key Rights for User Pages
2-26
2.8.4
Verifying of Access Privileges
2-26
2.8.5
Loading and Storing Debug Registers
2-27
2.8.6
Invalidating Caches and TLBs
2-27
2.8.7
Controlling the Processor
2-28
2.8.8
Reading Performance-Monitoring Counters
2-28
2.8.9
Reading Time-Stamp Counter and IA32_TSC_AUX
2-29
2.8.10
Reading and Writing Model-Specific Registers
2-29
2.8.11
Enabling Processor Extended States
2-29
CHAPTER 3
PROTECTED-MODE MEMORY MANAGEMENT
3.1
MEMORY MANAGEMENT OVERVIEW
3-1
3.2
USING SEGMENTS
3-2
3.2.1
Basic Flat Model
3-3
3.2.2
Protected Flat Model
3-3
3.2.3
Multi-Segment Model
3-4
3.2.4
Segmentation in IA-32e Mode
3-5
3.2.5
Paging and Segmentation
3-5
Vol. 3A iii
CONTENTS
PAGE
3.3
PHYSICAL ADDRESS SPACE
3-6
3.3.1
Intel® 64 Processors and Physical Address Space
3-6
3.4
LOGICAL AND LINEAR ADDRESSES
3-6
3.4.1
Logical Address Translation in IA-32e Mode
3-7
3.4.2
Segment Selectors
3-7
3.4.3
Segment Registers
3-8
3.4.4
Segment Loading Instructions in IA-32e Mode
3-9
3.4.5
Segment Descriptors
3-9
3.4.5.1
Code- and Data-Segment Descriptor Types
3-12
3.5
SYSTEM DESCRIPTOR TYPES
3-13
3.5.1
Segment Descriptor Tables
3-14
3.5.2
Segment Descriptor Tables in IA-32e Mode
3-16
CHAPTER 4
LINEAR-ADDRESS PRE-PROCESSING
4.1
ENABLING AND ENUMERATION
4-1
4.2
MODE-BASED ACCESSES AND LINEAR-ADDRESS-SPACE PARTITIONING
4-1
4.3
LINEAR-ADDRESS-SPACE SEPARATION (LASS)
4-2
4.3.1
Enumeration and Enabling
4-2
4.3.2
Operation of Linear-Address-Space Separation (LASS)
4-2
4.4
LINEAR-ADDRESS MASKING
4-3
4.4.1
Enumeration, Enabling, and Configuration
4-3
4.4.2
Treatment of Data Accesses with LAM Active
4-4
4.4.3
Paging Interactions
4-4
4.5
CANONICALITY CHECKING
4-4
4.5.1
Memory Accesses
4-5
4.5.2
Loads of the Instruction Pointer (RIP)
4-5
4.5.3
System Registers Containing Linear Addresses
4-5
4.5.4
TLB-Invalidation Instructions
4-7
CHAPTER 5
PAGING
5.1
PAGING MODES AND CONTROL BITS
5-1
5.1.1
Four Paging Modes
5-1
5.1.2
Paging-Mode Enabling
5-3
5.1.3
Paging-Mode Modifiers
5-4
5.1.4
Enumeration of Paging Features by CPUID
5-5
5.2
HIERARCHICAL PAGING STRUCTURES: AN OVERVIEW
5-7
5.3
32-BIT PAGING
5-9
5.4
PAE PAGING
5-14
5.4.1
PDPTE Registers
5-14
5.4.2
Linear-Address Translation with PAE Paging
5-15
5.5
4-LEVEL PAGING AND 5-LEVEL PAGING
5-20
5.5.1
Ordinary Paging and HLAT Paging
5-20
5.5.2
Use of CR3 with Ordinary 4-Level Paging and 5-Level Paging
5-21
5.5.3
Use of HLATP with HLAT 4-Level Paging and 5-Level Paging
5-22
5.5.4
Linear-Address Translation with 4-Level Paging and 5-Level Paging
5-22
5.5.5
Restart of HLAT Paging
5-33
5.6
ACCESS RIGHTS
5-33
5.6.1
Determination of Access Rights
5-33
5.6.2
Protection Keys
5-36
5.7
PAGE-FAULT EXCEPTIONS
5-37
5.8
ACCESSED AND DIRTY FLAGS
5-39
5.9
PAGING AND MEMORY TYPING
5-39
5.9.1
Paging and Memory Typing When the PAT is Not Supported (Pentium Pro and Pentium II Processors)
5-40
5.9.2
Paging and Memory Typing When the PAT is Supported (Pentium III and More Recent Processor Families)
5-40
5.9.3
Caching Paging-Related Information about Memory Typing
5-41
5.10
CACHING TRANSLATION INFORMATION
5-41
5.10.1
Process-Context Identifiers (PCIDs)
5-41
5.10.2
Translation Lookaside Buffers (TLBs)
5-42
5.10.2.1
Page Numbers, Page Frames, and Page Offsets
5-42
5.10.2.2
Caching Translations in TLBs
5-43
iv Vol. 3A
CONTENTS
PAGE
5.10.2.3
Details of TLB Use
5-43
5.10.2.4
Global Pages
5-44
5.10.3
Paging-Structure Caches
5-44
5.10.3.1
Caches for Paging Structures
5-44
5.10.3.2
Using the Paging-Structure Caches to Translate Linear Addresses
5-47
5.10.3.3
Multiple Cached Entries for a Single Paging-Structure Entry
5-47
5.10.4
Invalidation of TLBs and Paging-Structure Caches
5-48
5.10.4.1
Operations that Invalidate TLBs and Paging-Structure Caches
5-48
5.10.4.2
Recommended Invalidation
5-50
5.10.4.3
Optional Invalidation
5-51
5.10.4.4
Delayed Invalidation
5-52
5.10.5
Propagation of Paging-Structure Changes to Multiple Processors
5-52
5.11
INTERACTIONS WITH VIRTUAL-MACHINE EXTENSIONS (VMX)
5-53
5.11.1
VMX Transitions
5-53
5.11.2
VMX Support for Address Translation
5-54
5.12
USING PAGING FOR VIRTUAL MEMORY
5-54
5.13
MAPPING SEGMENTS TO PAGES
5-54
CHAPTER 6
PROTECTION
6.1
ENABLING AND DISABLING SEGMENT AND PAGE PROTECTION
6-1
6.2
FIELDS AND FLAGS USED FOR SEGMENT-LEVEL AND PAGE-LEVEL PROTECTION
6-2
6.2.1
Code-Segment Descriptor in 64-bit Mode
6-3
6.3
LIMIT CHECKING
6-4
6.3.1
Limit Checking in 64-bit Mode
6-5
6.4
TYPE CHECKING
6-5
6.4.1
Null Segment Selector Checking
6-6
6.4.1.1
NULL Segment Checking in 64-bit Mode
6-6
6.5
PRIVILEGE LEVELS
6-6
6.6
PRIVILEGE LEVEL CHECKING WHEN ACCESSING DATA SEGMENTS
6-8
6.6.1
Accessing Data in Code Segments
6-9
6.7
PRIVILEGE LEVEL CHECKING WHEN LOADING THE SS REGISTER
6-10
6.8
PRIVILEGE LEVEL CHECKING WHEN TRANSFERRING PROGRAM CONTROL BETWEEN CODE SEGMENTS
6-10
6.8.1
Direct Calls or Jumps to Code Segments
6-10
6.8.1.1
Accessing Nonconforming Code Segments
6-11
6.8.1.2
Accessing Conforming Code Segments
6-12
6.8.2
Gate Descriptors
6-13
6.8.3
Call Gates
6-13
6.8.3.1
IA-32e Mode Call Gates
6-14
6.8.4
Accessing a Code Segment Through a Call Gate
6-15
6.8.5
Stack Switching
6-17
6.8.5.1
Stack Switching in 64-bit Mode
6-19
6.8.6
Returning from a Called Procedure
6-20
6.8.7
Performing Fast Calls to System Procedures with the SYSENTER and SYSEXIT Instructions
6-20
6.8.7.1
SYSENTER and SYSEXIT Instructions in IA-32e Mode
6-21
6.8.8
Fast System Calls in 64-Bit Mode
6-22
6.9
PRIVILEGED INSTRUCTIONS
6-23
6.10
POINTER VALIDATION
6-24
6.10.1
Checking Access Rights (LAR Instruction)
6-24
6.10.2
Checking Read/Write Rights (VERR and VERW Instructions)
6-25
6.10.3
Checking That the Pointer Offset Is Within Limits (LSL Instruction)
6-25
6.10.4
Checking Caller Access Privileges (ARPL Instruction)
6-26
6.10.5
Checking Alignment
6-28
6.11
PAGE-LEVEL PROTECTION
6-28
6.11.1
Page-Protection Flags
6-28
6.11.2
Restricting Addressable Domain
6-28
6.11.3
Page Type
6-29
6.11.4
Combining Protection of Both Levels of Page Tables
6-29
6.11.5
Overrides to Page Protection
6-29
6.12
COMBINING PAGE AND SEGMENT PROTECTION
6-29
6.13
PAGE-LEVEL PROTECTION AND EXECUTE-DISABLE BIT
6-30
6.13.1
Detecting and Enabling the Execute-Disable Capability
6-30
6.13.2
Execute-Disable Page Protection
6-31
6.13.3
Reserved Bit Checking
6-32
Vol. 3A v
CONTENTS
PAGE
6.13.4
Exception Handling
6-34
CHAPTER 7
INTERRUPT AND EXCEPTION HANDLING
7.1
INTERRUPT AND EXCEPTION OVERVIEW
7-1
7.2
EXCEPTION AND INTERRUPT VECTORS
7-1
7.3
SOURCES OF INTERRUPTS
7-2
7.3.1
External Interrupts
7-2
7.3.2
Maskable Hardware Interrupts
7-3
7.3.3
Software-Generated Interrupts
7-4
7.4
SOURCES OF EXCEPTIONS
7-4
7.4.1
Program-Error Exceptions
7-4
7.4.2
Software-Generated Exceptions
7-4
7.4.3
Machine-Check Exceptions
7-4
7.5
EXCEPTION CLASSIFICATIONS
7-4
7.6
PROGRAM OR TASK RESTART
7-5
7.7
NONMASKABLE INTERRUPT (NMI)
7-6
7.7.1
NMI Delivery
7-6
7.7.2
NMI Blocking
7-6
7.7.3
NMI-Source Reporting
7-7
7.8
ENABLING AND DISABLING INTERRUPTS
7-7
7.8.1
Masking Maskable Hardware Interrupts
7-7
7.8.2
Masking Instruction Breakpoints
7-8
7.8.3
Masking Exceptions and Interrupts When Switching Stacks
7-8
7.9
PRIORITIZATION OF CONCURRENT EVENTS
7-9
7.10
INTERRUPT DESCRIPTOR TABLE (IDT)
7-10
7.11
IDT DESCRIPTORS
7-11
7.12
EXCEPTION AND INTERRUPT HANDLING
7-12
7.12.1
Exception- or Interrupt-Handler Procedures
7-13
7.12.1.1
Shadow Stack Usage on Transfers to Interrupt and Exception Handling Routines
7-15
7.12.1.2
Protection of Exception- and Interrupt-Handler Procedures
7-17
7.12.1.3
Flag Usage By Exception- or Interrupt-Handler Procedure
7-18
7.12.2
Interrupt Tasks
7-18
7.13
ERROR CODE
7-19
7.14
EXCEPTION AND INTERRUPT HANDLING IN 64-BIT MODE
7-20
7.14.1
64-Bit Mode IDT
7-20
7.14.2
64-Bit Mode Stack Frame
7-21
7.14.3
IRET in IA-32e Mode
7-22
7.14.4
Stack Switching in IA-32e Mode
7-22
7.14.5
Interrupt Stack Table
7-23
7.15
EXCEPTION AND INTERRUPT REFERENCE
7-24
Event 0-Divide Error Exception (#DE)
7-25
Event 1-Debug Exception (#DB)
7-26
Event 2-NMI Interrupt
7-28
Event 3-Breakpoint Exception (#BP)
7-29
Event 4-Overflow Exception (#OF)
7-30
Event 5-BOUND Range Exceeded Exception (#BR)
7-31
Event 6-Invalid Opcode Exception (#UD)
7-32
Event 7-Device Not Available Exception (#NM)
7-34
Event 8-Double Fault Exception (#DF)
7-36
Event 9-Coprocessor Segment Overrun
7-38
Event 10-Invalid TSS Exception (#TS)
7-39
Event 11-Segment Not Present (#NP)
7-41
Event 12-Stack Fault Exception (#SS)
7-43
Event 13-General Protection Exception (#GP)
7-44
Event 14-Page-Fault Exception (#PF)
7-47
Event 16-x87 FPU Floating-Point Error (#MF)
7-51
Event 17-Alignment Check Exception (#AC)
7-53
Event 18-Machine-Check Exception (#MC)
7-55
Event 19-SIMD Floating-Point Exception (#XM)
7-56
Event 20-Virtualization Exception (#VE)
7-58
Event 21-Control Protection Exception (#CP)
7-59
vi Vol. 3A
CONTENTS
PAGE
Events 32 to 255-User Defined Interrupts
7-61
CHAPTER 8
FLEXIBLE RETURN AND EVENT DELIVERY (FRED)
8.1
OVERVIEW OF THE FRED ARCHITECTURE
8-1
8.2
ENUMERATION, ENABLING, AND CONFIGURATION
8-2
8.2.1
Enumeration
8-2
8.2.2
Enabling in CR4
8-2
8.2.3
New MSRs for Configuration of FRED Transitions
8-2
8.2.4
FRED Use of Existing MSRs
8-4
8.3
FRED EVENT DELIVERY
8-4
8.3.1
Determining and Establishing the New Context
8-4
8.3.1.1
Determining the New RIP Value
8-4
8.3.1.2
Determining the New Values for Stack Level, RSP, and SSP
8-5
8.3.1.3
Establishing the New Context
8-5
8.3.2
Saving Information About the Event and the Old Context
8-6
8.3.2.1
Saving Information on the Regular Stack
8-6
8.3.2.2
Saving Information on the Shadow Stack
8-10
8.3.3
Loading Additional State
8-11
8.3.4
Faults During FRED Event Delivery
8-11
8.3.5
Detailed Operation of FRED Event Delivery
8-11
8.4
FRED RETURN INSTRUCTIONS
8-15
8.4.1
ERETS (Event Return to Supervisor)
8-15
8.4.1.1
Loading and Checking the Return State
8-15
8.4.1.2
Checking the Shadow Stack
8-16
8.4.1.3
Establishing the Return State
8-16
8.4.2
ERETU (Event Return to User)
8-17
8.4.2.1
Loading and Checking the Return State
8-17
8.4.2.2
Checking the Shadow-Stack Pointers
8-18
8.4.2.3
Establishing the Return State
8-19
8.4.2.4
Interactions Between ERETU and Other Instructions
8-19
8.5
FRED AND EXISTING INSTRUCTIONS
8-19
8.5.1
Disallowed Instructions
8-19
8.5.2
Far CALL, IRET, Far JMP, and Far RET
8-20
8.5.3
Software Interrupts and Related Instructions
8-20
8.5.4
SYSCALL and SYSENTER
8-21
8.5.5
GETSEC and Authenticated-Code Execution Mode
8-21
8.6
LKGS: SUPPORT FOR MANAGING GS
8-22
CHAPTER 9
USER INTERRUPTS
9.1
INTRODUCTION
9-1
9.2
ENUMERATION AND ENABLING
9-1
9.3
USER-INTERRUPT STATE AND USER-INTERRUPT MSRS
9-1
9.3.1
User-Interrupt State
9-2
9.3.2
User-Interrupt MSRs
9-2
9.4
EVALUATION AND DELIVERY OF USER INTERRUPTS
9-3
9.4.1
User-Interrupt Recognition
9-3
9.4.2
User-Interrupt Delivery
9-3
9.5
USER-INTERRUPT NOTIFICATION IDENTIFICATION AND PROCESSING
9-5
9.5.1
User-Interrupt Notification Identification
9-6
9.5.2
User-Interrupt Notification Processing
9-6
9.6
USER-INTERRUPT INSTRUCTIONS
9-7
9.7
FLEXIBLE UPDATES OF UIF BY UIRET
9-7
9.8
USER IPIS
9-7
CHAPTER 10
TASK MANAGEMENT
10.1
TASK MANAGEMENT OVERVIEW
10-1
10.1.1
Task Structure
10-1
10.1.2
Task State
10-2
Vol. 3A vii
CONTENTS
PAGE
10.1.3
Executing a Task
10-2
10.2
TASK MANAGEMENT DATA STRUCTURES
10-3
10.2.1
Task-State Segment (TSS)
10-3
10.2.2
TSS Descriptor
10-5
10.2.3
TSS Descriptor in 64-bit mode
10-6
10.2.4
Task Register
10-7
10.2.5
Task-Gate Descriptor
10-8
10.3
TASK SWITCHING
10-9
10.4
TASK LINKING
10-15
10.4.1
Use of Busy Flag To Prevent Recursive Task Switching
10-16
10.4.2
Modifying Task Linkages
10-16
10.5
TASK ADDRESS SPACE
10-16
10.5.1
Mapping Tasks to the Linear and Physical Address Spaces
10-17
10.5.2
Task Logical Address Space
10-17
10.6
16-BIT TASK-STATE SEGMENT (TSS)
10-18
10.7
TASK MANAGEMENT IN 64-BIT MODE
10-19
CHAPTER 11
MULTIPLE-PROCESSOR MANAGEMENT
11.1
LOCKED ATOMIC OPERATIONS
11-1
11.1.1
Guaranteed Atomic Operations
11-2
11.1.2
Bus Locking
11-3
11.1.2.1
Automatic Locking
11-3
11.1.2.2
Software Controlled Bus Locking
11-4
11.1.2.3
Features to Disable Bus Locks
11-4
11.1.3
Handling Self- and Cross-Modifying Code
11-5
11.1.4
Effects of a LOCK Operation on Internal Processor Caches
11-6
11.2
MEMORY ORDERING
11-6
11.2.1
Memory Ordering in the Intel® Pentium® and Intel486™ Processors
11-7
11.2.2
Memory Ordering in P6 and More Recent Processor Families
11-7
11.2.3
Examples Illustrating the Memory-Ordering Principles
11-9
11.2.3.1
Assumptions, Terminology, and Notation
11-9
11.2.3.2
Neither Loads Nor Stores Are Reordered with Like Operations
11-10
11.2.3.3
Stores Are Not Reordered With Earlier Loads
11-10
11.2.3.4
Loads May Be Reordered with Earlier Stores to Different Locations
11-11
11.2.3.5
Intra-Processor Forwarding Is Allowed
11-12
11.2.3.6
Stores Are Transitively Visible
11-12
11.2.3.7
Stores Are Seen in a Consistent Order by Other Processors
11-13
11.2.3.8
Locked Instructions Have a Total Order
11-13
11.2.3.9
Loads and Stores Are Not Reordered with Locked Instructions
11-13
11.2.4
Fast-String Operation and Out-of-Order Stores
11-14
11.2.4.1
Memory-Ordering Model for String Operations on Write-Back (WB) Memory
11-14
11.2.4.2
Examples Illustrating Memory-Ordering Principles for String Operations
11-15
11.2.5
Strengthening or Weakening the Memory-Ordering Model
11-17
11.3
SERIALIZING INSTRUCTIONS
11-18
11.4
MULTIPLE-PROCESSOR (MP) INITIALIZATION
11-20
11.4.1
BSP and AP Processors
11-20
11.4.2
MP Initialization Protocol Requirements and Restrictions
11-21
11.4.3
MP Initialization Protocol Algorithm for MP Systems
11-21
11.4.4
MP Initialization Example
11-22
11.4.4.1
Typical BSP Initialization Sequence
11-22
11.4.4.2
Typical AP Initialization Sequence
11-24
11.4.5
Identifying Logical Processors in an MP System
11-25
11.5
INTEL® HYPER-THREADING TECHNOLOGY AND INTEL® MULTI-CORE TECHNOLOGY
11-26
11.6
DETECTING HARDWARE MULTI-THREADING SUPPORT AND TOPOLOGY
11-26
11.6.1
Initializing Processors Supporting Intel® Hyper-Threading Technology
11-27
11.6.2
Initializing Multi-Core Processors
11-27
11.6.3
Executing Multiple Threads on an Intel® 64 or IA-32 Processor Supporting Hardware Multi-Threading
11-28
11.6.4
Handling Interrupts on an IA-32 Processor Supporting Hardware Multi-Threading
11-28
11.7
INTEL® HYPER-THREADING TECHNOLOGY ARCHITECTURE
11-28
11.7.1
State of the Logical Processors
11-29
11.7.2
APIC Functionality
11-30
11.7.3
Memory Type Range Registers (MTRR)
11-30
11.7.4
Page Attribute Table (PAT)
11-30
viii Vol. 3A
CONTENTS
PAGE
11.7.5
Machine Check Architecture
11-30
11.7.6
Debug Registers and Extensions
11-31
11.7.7
Performance Monitoring Counters
11-31
11.7.8
IA32_MISC_ENABLE MSR
11-31
11.7.9
Memory Ordering
11-31
11.7.10
Serializing Instructions
11-31
11.7.11
Microcode Update Resources
11-31
11.7.12
Self Modifying Code
11-32
11.7.13
Implementation-Specific Intel® HT Technology Facilities
11-32
11.7.13.1
Processor Caches
11-32
11.7.13.2
Processor Translation Lookaside Buffers (TLBs)
11-32
11.7.13.3
Thermal Monitor
11-33
11.7.13.4
External Signal Compatibility
11-33
11.8
MULTI-CORE ARCHITECTURE
11-33
11.8.1
Logical Processor Support
11-34
11.8.2
Memory Type Range Registers (MTRR)
11-34
11.8.3
Performance Monitoring Counters
11-34
11.8.4
IA32_MISC_ENABLE MSR
11-34
11.8.5
Microcode Update Resources
11-34
11.9
PROGRAMMING CONSIDERATIONS FOR HARDWARE MULTI-THREADING CAPABLE PROCESSORS
11-35
11.9.1
Hierarchical Mapping of Shared Resources
11-35
11.9.2
Hierarchical Mapping of CPUID Extended Topology Leaf
11-37
11.9.3
Hierarchical ID of Logical Processors in an MP System
11-40
11.9.3.1
Hierarchical ID of Logical Processors with x2APIC ID
11-41
11.9.4
Algorithm for Three-Domain Mappings of APIC_ID
11-42
11.9.5
Identifying Topological Relationships in an MP System
11-46
11.10
MANAGEMENT OF IDLE AND BLOCKED CONDITIONS
11-49
11.10.1
HLT Instruction
11-49
11.10.2
PAUSE Instruction
11-49
11.10.3
Detecting Support MONITOR/MWAIT Instruction
11-50
11.10.4
MONITOR/MWAIT Instruction
11-50
11.10.5
Monitor/Mwait Address Range Determination
11-51
11.10.6
Required Operating System Support
11-52
11.10.6.1
Use the PAUSE Instruction in Spin-Wait Loops
11-52
11.10.6.2
Potential Usage of MONITOR/MWAIT in C0 Idle Loops
11-52
11.10.6.3
Halt Idle Logical Processors
11-54
11.10.6.4
Potential Usage of MONITOR/MWAIT in C1 Idle Loops
11-54
11.10.6.5
Guidelines for Scheduling Threads on Logical Processors Sharing Execution Resources
11-55
11.10.6.6
Eliminate Execution-Based Timing Loops
11-55
11.10.6.7
Place Locks and Semaphores in Aligned, 128-Byte Blocks of Memory
11-55
11.11
MP INITIALIZATION FOR P6 FAMILY PROCESSORS
11-55
11.11.1
Overview of the MP Initialization Process for P6 Family Processors
11-56
11.11.2
MP Initialization Protocol Algorithm
11-56
11.11.2.1
Error Detection and Handling During the MP Initialization Protocol
11-58
CHAPTER 12
PROCESSOR MANAGEMENT AND INITIALIZATION
12.1
INITIALIZATION OVERVIEW
12-1
12.1.1
Processor State After Reset
12-2
12.1.2
Processor Built-In Self-Test (BIST)
12-5
12.1.3
Model and Stepping Information
12-5
12.1.4
First Instruction Executed
12-5
12.2
X87 FPU INITIALIZATION
12-5
12.2.1
Configuring the x87 FPU Environment
12-6
12.2.2
Setting the Processor for x87 FPU Software Emulation
12-6
12.3
CACHE ENABLING
12-7
12.4
MODEL-SPECIFIC REGISTERS (MSRS)
12-7
12.5
MEMORY TYPE RANGE REGISTERS (MTRRS)
12-8
12.6
INITIALIZING SSE/SSE2/SSE3/SSSE3 EXTENSIONS
12-8
12.7
SOFTWARE INITIALIZATION FOR REAL-ADDRESS MODE OPERATION
12-8
12.7.1
Real-Address Mode IDT
12-8
12.7.2
NMI Interrupt Handling
12-9
12.8
SOFTWARE INITIALIZATION FOR PROTECTED-MODE OPERATION
12-9
12.8.1
Protected-Mode System Data Structures
12-9
Vol. 3A ix
CONTENTS
PAGE
12.8.2
Initializing Protected-Mode Exceptions and Interrupts
12-10
12.8.3
Initializing Paging
12-10
12.8.4
Initializing Multitasking
12-10
12.8.5
Initializing IA-32e Mode
12-11
12.8.5.1
IA-32e Mode System Data Structures
12-11
12.8.5.2
IA-32e Mode Interrupts and Exceptions
12-12
12.8.5.3
64-bit Mode and Compatibility Mode Operation
12-12
12.8.5.4
Switching Out of IA-32e Mode Operation
12-12
12.9
MODE SWITCHING
12-13
12.9.1
Switching to Protected Mode
12-13
12.9.2
Switching Back to Real-Address Mode
12-14
12.10
INITIALIZATION AND MODE SWITCHING EXAMPLE
12-14
12.10.1
Assembler Usage
12-16
12.10.2
STARTUP.ASM Listing
12-16
12.10.3
MAIN.ASM Source Code
12-25
12.10.4
Supporting Files
12-25
12.11
MICROCODE UPDATE FACILITIES
12-27
12.11.1
Microcode Update
12-28
12.11.2
Optional Extended Signature Table
12-31
12.11.3
Processor Identification
12-32
12.11.4
Platform Identification
12-32
12.11.5
Microcode Update Checksum
12-33
12.11.6
Microcode Update Loader
12-34
12.11.6.1
Hard Resets in Update Loading
12-35
12.11.6.2
Update in a Multiprocessor System
12-35
12.11.6.3
Update in a System Supporting Intel Hyper-Threading Technology
12-35
12.11.6.4
Update in a System Supporting Dual-Core Technology
12-35
12.11.6.5
Update Loader Enhancements
12-35
12.11.7
Update Signature and Verification
12-36
12.11.7.1
Determining the Signature
12-36
12.11.7.2
Authenticating the Update
12-37
12.11.8
Optional Processor Microcode Update Specifications
12-37
12.11.8.1
Responsibilities of the BIOS
12-38
12.11.8.2
Responsibilities of the Calling Program
12-39
12.11.8.3
Microcode Update Functions
12-42
12.11.8.4
INT 15H-based Interface
12-42
12.11.8.5
Function 00H-Presence Test
12-42
12.11.8.6
Function 01H-Write Microcode Update Data
12-43
12.11.8.7
Function 02H-Microcode Update Control
12-47
12.11.8.8
Function 03H-Read Microcode Update Data
12-48
12.11.8.9
Return Codes
12-49
CHAPTER 13
ADVANCED PROGRAMMABLE INTERRUPT CONTROLLER (APIC)
13.1
LOCAL AND I/O APIC OVERVIEW
13-1
13.2
SYSTEM BUS VS. APIC BUS
13-3
13.3
THE INTEL® 82489DX EXTERNAL APIC, THE APIC, THE XAPIC, AND THE X2APIC
13-4
13.4
LOCAL APIC
13-4
13.4.1
The Local APIC Block Diagram
13-4
13.4.2
Presence of the Local APIC
13-7
13.4.3
Enabling or Disabling the Local APIC
13-7
13.4.4
Local APIC Status and Location
13-8
13.4.5
Relocating the Local APIC Registers
13-9
13.4.6
Local APIC ID
13-9
13.4.7
Local APIC State
13-10
13.4.7.1
Local APIC State After Power-Up or Reset
13-10
13.4.7.2
Local APIC State After It Has Been Software Disabled
13-10
13.4.7.3
Local APIC State After an INIT Reset (“Wait-for-SIPI” State)
13-10
13.4.7.4
Local APIC State After It Receives an INIT-Deassert IPI
13-11
13.4.8
Local APIC Version Register
13-11
13.5
HANDLING LOCAL INTERRUPTS
13-11
13.5.1
Local Vector Table
13-12
13.5.2
Valid Interrupt Vectors
13-15
13.5.3
Error Handling
13-15
x Vol. 3A
CONTENTS
PAGE
13.5.4
APIC Timer
13-16
13.5.4.1
TSC-Deadline Mode
13-17
13.5.5
Local Interrupt Acceptance
13-19
13.6
ISSUING INTERPROCESSOR INTERRUPTS
13-19
13.6.1
Interrupt Command Register (ICR)
13-19
13.6.2
Determining IPI Destination
13-23
13.6.2.1
Physical Destination Mode
13-24
13.6.2.2
Logical Destination Mode
13-24
13.6.2.3
Broadcast/Self Delivery Mode
13-26
13.6.2.4
Lowest Priority Delivery Mode
13-26
13.6.3
IPI Delivery and Acceptance
13-27
13.7
SYSTEM AND APIC BUS ARBITRATION
13-27
13.8
HANDLING INTERRUPTS
13-27
13.8.1
Interrupt Handling with the Pentium 4 and Intel Xeon Processors
13-27
13.8.2
Interrupt Handling with the P6 Family and Pentium Processors
13-28
13.8.3
Interrupt, Task, and Processor Priority
13-29
13.8.3.1
Task and Processor Priorities
13-29
13.8.4
Interrupt Acceptance for Fixed Interrupts
13-31
13.8.5
Signaling Interrupt Servicing Completion
13-31
13.8.6
Task Priority in IA-32e Mode
13-32
13.8.6.1
Interaction of Task Priorities between CR8 and APIC
13-33
13.9
SPURIOUS INTERRUPT
13-33
13.10
APIC BUS MESSAGE PASSING MECHANISM AND PROTOCOL (P6 FAMILY, PENTIUM PROCESSORS)
13-34
13.10.1
Bus Message Formats
13-35
13.11
MESSAGE SIGNALLED INTERRUPTS
13-35
13.11.1
Message Address Register Format
13-35
13.11.2
Message Data Register Format
13-36
13.12
EXTENDED XAPIC (X2APIC)
13-37
13.12.1
Detecting and Enabling x2APIC Mode
13-38
13.12.1.1
Instructions to Access APIC Registers
13-38
13.12.1.2
x2APIC Register Address Space
13-39
13.12.1.3
Reserved Bit Checking
13-41
13.12.2
x2APIC Register Availability
13-41
13.12.3
MSR Access in x2APIC Mode
13-41
13.12.4
VM-Exit Controls for MSRs and x2APIC Registers
13-42
13.12.5
x2APIC State Transitions
13-42
13.12.5.1
x2APIC States
13-42
x2APIC After Reset
13-43
x2APIC Transitions From x2APIC Mode
13-43
x2APIC Transitions From Disabled Mode
13-44
State Changes From xAPIC Mode to x2APIC Mode
13-44
13.12.6
Routing of Device Interrupts in x2APIC Mode
13-44
13.12.7
Initialization by System Software
13-44
13.12.8
CPUID Extensions And Topology Enumeration
13-44
13.12.8.1
Consistency of APIC IDs and CPUID
13-45
13.12.9
ICR Operation in x2APIC Mode
13-45
13.12.10
Determining IPI Destination in x2APIC Mode
13-46
13.12.10.1
Logical Destination Mode in x2APIC Mode
13-46
13.12.10.2
Deriving Logical x2APIC ID from the Local x2APIC ID
13-47
13.12.11
SELF IPI Register
13-48
13.13
APIC BUS MESSAGE FORMATS
13-48
13.13.1
Bus Message Formats
13-48
13.13.2
EOI Message
13-48
13.13.2.1
Short Message
13-49
13.13.2.2
Non-focused Lowest Priority Message
13-50
13.13.2.3
APIC Bus Status Cycles
13-51
CHAPTER 14
MEMORY CACHE CONTROL
14.1
INTERNAL CACHES, TLBS, AND BUFFERS
14-1
14.2
CACHING TERMINOLOGY
14-5
14.3
METHODS OF CACHING AVAILABLE
14-6
14.3.1
Buffering of Write Combining Memory Locations
14-8
Vol. 3A xi
CONTENTS
PAGE
14.3.2
Choosing a Memory Type
14-8
14.3.3
Code Fetches in Uncacheable Memory
14-9
14.4
CACHE CONTROL PROTOCOL
14-9
14.5
CACHE CONTROL
14-10
14.5.1
Cache Control Registers and Bits
14-10
14.5.2
Precedence of Cache Controls
14-13
14.5.2.1
Selecting Memory Types for Pentium Pro and Pentium II Processors
14-14
14.5.2.2
Selecting Memory Types for Pentium III and More Recent Processor Families
14-15
14.5.2.3
Writing Values Across Pages with Different Memory Types
14-16
14.5.3
Preventing Caching
14-16
14.5.4
Disabling and Enabling the L3 Cache
14-17
14.5.5
Cache Management Instructions
14-17
14.5.6
L1 Data Cache Context Mode
14-18
14.5.6.1
Adaptive Mode
14-18
14.5.6.2
Shared Mode
14-18
14.6
SELF-MODIFYING CODE
14-18
14.7
IMPLICIT CACHING (PENTIUM 4, INTEL® XEON®, AND P6 FAMILY PROCESSORS)
14-19
14.8
EXPLICIT CACHING
14-19
14.9
INVALIDATING THE TRANSLATION LOOKASIDE BUFFERS (TLBS)
14-19
14.10
STORE BUFFER
14-20
14.11
MEMORY TYPE RANGE REGISTERS (MTRRS)
14-20
14.11.1
MTRR Feature Identification
14-21
14.11.2
Setting Memory Ranges with MTRRs
14-22
14.11.2.1
IA32_MTRR_DEF_TYPE MSR
14-22
14.11.2.2
Fixed Range MTRRs
14-23
14.11.2.3
Variable Range MTRRs
14-23
14.11.2.4
System-Management Range Register Interface
14-25
14.11.3
Example Base and Mask Calculations
14-26
14.11.3.1
Base and Mask Calculations for Greater-Than 36-bit Physical Address Support
14-27
14.11.4
Range Size and Alignment Requirement
14-28
14.11.4.1
MTRR Precedences
14-28
14.11.5
MTRR Initialization
14-29
14.11.6
Remapping Memory Types
14-29
14.11.7
MTRR Maintenance Programming Interface
14-29
14.11.7.1
MemTypeGet() Function
14-29
14.11.7.2
MemTypeSet() Function
14-31
14.11.8
MTRR Considerations in MP Systems
14-32
14.11.9
Large Page Size Considerations
14-33
14.12
PAGE ATTRIBUTE TABLE (PAT)
14-33
14.12.1
Detecting Support for the PAT Feature
14-34
14.12.2
IA32_PAT MSR
14-34
14.12.3
Selecting a Memory Type from the PAT
14-35
14.12.4
Programming the PAT
14-35
14.12.5
PAT Compatibility with Earlier IA-32 Processors
14-36
CHAPTER 15
INTEL® MMX™ TECHNOLOGY SYSTEM PROGRAMMING
15.1
EMULATION OF THE MMX INSTRUCTION SET
15-1
15.2
THE MMX STATE AND MMX REGISTER ALIASING
15-1
15.2.1
Effect of MMX, x87 FPU, FXSAVE, and FXRSTOR Instructions on the x87 FPU Tag Word
15-3
15.3
SAVING AND RESTORING THE MMX STATE AND REGISTERS
15-3
15.4
SAVING MMX STATE ON TASK OR CONTEXT SWITCHES
15-4
15.5
EXCEPTIONS THAT CAN OCCUR WHEN EXECUTING MMX INSTRUCTIONS
15-4
15.5.1
Effect of MMX Instructions on Pending x87 Floating-Point Exceptions
15-5
15.6
DEBUGGING MMX CODE
15-5
CHAPTER 16
SYSTEM PROGRAMMING FOR INSTRUCTION SET EXTENSIONS AND PROCESSOR EXTENDED
STATES
16.1
PROVIDING OPERATING SYSTEM SUPPORT FOR SSE EXTENSIONS
16-1
16.1.1
Adding Support to an Operating System for SSE Extensions
16-2
16.1.2
Checking for CPU Support
16-2
xii Vol. 3A
CONTENTS
PAGE
16.1.3
Initialization of the SSE Extensions
16-2
16.1.4
Providing Non-Numeric Exception Handlers for Exceptions Generated by the SSE Instructions
16-4
16.1.5
Providing a Handler for the SIMD Floating-Point Exception (#XM)
16-5
16.1.5.1
Numeric Error flag and IGNNE#
16-6
16.2
EMULATION OF SSE EXTENSIONS
16-6
16.3
SAVING AND RESTORING SSE STATE
16-6
16.4
DESIGNING OS FACILITIES FOR SAVING X87 FPU, SSE, AND EXTENDED STATES ON TASK OR CONTEXT SWITCHES
16-6
16.4.1
Using the TS Flag to Control the Saving of the x87 FPU and SSE State
16-7
16.5
THE XSAVE FEATURE SET AND PROCESSOR EXTENDED STATE MANAGEMENT
16-7
16.5.1
Checking the Support for XSAVE Feature Set
16-8
16.5.2
Determining the XSAVE Managed Feature States And The Required Buffer Size
16-8
16.5.3
Enable the Use Of XSAVE Feature Set And XSAVE State Components
16-9
16.5.4
Provide an Initialization for the XSAVE State Components
16-9
16.5.5
Providing the Required Exception Handlers
16-9
16.6
INTEROPERABILITY OF THE XSAVE FEATURE SET AND FXSAVE/FXRSTOR
16-9
16.7
THE XSAVE FEATURE SET AND PROCESSOR SUPERVISOR STATE MANAGEMENT
16-10
16.8
SYSTEM PROGRAMMING FOR XSAVE MANAGED FEATURES
16-10
16.8.1
Intel® Advanced Vector Extensions (Intel® AVX)
16-11
16.8.2
Intel® Advanced Vector Extensions 512 (Intel® AVX-512)
16-11
CHAPTER 17
POWER AND THERMAL MANAGEMENT
17.1
ENHANCED INTEL SPEEDSTEP® TECHNOLOGY
17-1
17.1.1
Software Interface For Initiating Performance State Transitions
17-1
17.2
P-STATE HARDWARE COORDINATION
17-1
17.3
SYSTEM SOFTWARE CONSIDERATIONS AND OPPORTUNISTIC PROCESSOR PERFORMANCE OPERATION
17-3
17.3.1
Intel® Dynamic Acceleration Technology
17-3
17.3.2
System Software Interfaces for Opportunistic Processor Performance Operation
17-3
17.3.2.1
Discover Hardware Support and Enabling of Opportunistic Processor Performance Operation
17-4
17.3.2.2
OS Control of Opportunistic Processor Performance Operation
17-4
17.3.2.3
Required Changes to OS Power Management P-State Policy
17-4
17.3.3
Intel® Turbo Boost Technology
17-5
17.3.4
Performance and Energy Bias Hint Support
17-5
17.4
HARDWARE-CONTROLLED PERFORMANCE STATES (HWP)
17-6
17.4.1
HWP Programming Interfaces
17-6
17.4.2
Enabling HWP
17-7
17.4.3
HWP Performance Range and Dynamic Capabilities
17-7
17.4.4
Managing HWP
17-8
17.4.4.1
IA32_HWP_REQUEST MSR (Address: 774H Logical Processor Scope)
17-8
17.4.4.2
IA32_HWP_REQUEST_PKG MSR (Address: 772H Package Scope)
17-11
17.4.4.3
IA32_HWP_PECI_REQUEST_INFO MSR (Address 775H Package Scope)
17-11
17.4.4.4
IA32_HWP_CTL MSR (Address: 776H Logical Processor Scope)
17-12
17.4.5
HWP Feedback
17-13
17.4.5.1
Non-Architectural HWP Feedback
17-15
17.4.6
HWP Notifications
17-16
17.4.7
Idle Logical Processor Impact on Core Frequency
17-16
17.4.8
Fast Write of Uncore MSR (Model Specific Feature)
17-17
17.4.8.1
FAST_UNCORE_MSRS_CAPABILITY (Address: 65FH, Logical Processor Scope)
17-17
17.4.8.2
FAST_UNCORE_MSRS_CTL (Address: 657H, Logical Processor Scope)
17-17
17.4.8.3
FAST_UNCORE_MSRS_STATUS (Address: 65EH, Logical Processor Scope)
17-18
17.4.9
Fast_IA32_HWP_REQUEST CPUID
17-18
17.4.10
Recommendations for OS use of HWP Controls
17-18
17.5
HARDWARE DUTY CYCLING (HDC)
17-20
17.5.1
Hardware Duty Cycling Programming Interfaces
17-20
17.5.2
Package level Enabling HDC
17-21
17.5.3
Logical-Processor Level HDC Control
17-22
17.5.4
HDC Residency Counters
17-22
17.5.4.1
IA32_THREAD_STALL
17-22
17.5.4.2
Non-Architectural HDC Residency Counters
17-23
17.5.5
MPERF and APERF Counters Under HDC
17-25
17.6
HARDWARE FEEDBACK INTERFACE AND INTEL® THREAD DIRECTOR
17-25
17.6.1
Hardware Feedback Interface Table Structure
17-25
17.6.2
Intel® Thread Director Table Structure
17-27
17.6.3
Intel® Thread Director Usage Model
17-30
Vol. 3A xiii
CONTENTS
PAGE
17.6.4
Hardware Feedback Interface Pointer
17-31
17.6.5
Hardware Feedback Interface Configuration
17-31
17.6.6
Hardware Feedback Interface Notifications
17-32
17.6.7
Hardware Feedback Interface and Intel® Thread Director Structure Dynamic Update
17-33
17.6.8
Logical Processor Scope Intel® Thread Director Configuration
17-33
17.6.9
Implicit Reset of Package and Logical Processor Scope Configuration MSRs
17-34
17.6.10
Logical Processor Scope Intel® Thread Director Run Time Characteristics
17-34
17.6.11
Logical Processor Scope History
17-34
17.6.11.1
Enabling Intel® Thread Director History Reset
17-35
17.6.11.2
Implicit Intel® Thread Director History Reset
17-35
17.7
MWAIT EXTENSIONS FOR ADVANCED POWER MANAGEMENT
17-35
17.8
THERMAL MONITORING AND PROTECTION
17-36
17.8.1
Catastrophic Shutdown Detector
17-37
17.8.2
Thermal Monitor
17-37
17.8.2.1
Thermal Monitor 1
17-37
17.8.2.2
Thermal Monitor 2
17-37
17.8.2.3
Two Methods for Enabling TM2
17-37
17.8.2.4
Performance State Transitions and Thermal Monitoring
17-38
17.8.2.5
Thermal Status Information
17-38
17.8.2.6
Adaptive Thermal Monitor
17-39
17.8.3
Software Controlled Clock Modulation
17-40
17.8.3.1
Extension of Software Controlled Clock Modulation
17-41
17.8.4
Detection of Thermal Monitor and Software Controlled Clock Modulation Facilities
17-41
17.8.4.1
Detection of Software Controlled Clock Modulation Extension
17-41
17.8.5
On Die Digital Thermal Sensors
17-42
17.8.5.1
Digital Thermal Sensor Enumeration
17-42
17.8.5.2
Reading the Digital Sensor
17-42
17.8.6
Power Limit Notification
17-45
17.9
PACKAGE LEVEL THERMAL MANAGEMENT
17-45
17.9.1
Support for Passive and Active cooling
17-47
17.10
PLATFORM SPECIFIC POWER MANAGEMENT SUPPORT
17-48
17.10.1
RAPL Interfaces
17-48
17.10.2
RAPL Domains and Platform Specificity
17-49
17.10.3
Package RAPL Domain
17-50
17.10.4
PP0/PP1 RAPL Domains
17-52
17.10.5
DRAM RAPL Domain
17-54
CHAPTER 18
MACHINE-CHECK ARCHITECTURE
18.1
MACHINE-CHECK ARCHITECTURE
18-1
18.2
COMPATIBILITY WITH PENTIUM PROCESSOR
18-1
18.3
MACHINE-CHECK MSRS
18-2
18.3.1
Machine-Check Global Control MSRs
18-2
18.3.1.1
IA32_MCG_CAP MSR
18-2
18.3.1.2
IA32_MCG_STATUS MSR
18-4
18.3.1.3
IA32_MCG_CTL MSR
18-4
18.3.1.4
IA32_MCG_EXT_CTL MSR
18-5
18.3.1.5
Enabling Local Machine Check
18-5
18.3.2
Error-Reporting Register Banks
18-5
18.3.2.1
IA32_MCi_CTL MSRs
18-6
18.3.2.2
IA32_MCi_STATUS MSRS
18-6
18.3.2.3
IA32_MCi_ADDR MSRs
18-9
18.3.2.4
IA32_MCi_MISC MSRs
18-9
18.3.2.5
IA32_MCi_CTL2 MSRs
18-11
18.3.2.6
IA32_MCG Extended Machine Check State MSRs
18-12
18.3.3
Mapping of the Pentium Processor Machine-Check Errors to the Machine-Check Architecture
18-13
18.4
ENHANCED CACHE ERROR REPORTING
18-13
18.5
CORRECTED MACHINE CHECK ERROR INTERRUPT
18-14
18.5.1
CMCI Local APIC Interface
18-14
18.5.2
System Software Recommendation for Managing CMCI and Machine Check Resources
18-15
18.5.2.1
CMCI Initialization
18-15
18.5.2.2
CMCI Threshold Management
18-16
18.5.2.3
CMCI Interrupt Handler
18-16
18.6
RECOVERY OF UNCORRECTED RECOVERABLE (UCR) ERRORS
18-16
xiv Vol. 3A
CONTENTS
PAGE
18.6.1
Detection of Software Error Recovery Support
18-16
18.6.2
UCR Error Reporting and Logging
18-16
18.6.3
UCR Error Classification
18-17
18.6.4
UCR Error Overwrite Rules
18-18
18.7
STATIC LOCKSTEP MODE
18-19
18.8
MACHINE-CHECK AVAILABILITY
18-19
18.9
MACHINE-CHECK INITIALIZATION
18-19
18.10
INTERPRETING THE MCA ERROR CODES
18-21
18.10.1
Simple Error Codes
18-21
18.10.2
Compound Error Codes
18-21
18.10.2.1
Correction Report Filtering (F) Bit
18-22
18.10.2.2
Transaction Type (TT) Sub-Field
18-22
18.10.2.3
Level (LL) Sub-Field
18-22
18.10.2.4
Request (RRRR) Sub-Field
18-23
18.10.2.5
Bus and Interconnect Errors
18-23
18.10.2.6
Memory Controller and Extended Memory Errors
18-24
18.10.3
Architecturally Defined UCR Errors
18-24
18.10.3.1
Architecturally Defined SRAO Errors
18-24
18.10.3.2
Architecturally Defined SRAR Errors
18-25
18.10.4
Multiple MCA Errors
18-27
18.10.5
Machine-Check Error Codes Interpretation
18-28
18.11
GUIDELINES FOR WRITING MACHINE-CHECK SOFTWARE
18-28
18.11.1
Machine-Check Exception Handler
18-28
18.11.2
Pentium Processor Machine-Check Exception Handling
18-30
18.11.3
Logging Correctable Machine-Check Errors
18-30
18.11.4
Machine-Check Software Handler Guidelines for Error Recovery
18-31
18.11.4.1
Machine-Check Exception Handler for Error Recovery
18-31
18.11.4.2
Corrected Machine-Check Handler for Error Recovery
18-36
CHAPTER 19
INTERPRETING MACHINE CHECK ERROR CODES
19.1
INCREMENTAL DECODING INFORMATION: PROCESSOR FAMILY 06H, MACHINE ERROR CODES FOR MACHINE CHECK . . . 19-1
19.2
INCREMENTAL DECODING INFORMATION: INTEL® CORE™ 2 PROCESSOR FAMILY, MACHINE ERROR CODES FOR MACHINE CHECK
19-3
19.2.1
Model-Specific Machine Check Error Codes for Intel® Xeon® Processor 7400 Series
19-5
19.2.1.1
Processor Machine Check Status Register, Incremental MCA Error Code Definition
19-5
19.2.2
Intel® Xeon® Processor 7400 Model Specific Error Code Field
19-6
19.2.2.1
Processor Model Specific Error Code Field, Type B: Bus and Interconnect Error Codes
19-6
19.2.2.2
Processor Model Specific Error Code Field, Type C: Cache Bus Controller Error Codes
19-6
19.3
INCREMENTAL DECODING INFORMATION: INTEL® XEON® PROCESSOR 3400, 3500, 5500 SERIES, MACHINE ERROR CODES FOR
MACHINE CHECK
19-7
19.3.1
Intel® QPI Machine Check Errors
19-7
19.3.2
Internal Machine Check Errors
19-8
19.3.3
Memory Controller Errors
19-9
19.4
INCREMENTAL DECODING INFORMATION: INTEL® XEON® PROCESSOR E5 FAMILY, MACHINE ERROR CODES FOR MACHINE CHECK
19-9
19.4.1
Internal Machine Check Errors
19-10
19.4.2
Intel® QPI Machine Check Errors
19-11
19.4.3
Integrated Memory Controller Machine Check Errors
19-11
19.5
INCREMENTAL DECODING INFORMATION: INTEL® XEON® PROCESSOR E5 V2 AND INTEL® XEON® PROCESSOR E7 V2 FAMILIES,
MACHINE ERROR CODES FOR MACHINE CHECK
19-12
19.5.1
Internal Machine Check Errors
19-12
19.5.2
Integrated Memory Controller Machine Check Errors
19-13
19.5.3
Home Agent Machine Check Errors
19-14
19.6
INCREMENTAL DECODING INFORMATION: INTEL® XEON® PROCESSOR E5 V3 FAMILY, MACHINE ERROR CODES FOR MACHINE
CHECK
19-15
19.6.1
Internal Machine Check Errors
19-15
19.6.2
Intel® QPI Machine Check Errors
19-16
19.6.3
Integrated Memory Controller Machine Check Errors
19-17
19.6.4
Home Agent Machine Check Errors
19-19
19.7
INCREMENTAL DECODING INFORMATION: INTEL® XEON® PROCESSOR D FAMILY, MACHINE ERROR CODES FOR MACHINE CHECK
19-19
19.7.1
Internal Machine Check Errors
19-19
19.7.2
Integrated Memory Controller Machine Check Errors
19-20
Vol. 3A xv
CONTENTS
PAGE
19.8
INCREMENTAL DECODING INFORMATION: INTEL® XEON® PROCESSOR E5 V4 FAMILY, MACHINE ERROR CODES FOR MACHINE
CHECK
19-21
19.8.1
Integrated Memory Controller Machine Check Errors
19-21
19.8.2
Home Agent Machine Check Errors
19-21
19.9
INCREMENTAL DECODING INFORMATION: INTEL® XEON® SCALABLE PROCESSOR FAMILY, MACHINE ERROR CODES FOR
MACHINE CHECK
19-22
19.9.1
Internal Machine Check Errors
19-22
19.9.2
Interconnect Machine Check Errors
19-24
19.9.3
Integrated Memory Controller Machine Check Errors
19-25
19.9.4
M2M Machine Check Errors
19-26
19.9.5
Home Agent Machine Check Errors
19-27
19.10
INCREMENTAL DECODING INFORMATION: PROCESSOR FAMILY WITH CPUID DISPLAYFAMILY_DISPLAYMODEL SIGNATURE
06_5FH, MACHINE ERROR CODES FOR MACHINE CHECK
19-27
19.10.1
Integrated Memory Controller Machine Check Errors
19-28
19.11
INCREMENTAL DECODING INFORMATION: 3RD GENERATION INTEL® XEON® SCALABLE PROCESSOR FAMILY, MACHINE ERROR
CODES FOR MACHINE CHECK
19-28
19.11.1
Internal Machine Check Errors
19-29
19.11.2
Interconnect Machine Check Errors
19-31
19.11.3
Integrated Memory Controller Machine Check Errors
19-32
19.11.4
M2M Machine Check Errors
19-36
19.12
INCREMENTAL DECODING INFORMATION: PROCESSOR FAMILY WITH CPUID DISPLAYFAMILY_DISPLAYMODEL SIGNATURE
06_86H, MACHINE ERROR CODES FOR MACHINE CHECK
19-36
19.12.1
Integrated Memory Controller Machine Check Errors
19-36
19.12.2
M2M Machine Check Errors
19-37
19.13
INCREMENTAL DECODING INFORMATION: 4TH GENERATION INTEL® XEON® SCALABLE PROCESSOR FAMILY, MACHINE ERROR
CODES FOR MACHINE CHECK
19-37
19.13.1
Internal Machine Check Errors
19-37
19.13.2
Interconnect Machine Check Errors
19-39
19.13.3
Integrated Memory Controller Machine Check Errors
19-41
19.13.4
M2M Machine Check Errors
19-43
19.13.5
High Bandwidth Memory Machine Check Errors
19-44
19.14
INCREMENTAL DECODING INFORMATION: PROCESSOR FAMILY 0FH, MACHINE ERROR CODES FOR MACHINE CHECK . . 19-44
19.14.1
Model-Specific Machine Check Error Codes for the Intel® Xeon® Processor MP 7100 Series
19-45
19.14.1.1
Processor Machine Check Status Register MCA Error Code Definition
19-46
19.14.2
Other_Info Field (All MCA Error Types)
19-47
19.14.3
Processor Model Specific Error Code Field
19-48
19.14.3.1
MCA Error Type A: L3 Error
19-48
19.14.3.2
Processor Model Specific Error Code Field Type B: Bus and Interconnect Error
19-48
19.14.3.3
Processor Model Specific Error Code Field Type C: Cache Bus Controller Error
19-49
CHAPTER 20
DEBUG, BRANCH PROFILE, TSC, AND INTEL® RESOURCE DIRECTOR TECHNOLOGY (INTEL® RDT)
FEATURES
20.1
OVERVIEW OF DEBUG SUPPORT FACILITIES
20-1
20.2
DEBUG REGISTERS
20-2
20.2.1
Debug Address Registers (DR0-DR3)
20-4
20.2.2
Debug Registers DR4 and DR5
20-4
20.2.3
Debug Status Register (DR6)
20-4
20.2.4
Debug Control Register (DR7)
20-4
20.2.5
Breakpoint Field Recognition
20-6
20.2.6
Debug Registers and Intel® 64 Processors
20-7
20.3
DEBUG EXCEPTIONS
20-7
20.3.1
Debug Exception (#DB)-Interrupt Vector 1
20-7
20.3.1.1
Instruction-Breakpoint Exception Condition
20-9
20.3.1.2
Data Memory and I/O Breakpoint Exception Conditions
20-10
20.3.1.3
General-Detect Exception Condition
20-10
20.3.1.4
Single-Step Exception Condition
20-11
20.3.1.5
Task-Switch Exception Condition
20-11
20.3.1.6
OS Bus-Lock Detection
20-11
20.3.2
Breakpoint Exception (#BP)-Interrupt Vector 3
20-11
20.3.3
Debug Exceptions, Breakpoint Exceptions, and Restricted Transactional Memory (RTM)
20-12
20.4
LAST BRANCH, INTERRUPT, AND EXCEPTION RECORDING OVERVIEW
20-12
20.4.1
IA32_DEBUGCTL MSR
20-13
xvi Vol. 3A
CONTENTS
PAGE
20.4.2
Monitoring Branches, Exceptions, and Interrupts
20-14
20.4.3
Single-Stepping on Branches
20-14
20.4.4
Branch Trace Messages
20-15
20.4.4.1
Branch Trace Message Visibility
20-15
20.4.5
Branch Trace Store (BTS)
20-15
20.4.6
CPL-Qualified Branch Trace Mechanism
20-15
20.4.7
Freezing LBR and Performance Counters on PMI
20-15
20.4.8
LBR Stack
20-17
20.4.8.1
LBR Stack and Intel® 64 Processors
20-18
20.4.8.2
LBR Stack and IA-32 Processors
20-19
20.4.8.3
Last Exception Records and Intel 64 Architecture
20-19
20.4.9
BTS and DS Save Area
20-19
20.4.9.1
64 Bit Format of the DS Save Area
20-22
20.4.9.2
Setting Up the DS Save Area
20-24
20.4.9.3
Setting Up the BTS Buffer
20-25
20.4.9.4
Setting Up CPL-Qualified BTS
20-26
20.4.9.5
Writing the DS Interrupt Service Routine
20-26
20.5
LAST BRANCH, INTERRUPT, AND EXCEPTION RECORDING (INTEL® CORE™ 2 DUO AND INTEL ATOM® PROCESSORS) . . 20-27
20.5.1
LBR Stack
20-27
20.5.2
LBR Stack in Intel Atom® Processors based on the Silvermont Microarchitecture
20-28
20.6
LAST BRANCH, CALL STACK, INTERRUPT, AND EXCEPTION RECORDING FOR PROCESSORS BASED ON GOLDMONT
MICROARCHITECTURE
20-28
20.7
LAST BRANCH, CALL STACK, INTERRUPT, AND EXCEPTION RECORDING FOR PROCESSORS BASED ON GOLDMONT PLUS
MICROARCHITECTURE
20-29
20.8
LAST BRANCH, INTERRUPT, AND EXCEPTION RECORDING FOR INTEL® XEON PHI™ PROCESSOR 7200/5200/3200 . . . 20-29
20.9
LAST BRANCH, INTERRUPT, AND EXCEPTION RECORDING FOR PROCESSORS BASED ON NEHALEM MICROARCHITECTURE 20-
29
20.9.1
LBR Stack
20-30
20.9.2
Filtering of Last Branch Records
20-31
20.10
LAST BRANCH, INTERRUPT, AND EXCEPTION RECORDING FOR PROCESSORS BASED ON SANDY BRIDGE MICROARCHITECTURE
20-31
20.11
LAST BRANCH, CALL STACK, INTERRUPT, AND EXCEPTION RECORDING FOR PROCESSORS BASED ON HASWELL
MICROARCHITECTURE
20-32
20.11.1
LBR Stack Enhancement
20-33
20.12
LAST BRANCH, CALL STACK, INTERRUPT, AND EXCEPTION RECORDING FOR PROCESSORS BASED ON SKYLAKE
MICROARCHITECTURE
20-33
20.12.1
MSR_LBR_INFO_x MSR
20-34
20.12.2
Streamlined Freeze_LBRs_On_PMI Operation
20-34
20.12.3
LBR Behavior and Deep C-State
20-35
20.13
LAST BRANCH, INTERRUPT, AND EXCEPTION RECORDING (PROCESSORS BASED ON INTEL NETBURST® MICROARCHITECTURE)
20-35
20.13.1
MSR_DEBUGCTLA MSR
20-35
20.13.2
LBR Stack for Processors Based on Intel NetBurst® Microarchitecture
20-36
20.13.3
Last Exception Records
20-37
20.14
LAST BRANCH, INTERRUPT, AND EXCEPTION RECORDING (INTEL® CORE™ SOLO AND INTEL® CORE™ DUO PROCESSORS) 20-38
20.15
LAST BRANCH, INTERRUPT, AND EXCEPTION RECORDING (PENTIUM M PROCESSORS)
20-39
20.16
LAST BRANCH, INTERRUPT, AND EXCEPTION RECORDING (P6 FAMILY PROCESSORS)
20-40
20.16.1
DEBUGCTLMSR Register
20-40
20.16.2
Last Branch and Last Exception MSRs
20-41
20.16.3
Monitoring Branches, Exceptions, and Interrupts
20-42
20.17
TIME-STAMP COUNTER
20-42
20.17.1
Invariant TSC
20-43
20.17.2
IA32_TSC_AUX Register and RDTSCP Support
20-43
20.17.3
Time-Stamp Counter Adjustment
20-44
20.17.4
Invariant Time-Keeping
20-44
20.18
INTEL® RESOURCE DIRECTOR TECHNOLOGY (INTEL® RDT) MONITORING FEATURES
20-44
20.18.1
Overview of Cache Monitoring Technology and Memory Bandwidth Monitoring
20-45
20.18.2
Enabling Monitoring: Usage Flow
20-45
20.18.3
Enumeration and Detecting Support of Cache Monitoring Technology and Memory Bandwidth Monitoring
20-46
20.18.4
Monitoring Resource Type and Capability Enumeration
20-46
20.18.5
Feature-Specific Enumeration
20-47
20.18.5.1
Cache Monitoring Technology
20-48
20.18.5.2
Memory Bandwidth Monitoring
20-48
20.18.6
Monitoring Resource RMID Association
20-49
20.18.7
Monitoring Resource Selection and Reporting Infrastructure
20-50
Vol. 3A xvii
CONTENTS
PAGE
20.18.8
Monitoring Programming Considerations
20-51
20.18.8.1
Monitoring Dynamic Configuration
20-52
20.18.8.2
Monitoring Operation With Power Saving Features
20-52
20.18.8.3
Monitoring Operation with Other Operating Modes
20-52
20.18.8.4
Monitoring Operation with RAS Features
20-52
20.19
INTEL® RESOURCE DIRECTOR TECHNOLOGY (INTEL® RDT) ALLOCATION FEATURES
20-52
20.19.1
Introduction to Cache Allocation Technology (CAT)
20-52
20.19.2
Cache Allocation Technology Architecture
20-53
20.19.3
Code and Data Prioritization (CDP) Technology
20-56
20.19.4
Enabling Cache Allocation Technology Usage Flow
20-57
20.19.4.1
Enumeration and Detection Support of Cache Allocation Technology
20-58
20.19.4.2
Cache Allocation Technology: Resource Type and Capability Enumeration
20-58
20.19.4.3
Cache Allocation Technology: Cache Mask Configuration
20-61
20.19.4.4
Class of Service to Cache Mask Association: Common Across Allocation Features
20-62
20.19.5
Code and Data Prioritization (CDP): Enumerating and Enabling L3 CDP Technology
20-62
20.19.5.1
Mapping Between L3 CDP Masks and CAT Masks
20-63
20.19.6
Code and Data Prioritization (CDP): Enumerating and Enabling L2 CDP Technology
20-63
20.19.6.1
Mapping Between L2 CDP Masks and L2 CAT Masks
20-64
20.19.6.2
Common L2 and L3 CDP Programming Considerations
20-64
20.19.6.3
Cache Allocation Technology Dynamic Configuration
20-65
20.19.6.4
Cache Allocation Technology Operation With Power Saving Features
20-65
20.19.6.5
Cache Allocation Technology Operation with Other Operating Modes
20-65
20.19.6.6
Associating Threads with CAT/CDP Classes of Service
20-66
20.19.7
Introduction to Memory Bandwidth Allocation
20-66
20.19.7.1
Memory Bandwidth Allocation Enumeration
20-66
20.19.7.2
Memory Bandwidth Allocation Configuration
20-67
20.19.7.3
Memory Bandwidth Allocation Usage Considerations
20-69
20.19.8
Cache Bandwidth Allocation (CBA)
20-69
20.19.8.1
Introduction to Cache Bandwidth Allocation
20-69
20.19.8.2
Cache Bandwidth Allocation Enumeration
20-69
20.19.8.3
Cache Bandwidth Allocation Configuration
20-70
20.19.8.4
Cache Bandwidth Allocation Usage Considerations
20-72
20.20
INTEL® RESOURCE DIRECTOR TECHNOLOGY (INTEL® RDT) FOR NON-CPU AGENTS
20-72
20.20.1
Non-CPU Agent Intel® RDT Features Enumeration Details
20-72
20.20.1.1
CPUID-Based Enumeration for Non-CPU Agent Intel® RDT Feature
20-72
20.20.1.2
ACPI Enumeration
20-73
20.20.2
Non-CPU Agent Intel® RDT Feature Enable MSR
20-73
20.20.3
Asymmetrical Enumeration of Intel® RDT Features
20-74
20.21
INTEL® RDT DERIVATIVE TECHNOLOGIES
20-76
20.21.1
Core Telemetry for Intel® Platform Monitoring Technology (PMT)
20-76
20.21.2
Resource Priority
20-76
20.21.2.1
Resource Priority Enumeration Details
20-76
20.21.2.2
Resource Priority Feature Enable MSRs
20-78
CHAPTER 21
LAST BRANCH RECORDS
21.1
BEHAVIOR
21-1
21.1.1
Logged Operations
21-1
21.1.2
Configuration
21-2
21.1.2.1
Enabling and Disabling
21-2
21.1.2.2
LBR Depth
21-2
21.1.2.3
Branch Type Enabling and Filtering
21-2
21.1.2.4
Call-Stack Mode
21-3
Call-Stack Mode and LBR Freeze
21-3
21.1.2.5
CPL Filtering
21-4
21.1.3
Record Data
21-4
21.1.3.1
IP Fields
21-4
21.1.3.2
Branch Types
21-4
21.1.3.3
Cycle Time
21-4
21.1.3.4
Mispredict Information
21-5
21.1.3.5
Intel® TSX Information
21-5
21.1.3.6
LBR Event Logging
21-5
21.1.4
Interaction with Other Processor Features
21-5
xviii Vol. 3A
CONTENTS
PAGE
21.1.4.1
SMM
21-5
21.1.4.2
SMM Transfer Monitor (STM)
21-5
21.1.4.3
VMX
21-6
21.1.4.4
Intel® SGX
21-6
21.1.4.5
Debug Exceptions
21-6
21.1.4.6
SMX
21-6
21.1.4.7
MWAIT
21-6
21.1.4.8
Processor Event-Based Sampling (PEBS)
21-6
21.2
MSRS
21-7
21.3
FAST LBR READ ACCESS
21-7
21.4
OTHER IMPACTS
21-7
21.4.1
Branch Trace Store on Intel Atom® Processors
21-7
21.4.2
IA32_DEBUGCTL
21-7
21.4.3
IA32_PERF_CAPABILITIES
21-7
CHAPTER 22
PERFORMANCE MONITORING
22.1
PERFORMANCE MONITORING OVERVIEW
22-1
22.2
ARCHITECTURAL PERFORMANCE MONITORING
22-2
22.2.1
Architectural Performance Monitoring Version 1
22-3
22.2.2
Architectural Performance Monitoring Version 2
22-5
22.2.3
Architectural Performance Monitoring Version 3
22-9
22.2.3.1
AnyThread Counting and Software Evolution
22-11
22.2.4
Architectural Performance Monitoring Version 4
22-12
22.2.4.1
Enhancement in IA32_PERF_GLOBAL_STATUS
22-12
22.2.4.2
IA32_PERF_GLOBAL_STATUS_RESET and IA32_PERF_GLOBAL_STATUS_SET MSRS
22-13
22.2.4.3
IA32_PERF_GLOBAL_INUSE MSR
22-14
22.2.5
Architectural Performance Monitoring Version 5
22-15
22.2.5.1
AnyThread Mode Deprecation
22-15
22.2.5.2
Fixed Counter Enumeration
22-15
22.2.5.3
Domain Separation
22-15
22.2.6
Architectural Performance Monitoring Version 6
22-15
22.2.6.1
Performance Monitoring MSR Aliasing
22-16
22.2.6.2
Unit Mask 2
22-17
22.2.6.3
Equal Flag
22-18
22.2.7
Pre-defined Architectural Performance Events
22-18
22.2.8
Full-Width Writes to Performance Counter Registers
22-20
22.2.9
Scalable Enumeration Architecture
22-21
22.2.9.1
CPUID Sub-leaves
22-21
22.2.9.2
Reporting Per Logical Processor
22-21
22.2.9.3
General-Purpose Counters Bitmap
22-22
22.2.9.4
Fixed-Function Counters True-View Bitmap
22-22
22.2.9.5
Architectural Performance Monitoring Events Bitmap
22-22
22.2.9.6
TMA Slots Per Cycle
22-22
22.3
PERFORMANCE MONITORING (INTEL® CORE™ PROCESSORS AND INTEL® XEON® PROCESSORS)
22-23
22.3.1
Performance Monitoring for Processors Based on Nehalem Microarchitecture
22-23
22.3.1.1
Enhancements of Performance Monitoring in the Processor Core
22-24
22.3.1.2
Performance Monitoring Facility in the Uncore
22-31
22.3.1.3
Intel® Xeon® Processor 7500 Series Performance Monitoring Facility
22-36
22.3.2
Performance Monitoring for Processors Based on Westmere Microarchitecture
22-37
22.3.3
Intel® Xeon® Processor E7 Family Performance Monitoring Facility
22-38
22.3.4
Performance Monitoring for Processors Based on Sandy Bridge Microarchitecture
22-38
22.3.4.1
Global Counter Control Facilities in Sandy Bridge Microarchitecture
22-39
22.3.4.2
Counter Coalescence
22-41
22.3.4.3
Full Width Writes to Performance Counters
22-41
22.3.4.4
PEBS Support in Sandy Bridge Microarchitecture
22-41
22.3.4.5
Off-core Response Performance Monitoring
22-46
22.3.4.6
Uncore Performance Monitoring Facilities in the Intel® Core™ i7-2xxx, Intel® Core™ i5-2xxx, and Intel® Core™ i3-2xxx
Processor Series
22-49
22.3.4.7
Intel® Xeon® Processor E5 Family Performance Monitoring Facility
22-51
22.3.4.8
Intel® Xeon® Processor E5 Family Uncore Performance Monitoring Facility
22-51
22.3.5
3rd Generation Intel® Core™ Processor Performance Monitoring Facility
22-52
22.3.5.1
Intel® Xeon® Processor E5 v2 and E7 v2 Family Uncore Performance Monitoring Facility
22-52
22.3.6
4th Generation Intel® Core™ Processor Performance Monitoring Facility
22-52
Vol. 3A xix
CONTENTS
PAGE
22.3.6.1
Processor Event Based Sampling (PEBS) Facility
22-53
22.3.6.2
PEBS Data Format
22-54
22.3.6.3
PEBS Data Address Profiling
22-55
22.3.6.4
Off-core Response Performance Monitoring
22-56
22.3.6.5
Performance Monitoring and Intel® TSX
22-58
22.3.6.6
Uncore Performance Monitoring Facilities in the 4th Generation Intel® Core™ Processors
22-60
22.3.6.7
Intel® Xeon® Processor E5 v3 Family Uncore Performance Monitoring Facility
22-60
22.3.7
5th Generation Intel® Core™ Processor and Intel® Core™ M Processor Performance Monitoring Facility
22-61
22.3.8
6th Generation, 7th Generation and 8th Generation Intel® Core™ Processor Performance Monitoring Facility
22-62
22.3.8.1
Processor Event Based Sampling (PEBS) Facility
22-63
22.3.8.2
Frontend Retired Facility
22-66
22.3.8.3
Off-core Response Performance Monitoring
22-68
22.3.8.4
Uncore Performance Monitoring Facilities on Intel® Core™ Processors Based on Cannon Lake Microarchitecture .22-71
22.3.9
10th Generation Intel® Core™ Processor Performance Monitoring Facility
22-72
22.3.9.1
Processor Event Based Sampling (PEBS) Facility
22-72
22.3.9.2
Off-core Response Performance Monitoring
22-72
22.3.9.3
Performance Metrics
22-74
22.3.10
12th and 13th Generation Intel® Core™ Processors, and 4th and 5th Generation Intel® Xeon® Scalable Processor Family
Performance Monitoring Facility
22-76
22.3.10.1
P-core Performance Monitoring Unit
22-76
22.3.10.2
E-core Performance Monitoring Unit
22-78
22.3.10.3
Unhalted Reference Cycles
22-81
22.3.11
Intel® Series 2 Core™ Ultra Processor Performance Monitoring Facility
22-81
22.3.11.1
P-core Performance Monitoring Unit
22-81
22.3.11.2
E-core Performance Monitoring Unit
22-83
22.4
PERFORMANCE MONITORING (INTEL® XEON™ PHI PROCESSORS)
22-83
22.4.1
Intel® Xeon Phi™ Processor 7200/5200/3200 Performance Monitoring
22-83
22.4.1.1
Enhancements of Performance Monitoring in the Intel® Xeon Phi™ Processor Tile
22-84
22.5
PERFORMANCE MONITORING (INTEL ATOM® PROCESSORS)
22-87
22.5.1
Performance Monitoring (45 nm and 32 nm Intel Atom® Processors)
22-87
22.5.2
Performance Monitoring for Silvermont Microarchitecture
22-88
22.5.2.1
Enhancements of Performance Monitoring in the Processor Core
22-88
22.5.2.2
Offcore Response Event
22-90
22.5.2.3
Average Offcore Request Latency Measurement
22-93
22.5.3
Performance Monitoring for Goldmont Microarchitecture
22-93
22.5.3.1
Processor Event Based Sampling (PEBS)
22-94
22.5.3.2
Offcore Response Event
22-97
22.5.3.3
Average Offcore Request Latency Measurement
22-99
22.5.4
Performance Monitoring for Goldmont Plus Microarchitecture
22-99
22.5.4.1
Extended PEBS
22-99
22.5.5
Performance Monitoring for Tremont Microarchitecture
22-100
22.5.5.1
Adaptive PEBS
22-100
22.5.5.2
PEBS output to Intel® Processor Trace
22-101
22.5.5.3
Precise Distribution Support on Fixed Counter 0
22-102
22.5.5.4
Compatibility Enhancements to Offcore Response MSRs
22-102
22.6
PERFORMANCE MONITORING (LEGACY INTEL PROCESSORS)
22-104
22.6.1
Performance Monitoring (Intel® Core™ Solo and Intel® Core™ Duo Processors)
22-104
22.6.2
Performance Monitoring (Processors Based on Intel® Core™ Microarchitecture)
22-106
22.6.2.1
Fixed-function Performance Counters
22-107
22.6.2.2
Global Counter Control Facilities
22-107
22.6.2.3
At-Retirement Events
22-109
22.6.2.4
Processor Event Based Sampling (PEBS)
22-109
22.6.3
Performance Monitoring (Processors Based on Intel NetBurst® Microarchitecture)
22-112
22.6.3.1
ESCR MSRs
22-115
22.6.3.2
Performance Counters
22-116
22.6.3.3
CCCR MSRs
22-117
22.6.3.4
Debug Store (DS) Mechanism
22-119
22.6.3.5
Programming the Performance Counters for Non-Retirement Events
22-119
22.6.3.6
At-Retirement Counting
22-125
22.6.3.7
Tagging Mechanism for Replay_event
22-127
22.6.3.8
Processor Event-Based Sampling (PEBS)
22-127
22.6.3.9
Operating System Implications
22-128
22.6.4
Performance Monitoring and Intel® Hyper-Threading Technology in Processors Based on Intel NetBurst® Microarchitecture
22-129
22.6.4.1
ESCR MSRs
22-129
xx Vol. 3A
CONTENTS
PAGE
22.6.4.2
CCCR MSRs
22-130
22.6.4.3
IA32_PEBS_ENABLE MSR
22-131
22.6.4.4
Performance Monitoring Events
22-131
22.6.4.5
Counting Clocks on systems with Intel® Hyper-Threading Technology in Processors Based on Intel NetBurst®
Microarchitecture
22-132
22.6.5
Performance Monitoring and Dual-Core Technology
22-133
22.6.6
Performance Monitoring on 64-bit Intel® Xeon® Processor MP with Up to 8-MByte L3 Cache
22-133
22.6.7
Performance Monitoring on L3 and Caching Bus Controller Sub-Systems
22-136
22.6.7.1
Overview of Performance Monitoring with L3/Caching Bus Controller
22-138
22.6.7.2
GBSQ Event Interface
22-138
22.6.7.3
GSNPQ Event Interface
22-140
22.6.7.4
FSB Event Interface
22-141
22.6.7.5
Common Event Control Interface
22-142
22.6.8
Performance Monitoring (P6 Family Processor)
22-142
22.6.8.1
PerfEvtSel0 and PerfEvtSel1 MSRs
22-143
22.6.8.2
PerfCtr0 and PerfCtr1 MSRs
22-144
22.6.8.3
Starting and Stopping the Performance-Monitoring Counters
22-144
22.6.8.4
Event and Time-Stamp Monitoring Software
22-144
22.6.8.5
Monitoring Counter Overflow
22-145
22.6.9
Performance Monitoring (Pentium Processors)
22-145
22.6.9.1
Control and Event Select Register (CESR)
22-146
22.6.9.2
Use of the Performance-Monitoring Pins
22-146
22.6.9.3
Events Counted
22-147
22.7
COUNTING CLOCKS
22-147
22.7.1
Non-Halted Reference Clockticks
22-148
22.7.2
Cycle Counting and Opportunistic Processor Operation
22-148
22.7.3
Determining the Processor Base Frequency
22-149
22.7.3.1
For Intel® Processors Based on Sandy Bridge, Ivy Bridge, Haswell, and Broadwell Microarchitectures
22-149
22.7.3.2
For Intel® Processors Based on Nehalem Microarchitecture
22-149
22.7.3.3
For Intel Atom® Processors Based on Silvermont Microarchitecture (Including Intel Processors Based on Airmont
Microarchitecture)
22-149
22.7.3.4
For Intel® Core™ 2 Processor Family and for Intel® Xeon® Processors Based on Intel Core Microarchitecture . . . 22-149
22.8
IA32_PERF_CAPABILITIES MSR ENUMERATION
22-150
22.8.1
Filtering of SMM Handler Overhead
22-151
22.9
PEBS FACILITY
22-151
22.9.1
Extended PEBS
22-151
22.9.2
Adaptive PEBS
22-153
22.9.2.1
Adaptive_Record Counter Control
22-154
22.9.2.2
PEBS Record Format
22-155
22.9.2.3
MSR_PEBS_DATA_CFG
22-159
22.9.2.4
PEBS Record Examples
22-162
22.9.3
Precise Distribution of Instructions Retired (PDIR) Facility
22-164
22.9.4
Reduced Skid PEBS
22-164
22.9.5
EPT-Friendly PEBS
22-165
22.9.6
PDist: Precise Distribution
22-165
22.9.7
Load Latency Facility
22-165
22.9.8
Store Latency Facility
22-167
22.9.9
Timed Processor Event Based Sampling
22-168
22.9.10
Counters Snapshotting
22-168
22.10
ARCHITECTURAL PEBS
22-168
22.10.1
Configuration
22-169
22.10.1.1
IA32_PERF_CAPABILITIES
22-169
22.10.1.2
IA32_MISC_ENABLE
22-169
22.10.2
Behavior
22-169
22.10.2.1
Counters
22-169
22.10.2.2
Record Data
22-170
22.10.2.3
Programming PEBS
22-170
22.10.3
Model-Specific Registers (MSRs)
22-172
22.10.3.1
IA32_PEBS_BASE MSR
22-172
22.10.3.2
IA32_PEBS_INDEX MSR
22-173
22.10.3.3
IA32_PMC_GPn_CFG_C and IA32_PMC_FXm_CFG_C MSRs
22-173
22.10.3.4
Changes from Legacy PEBS
22-175
22.10.4
Records and Groups
22-176
22.10.4.1
Basic Group
22-176
22.10.4.2
Auxiliary Group
22-178
Vol. 3A xxi
CONTENTS
PAGE
22.10.4.3
General-Purpose Register Group
22-179
22.10.4.4
XSAVE-Enabled Registers Group
22-180
22.10.4.5
Last Branch Record Group
22-181
22.10.4.6
Performance Counters Group
22-182
22.10.4.7
Fragmented Records
22-183
22.10.5
Interactions with Other Processor Features
22-185
22.10.5.1
Virtualization
22-185
22.10.5.2
Intel® Secure Guard Extensions (Intel® SGX)
22-186
22.10.5.3
Intel® Trust Domain Extensions (Intel® TDX)
22-187
22.10.5.4
System Management Mode (SMM)
22-187
22.10.5.5
SMM-Transfer Monitor (STM)
22-187
22.11
AUTO COUNTER RELOAD
22-187
22.11.1
Discovery and Interface
22-187
22.11.2
Configuration and Behavior
22-188
22.11.2.1
Reload Precision
22-188
22.11.2.2
PEBS Interaction
22-188
22.11.2.3
Precise Distribution (PDIST) Interaction
22-188
CHAPTER 23
8086 EMULATION
23.1
REAL-ADDRESS MODE
23-1
23.1.1
Address Translation in Real-Address Mode
23-2
23.1.2
Registers Supported in Real-Address Mode
23-3
23.1.3
Instructions Supported in Real-Address Mode
23-3
23.1.4
Interrupt and Exception Handling
23-4
23.2
VIRTUAL-8086 MODE
23-5
23.2.1
Enabling Virtual-8086 Mode
23-6
23.2.2
Structure of a Virtual-8086 Task
23-7
23.2.3
Paging of Virtual-8086 Tasks
23-7
23.2.4
Protection within a Virtual-8086 Task
23-8
23.2.5
Entering Virtual-8086 Mode
23-8
23.2.6
Leaving Virtual-8086 Mode
23-9
23.2.7
Sensitive Instructions
23-10
23.2.8
Virtual-8086 Mode I/O
23-10
23.2.8.1
I/O-Port-Mapped I/O
23-11
23.2.8.2
Memory-Mapped I/O
23-11
23.2.8.3
Special I/O Buffers
23-11
23.3
INTERRUPT AND EXCEPTION HANDLING IN VIRTUAL-8086 MODE
23-11
23.3.1
Class 1-Hardware Interrupt and Exception Handling in Virtual-8086 Mode
23-12
23.3.1.1
Handling an Interrupt or Exception Through a Protected-Mode Trap or Interrupt Gate
23-12
23.3.1.2
Handling an Interrupt or Exception With an 8086 Program Interrupt or Exception Handler
23-14
23.3.1.3
Handling an Interrupt or Exception Through a Task Gate
23-14
23.3.2
Class 2-Maskable Hardware Interrupt Handling in Virtual-8086 Mode Using the Virtual Interrupt Mechanism
23-15
23.3.3
Class 3-Software Interrupt Handling in Virtual-8086 Mode
23-16
23.3.3.1
Method 1: Software Interrupt Handling
23-18
23.3.3.2
Methods 2 and 3: Software Interrupt Handling
23-18
23.3.3.3
Method 4: Software Interrupt Handling
23-19
23.3.3.4
Method 5: Software Interrupt Handling
23-19
23.3.3.5
Method 6: Software Interrupt Handling
23-19
23.4
PROTECTED-MODE VIRTUAL INTERRUPTS
23-20
CHAPTER 24
MIXING 16-BIT AND 32-BIT CODE
24.1
DEFINING 16-BIT AND 32-BIT PROGRAM MODULES
24-1
24.2
MIXING 16-BIT AND 32-BIT OPERATIONS WITHIN A CODE SEGMENT
24-2
24.3
SHARING DATA AMONG MIXED-SIZE CODE SEGMENTS
24-3
24.4
TRANSFERRING CONTROL AMONG MIXED-SIZE CODE SEGMENTS
24-3
24.4.1
Code-Segment Pointer Size
24-4
24.4.2
Stack Management for Control Transfer
24-4
24.4.2.1
Controlling the Operand-Size Attribute For a Call
24-5
24.4.2.2
Passing Parameters With a Gate
24-6
24.4.3
Interrupt Control Transfers
24-6
xxii Vol. 3A
CONTENTS
PAGE
24.4.4
Parameter Translation
24-6
24.4.5
Writing Interface Procedures
24-6
CHAPTER 25
ARCHITECTURE COMPATIBILITY
25.1
PROCESSOR FAMILIES AND CATEGORIES
25-1
25.2
RESERVED BITS
25-2
25.3
ENABLING NEW FUNCTIONS AND MODES
25-2
25.4
DETECTING THE PRESENCE OF NEW FEATURES THROUGH SOFTWARE
25-2
25.5
INTEL MMX TECHNOLOGY
25-2
25.6
STREAMING SIMD EXTENSIONS (SSE)
25-3
25.7
STREAMING SIMD EXTENSIONS 2 (SSE2)
25-3
25.8
STREAMING SIMD EXTENSIONS 3 (SSE3)
25-3
25.9
ADDITIONAL STREAMING SIMD EXTENSIONS
25-3
25.10
INTEL HYPER-THREADING TECHNOLOGY
25-3
25.11
MULTI-CORE TECHNOLOGY
25-4
25.12
SPECIFIC FEATURES OF DUAL-CORE PROCESSOR
25-4
25.13
NEW INSTRUCTIONS IN THE PENTIUM AND LATER IA-32 PROCESSORS
25-4
25.13.1
Instructions Added Prior to the Pentium Processor
25-4
25.14
OBSOLETE INSTRUCTIONS
25-5
25.15
UNDEFINED OPCODES
25-5
25.16
NEW FLAGS IN THE EFLAGS REGISTER
25-6
25.16.1
Using EFLAGS Flags to Distinguish Between 32-Bit IA-32 Processors
25-6
25.17
STACK OPERATIONS AND USER SOFTWARE
25-7
25.17.1
PUSH SP
25-7
25.17.2
EFLAGS Pushed on the Stack
25-7
25.18
X87 FPU
25-7
25.18.1
Control Register CR0 Flags
25-8
25.18.2
x87 FPU Status Word
25-8
25.18.2.1
Condition Code Flags (C0 through C3)
25-8
25.18.2.2
Stack Fault Flag
25-8
25.18.3
x87 FPU Control Word
25-9
25.18.4
x87 FPU Tag Word
25-9
25.18.5
Data Types
25-9
25.18.5.1
NaNs
25-9
25.18.5.2
Pseudo-zero, Pseudo-NaN, Pseudo-infinity, and Unnormal Formats
25-9
25.18.6
Floating-Point Exceptions
25-10
25.18.6.1
Denormal Operand Exception (#D)
25-10
25.18.6.2
Numeric Overflow Exception (#O)
25-10
25.18.6.3
Numeric Underflow Exception (#U)
25-10
25.18.6.4
Exception Precedence
25-10
25.18.6.5
CS and EIP For FPU Exceptions
25-11
25.18.6.6
FPU Error Signals
25-11
25.18.6.7
Assertion of the FERR# Pin
25-11
25.18.6.8
Invalid Operation Exception On Denormals
25-11
25.18.6.9
Alignment Check Exceptions (#AC)
25-11
25.18.6.10
Segment Not Present Exception During FLDENV
25-12
25.18.6.11
Device Not Available Exception (#NM)
25-12
25.18.6.12
Coprocessor Segment Overrun Exception
25-12
25.18.6.13
General Protection Exception (#GP)
25-12
25.18.6.14
Floating-Point Error Exception (#MF)
25-12
25.18.7
Changes to Floating-Point Instructions
25-12
25.18.7.1
FDIV, FPREM, and FSQRT Instructions
25-12
25.18.7.2
FSCALE Instruction
25-12
25.18.7.3
FPREM1 Instruction
25-13
25.18.7.4
FPREM Instruction
25-13
25.18.7.5
FUCOM, FUCOMP, and FUCOMPP Instructions
25-13
25.18.7.6
FPTAN Instruction
25-13
25.18.7.7
Stack Overflow
25-13
25.18.7.8
FSIN, FCOS, and FSINCOS Instructions
25-13
25.18.7.9
FPATAN Instruction
25-13
25.18.7.10
F2XM1 Instruction
25-13
25.18.7.11
FLD Instruction
25-14
25.18.7.12
FXTRACT Instruction
25-14
Vol. 3A xxiii
CONTENTS
PAGE
25.18.7.13
Load Constant Instructions
25-14
25.18.7.14
FXAM Instruction
25-14
25.18.7.15
FSAVE and FSTENV Instructions
25-14
25.18.8
Transcendental Instructions
25-14
25.18.9
Obsolete Instructions and Undefined Opcodes
25-15
25.18.10
WAIT/FWAIT Prefix Differences
25-15
25.18.11
Operands Split Across Segments and/or Pages
25-15
25.18.12
FPU Instruction Synchronization
25-15
25.19
SERIALIZING INSTRUCTIONS
25-16
25.20
FPU AND MATH COPROCESSOR INITIALIZATION
25-16
25.20.1
Intel® 387 and Intel® 287 Math Coprocessor Initialization
25-16
25.20.2
Intel486 SX Processor and Intel 487 SX Math Coprocessor Initialization
25-16
25.21
CONTROL REGISTERS
25-17
25.22
MEMORY MANAGEMENT FACILITIES
25-19
25.22.1
New Memory Management Control Flags
25-19
25.22.1.1
Physical Memory Addressing Extension
25-19
25.22.1.2
Global Pages
25-19
25.22.1.3
Larger Page Sizes
25-19
25.22.2
CD and NW Cache Control Flags
25-19
25.22.3
Descriptor Types and Contents
25-19
25.22.4
Changes in Segment Descriptor Loads
25-20
25.23
DEBUG FACILITIES
25-20
25.23.1
Differences in Debug Register DR6
25-20
25.23.2
Differences in Debug Register DR7
25-20
25.23.3
Debug Registers DR4 and DR5
25-20
25.24
RECOGNITION OF BREAKPOINTS
25-20
25.25
EXCEPTIONS AND/OR EXCEPTION CONDITIONS
25-21
25.25.1
Machine-Check Architecture
25-22
25.25.2
Priority of Exceptions
25-22
25.25.3
Exception Conditions of Legacy SIMD Instructions Operating on MMX Registers
25-22
25.26
INTERRUPTS
25-27
25.26.1
Interrupt Propagation Delay
25-27
25.26.2
NMI Interrupts
25-27
25.26.3
IDT Limit
25-27
25.27
ADVANCED PROGRAMMABLE INTERRUPT CONTROLLER (APIC)
25-27
25.27.1
Software Visible Differences Between the Local APIC and the 82489DX
25-28
25.27.2
New Features Incorporated in the Local APIC for the P6 Family and Pentium Processors
25-28
25.27.3
New Features Incorporated in the Local APIC of the Pentium 4 and Intel Xeon Processors
25-28
25.28
TASK SWITCHING AND TSS
25-28
25.28.1
P6 Family and Pentium Processor TSS
25-29
25.28.2
TSS Selector Writes
25-29
25.28.3
Order of Reads/Writes to the TSS
25-29
25.28.4
Using A 16-Bit TSS with 32-Bit Constructs
25-29
25.28.5
Differences in I/O Map Base Addresses
25-29
25.29
CACHE MANAGEMENT
25-30
25.29.1
Self-Modifying Code with Cache Enabled
25-30
25.29.2
Disabling the L3 Cache
25-31
25.30
PAGING
25-31
25.30.1
Large Pages
25-31
25.30.2
PCD and PWT Flags
25-31
25.30.3
Enabling and Disabling Paging
25-32
25.31
STACK OPERATIONS AND SUPERVISOR SOFTWARE
25-32
25.31.1
Selector Pushes and Pops
25-32
25.31.2
Error Code Pushes
25-32
25.31.3
Fault Handling Effects on the Stack
25-33
25.31.4
Interlevel RET/IRET From a 16-Bit Interrupt or Call Gate
25-33
25.32
MIXING 16- AND 32-BIT SEGMENTS
25-33
25.33
SEGMENT AND ADDRESS WRAPAROUND
25-33
25.33.1
Segment Wraparound
25-34
25.34
STORE BUFFERS AND MEMORY ORDERING
25-34
25.35
BUS LOCKING
25-35
25.36
BUS HOLD
25-35
25.37
MODEL-SPECIFIC EXTENSIONS TO THE IA-32
25-35
25.37.1
Model-Specific Registers
25-36
25.37.2
RDMSR and WRMSR Instructions
25-36
xxiv Vol. 3A
CONTENTS
PAGE
25.37.3
Memory Type Range Registers
25-36
25.37.4
Machine-Check Exception and Architecture
25-36
25.37.5
Performance-Monitoring Counters
25-37
25.38
TWO WAYS TO RUN INTEL 286 PROCESSOR TASKS
25-37
25.39
INITIAL STATE OF PENTIUM, PENTIUM PRO AND PENTIUM 4 PROCESSORS
25-37
CHAPTER 26
INTRODUCTION TO VIRTUAL MACHINE EXTENSIONS
26.1
OVERVIEW
26-1
26.2
VIRTUAL MACHINE ARCHITECTURE
26-1
26.3
INTRODUCTION TO VMX OPERATION
26-1
26.4
LIFE CYCLE OF VMM SOFTWARE
26-2
26.5
VIRTUAL-MACHINE CONTROL STRUCTURE
26-2
26.6
DISCOVERING SUPPORT FOR VMX
26-2
26.7
ENABLING AND ENTERING VMX OPERATION
26-3
26.8
RESTRICTIONS ON VMX OPERATION
26-3
CHAPTER 27
VIRTUAL MACHINE CONTROL STRUCTURES
27.1
OVERVIEW
27-1
27.2
FORMAT OF THE VMCS REGION
27-2
27.3
ORGANIZATION OF VMCS DATA
27-3
27.4
GUEST-STATE AREA
27-4
27.4.1
Guest Register State
27-4
27.4.2
Guest Non-Register State
27-6
27.5
HOST-STATE AREA
27-9
27.6
VM-EXECUTION CONTROL FIELDS
27-10
27.6.1
Pin-Based VM-Execution Controls
27-10
27.6.2
Processor-Based VM-Execution Controls
27-10
27.6.3
Exception Bitmap
27-14
27.6.4
I/O-Bitmap Addresses
27-14
27.6.5
Time-Stamp Counter Offset and Multiplier
27-15
27.6.6
Guest/Host Masks and Read Shadows for CR0 and CR4
27-15
27.6.7
CR3-Target Controls
27-15
27.6.8
Controls for APIC Virtualization
27-15
27.6.9
MSR-Bitmap Address
27-17
27.6.10
Executive-VMCS Pointer
27-17
27.6.11
Extended-Page-Table Pointer (EPTP)
27-17
27.6.12
Virtual-Processor Identifier (VPID)
27-18
27.6.13
Controls for PAUSE-Loop Exiting
27-18
27.6.14
VM-Function Controls
27-18
27.6.15
VMCS Shadowing Bitmap Addresses
27-19
27.6.16
ENCLS-Exiting Bitmap
27-19
27.6.17
PCONFIG-Exiting Bitmap
27-19
27.6.18
Control Field for Page-Modification Logging
27-19
27.6.19
Controls for Virtualization Exceptions
27-19
27.6.20
XSS-Exiting Bitmap
27-19
27.6.21
Sub-Page-Permission-Table Pointer (SPPTP)
27-20
27.6.22
Fields Related to Hypervisor-Managed Linear-Address Translation
27-20
27.6.23
Fields Related to PASID Translation
27-21
27.6.24
Instruction-Timeout Control
27-21
27.6.25
Fields Controlling Virtualization of the IA32_SPEC_CTRL MSR
27-21
27.6.26
Fields Controlling SEAM Non-Root Operation
27-21
27.6.27
Fields Controlling APIC-Timer Virtualization
27-22
27.7
VM-EXIT CONTROL FIELDS
27-22
27.7.1
VM-Exit Controls
27-22
27.7.2
VM-Exit Controls for MSRs
27-24
27.8
VM-ENTRY CONTROL FIELDS
27-24
27.8.1
VM-Entry Controls
27-24
27.8.2
VM-Entry Controls for MSRs
27-25
27.8.3
VM-Entry Controls for Event Injection
27-26
27.9
VM-EXIT INFORMATION FIELDS
27-27
Vol. 3A xxv
CONTENTS
PAGE
27.9.1
Basic VM-Exit Information
27-27
27.9.2
Information for VM Exits Due to Vectored Events
27-28
27.9.3
Information for VM Exits That Occur During Event Delivery
27-29
27.9.4
Information for VM Exits Due to Instruction Execution
27-30
27.9.5
VM-Instruction Error Field
27-30
27.10
VMCS TYPES: ORDINARY AND SHADOW
27-31
27.11
SOFTWARE USE OF THE VMCS AND RELATED STRUCTURES
27-31
27.11.1
Software Use of Virtual-Machine Control Structures
27-31
27.11.2
VMREAD, VMWRITE, and Encodings of VMCS Fields
27-32
27.11.3
Initializing a VMCS
27-34
27.11.4
Software Access to Related Structures
27-34
27.11.5
VMXON Region
27-34
CHAPTER 28
VMX NON-ROOT OPERATION
28.1
INSTRUCTIONS THAT CAUSE VM EXITS
28-1
28.1.1
Relative Priority of Faults and VM Exits
28-1
28.1.2
Instructions That Cause VM Exits Unconditionally
28-2
28.1.3
Instructions That Cause VM Exits Conditionally
28-2
28.2
OTHER CAUSES OF VM EXITS
28-6
28.3
CHANGES TO INSTRUCTION BEHAVIOR IN VMX NON-ROOT OPERATION
28-8
28.4
OTHER CHANGES IN VMX NON-ROOT OPERATION
28-15
28.4.1
Event Blocking
28-15
28.4.2
Treatment of Task Switches
28-15
28.4.3
Shadow-Stack Updates
28-16
28.5
FEATURES SPECIFIC TO VMX NON-ROOT OPERATION
28-16
28.5.1
VMX-Preemption Timer
28-16
28.5.2
Monitor Trap Flag
28-17
28.5.3
Translation of Guest-Physical Addresses Using EPT
28-18
28.5.4
Translation of Guest-Physical Addresses Used by Intel Processor Trace
28-18
28.5.4.1
Guest-Physical Address Translation for Intel PT: Details
28-18
28.5.4.2
Trace-Address Pre-Translation (TAPT)
28-19
28.5.5
Translation of Guest-Physical Addresses Used by Architectural PEBS
28-19
28.5.6
APIC Virtualization
28-20
28.5.7
VM Functions
28-20
28.5.7.1
Enabling VM Functions
28-20
28.5.7.2
General Operation of the VMFUNC Instruction
28-20
28.5.7.3
EPTP Switching
28-21
28.5.8
Virtualization Exceptions
28-22
28.5.8.1
Convertible EPT Violations
28-22
28.5.8.2
Virtualization-Exception Information
28-23
28.5.8.3
Delivery of Virtualization Exceptions
28-24
28.5.9
PASID Translation
28-24
28.5.10
Guest Timer
28-25
28.5.10.1
Updating the Guest Deadline
28-25
28.5.10.2
Guest-Timer Events
28-26
28.6
UNRESTRICTED GUESTS
28-27
CHAPTER 29
VM ENTRIES
29.1
BASIC VM-ENTRY CHECKS
29-2
29.2
CHECKS ON VMX CONTROLS AND HOST-STATE AREA
29-2
29.2.1
Checks on VMX Controls
29-2
29.2.1.1
VM-Execution Control Fields
29-3
29.2.1.2
VM-Exit Control Fields
29-5
29.2.1.3
VM-Entry Control Fields
29-6
29.2.2
Checks on Host Control Registers, MSRs, and SSP
29-7
29.2.3
Checks on Host Segment and Descriptor-Table Registers
29-8
29.2.4
Checks Related to Address-Space Size
29-8
29.3
CHECKING AND LOADING GUEST STATE
29-8
29.3.1
Checks on the Guest State Area
29-9
29.3.1.1
Checks on Guest Control Registers, Debug Registers, and MSRs
29-9
xxvi Vol. 3A
CONTENTS
PAGE
29.3.1.2
Checks on Guest Segment Registers
29-10
29.3.1.3
Checks on Guest Descriptor-Table Registers
29-13
29.3.1.4
Checks on Guest RIP, RFLAGS, and SSP
29-13
29.3.1.5
Checks on Guest Non-Register State
29-13
29.3.1.6
Checks on Guest Page-Directory-Pointer-Table Entries
29-15
29.3.2
Loading Guest State
29-16
29.3.2.1
Loading Guest Control Registers, Debug Registers, and MSRs
29-16
29.3.2.2
Loading Guest Segment Registers and Descriptor-Table Registers
29-17
29.3.2.3
Loading Guest RIP, RSP, RFLAGS, and SSP
29-18
29.3.2.4
Loading Page-Directory-Pointer-Table Entries
29-18
29.3.2.5
Updating Non-Register State
29-19
29.3.3
Clearing Address-Range Monitoring
29-19
29.4
LOADING MSRS
29-19
29.5
TRACE-ADDRESS PRE-TRANSLATION (TAPT)
29-20
29.6
EVENT INJECTION
29-20
29.6.1
Injection of Interrupts and Exceptions
29-20
29.6.1.1
Details of Event Injection
29-21
29.6.1.2
VM Exits During Event Injection
29-23
29.6.1.3
Event Injection for VM Entries to Real-Address Mode
29-24
29.6.2
Injection of Pending MTF VM Exits
29-24
29.7
SPECIAL FEATURES OF VM ENTRY
29-24
29.7.1
Interruptibility State
29-24
29.7.2
Activity State
29-25
29.7.3
Delivery of Pending Debug Exceptions after VM Entry
29-26
29.7.4
VMX-Preemption Timer
29-26
29.7.5
Interrupt-Window Exiting and Virtual-Interrupt Delivery
29-27
29.7.6
NMI-Window Exiting
29-27
29.7.7
VM Exits Induced by the TPR Threshold
29-27
29.7.8
Pending MTF VM Exits
29-28
29.7.9
VM Entries and Advanced Debugging Features
29-28
29.7.10
User-Interrupt Recognition After VM Entry
29-28
29.8
VM-ENTRY FAILURES DURING OR AFTER LOADING GUEST STATE
29-28
29.9
MACHINE-CHECK EVENTS DURING VM ENTRY
29-29
CHAPTER 30
VM EXITS
30.1
ARCHITECTURAL STATE BEFORE A VM EXIT
30-1
30.2
RECORDING VM-EXIT INFORMATION AND UPDATING VM-ENTRY CONTROL FIELDS
30-4
30.2.1
Basic VM-Exit Information
30-4
30.2.2
Information for VM Exits Due to Vectored Events
30-12
30.2.3
Information About NMI Unblocking Due to IRET
30-13
30.2.4
Information for VM Exits During Event Delivery
30-14
30.2.5
Information for VM Exits Due to Instruction Execution
30-16
30.3
SAVING GUEST STATE
30-22
30.3.1
Saving Control Registers, Debug Registers, and MSRs
30-24
30.3.2
Saving Segment Registers and Descriptor-Table Registers
30-25
30.3.3
Saving RIP, RSP, RFLAGS, and SSP
30-25
30.3.4
Saving Non-Register State
30-27
30.4
SAVING MSRS
30-29
30.5
LOADING HOST STATE
30-29
30.5.1
Loading Host Control Registers, Debug Registers, MSRs
30-30
30.5.2
Loading Host Segment and Descriptor-Table Registers
30-31
30.5.3
Loading Host RIP, RSP, RFLAGS, and SSP
30-32
30.5.4
Checking and Loading Host Page-Directory-Pointer-Table Entries
30-32
30.5.5
Updating Non-Register State
30-33
30.5.6
Clearing Address-Range Monitoring
30-33
30.6
LOADING MSRS
30-33
30.7
VMX ABORTS
30-34
30.8
MACHINE-CHECK EVENTS DURING VM EXIT
30-35
30.9
USER-INTERRUPT RECOGNITION AFTER VM EXIT
30-35
Vol. 3A xxvii
CONTENTS
PAGE
CHAPTER 31
VMX SUPPORT FOR ADDRESS TRANSLATION
31.1
VIRTUAL PROCESSOR IDENTIFIERS (VPIDS)
31-1
31.2
HYPERVISOR-MANAGED LINEAR-ADDRESS TRANSLATION (HLAT)
31-1
31.3
THE EXTENDED PAGE TABLE MECHANISM (EPT)
31-2
31.3.1
EPT Overview
31-2
31.3.2
EPT Translation Mechanism
31-3
31.3.3
EPT-Induced VM Exits
31-10
31.3.3.1
EPT Misconfigurations
31-10
31.3.3.2
EPT Violations
31-12
31.3.3.3
Prioritization of EPT Misconfigurations and EPT Violations
31-15
31.3.4
Sub-Page Write Permissions
31-16
31.3.4.1
Write Accesses That Are Eligible for Sub-Page Write Permissions
31-17
31.3.4.2
Determining an Access’s Sub-Page Write Permission
31-17
31.3.5
Accessed and Dirty Flags for EPT
31-18
31.3.6
Page-Modification Logging
31-19
31.3.7
EPT and Memory Typing
31-19
31.3.7.1
Memory Type Used for Accessing EPT Paging Structures
31-19
31.3.7.2
Memory Type Used for Translated Guest-Physical Addresses
31-19
31.4
CACHING TRANSLATION INFORMATION
31-20
31.4.1
Information That May Be Cached
31-20
31.4.2
Creating and Using Cached Translation Information
31-21
31.4.3
Invalidating Cached Translation Information
31-22
31.4.3.1
Operations that Invalidate Cached Mappings
31-22
31.4.3.2
Operations that Need Not Invalidate Cached Mappings
31-24
31.4.3.3
Guidelines for Use of the INVVPID Instruction
31-24
31.4.3.4
Guidelines for Use of the INVEPT Instruction
31-25
CHAPTER 32
APIC VIRTUALIZATION AND VIRTUAL INTERRUPTS
32.1
VIRTUAL APIC STATE
32-1
32.1.1
Virtualized APIC Registers
32-2
32.1.2
TPR Virtualization
32-2
32.1.3
PPR Virtualization
32-2
32.1.4
EOI Virtualization
32-3
32.1.5
Self-IPI Virtualization
32-3
32.1.6
IPI Virtualization
32-3
32.1.6.1
Virtual-Interrupt Posting
32-4
32.1.6.2
IPI Virtualization Using Virtual-Interrupt Posting
32-4
32.2
EVALUATION AND DELIVERY OF VIRTUAL INTERRUPTS
32-5
32.2.1
Evaluation of Pending Virtual Interrupts
32-5
32.2.2
Virtual-Interrupt Delivery
32-6
32.2.3
Virtualizing User-Interrupt Notifications
32-7
32.3
VIRTUALIZING CR8-BASED TPR ACCESSES
32-7
32.4
VIRTUALIZING MEMORY-MAPPED APIC ACCESSES
32-8
32.4.1
Priority of APIC-Access VM Exits
32-9
32.4.2
Virtualizing Reads from the APIC-Access Page
32-9
32.4.3
Virtualizing Writes to the APIC-Access Page
32-10
32.4.3.1
Determining Whether a Write Access is Virtualized
32-10
32.4.3.2
APIC-Write Emulation
32-11
32.4.3.3
APIC-Write VM Exits
32-12
32.4.4
Instruction-Specific Considerations
32-12
32.4.5
Issues Pertaining to Page Size and TLB Management
32-13
32.4.6
APIC Accesses Not Directly Resulting From Linear Addresses
32-13
32.4.6.1
Guest-Physical Accesses to the APIC-Access Page
32-14
32.4.6.2
Physical Accesses to the APIC-Access Page
32-14
32.5
VIRTUALIZING MSR-BASED APIC ACCESSES
32-15
32.6
POSTED-INTERRUPT PROCESSING
32-16
32.7
VIRTUALIZING SENDUIPI
32-18
xxviii Vol. 3A
CONTENTS
PAGE
CHAPTER 33
VMX INSTRUCTION REFERENCE
33.1
OVERVIEW
33-1
33.2
CONVENTIONS
33-2
33.3
VMX INSTRUCTIONS
33-2
INVEPT- Invalidate Translations Derived from EPT
33-3
INVVPID- Invalidate Translations Based on VPID
33-6
VMCALL-Call to VM Monitor
33-9
VMCLEAR-Clear Virtual-Machine Control Structure
33-11
VMFUNC-Invoke VM function
33-13
VMLAUNCH/VMRESUME-Launch/Resume Virtual Machine
33-14
VMPTRLD-Load Pointer to Virtual-Machine Control Structure
33-17
VMPTRST-Store Pointer to Virtual-Machine Control Structure
33-19
VMREAD-Read Field from Virtual-Machine Control Structure
33-21
VMRESUME-Resume Virtual Machine
33-23
VMWRITE-Write Field to Virtual-Machine Control Structure
33-24
VMXOFF-Leave VMX Operation
33-26
VMXON-Enter VMX Operation
33-28
33.4
VM INSTRUCTION ERROR NUMBERS
33-30
CHAPTER 34
SYSTEM MANAGEMENT MODE
34.1
SYSTEM MANAGEMENT MODE OVERVIEW
34-1
34.1.1
System Management Mode and VMX Operation
34-2
34.2
SYSTEM MANAGEMENT INTERRUPT (SMI)
34-2
34.3
SWITCHING BETWEEN SMM AND THE OTHER PROCESSOR OPERATING MODES
34-2
34.3.1
Entering SMM
34-2
34.3.2
Exiting From SMM
34-3
34.4
SMRAM
34-4
34.4.1
SMRAM State Save Map
34-4
34.4.1.1
SMRAM State Save Map and Intel 64 Architecture
34-6
34.4.2
SMRAM Caching
34-8
34.4.2.1
System Management Range Registers (SMRR)
34-9
34.5
SMI HANDLER EXECUTION ENVIRONMENT
34-9
34.5.1
Initial SMM Execution Environment
34-10
34.5.2
SMI Handler Operating Mode Switching
34-11
34.5.3
Control-flow Enforcement Technology Interactions
34-11
34.6
EXCEPTIONS AND INTERRUPTS WITHIN SMM
34-11
34.7
MANAGING SYNCHRONOUS AND ASYNCHRONOUS SYSTEM MANAGEMENT INTERRUPTS
34-12
34.7.1
I/O State Implementation
34-12
34.8
NMI HANDLING WHILE IN SMM
34-13
34.9
SMM REVISION IDENTIFIER
34-13
34.10
AUTO HALT RESTART
34-14
34.10.1
Executing the HLT Instruction in SMM
34-15
34.11
SMBASE RELOCATION
34-15
34.12
I/O INSTRUCTION RESTART
34-15
34.12.1
Back-to-Back SMI Interrupts When I/O Instruction Restart Is Being Used
34-16
34.13
SMM MULTIPLE-PROCESSOR CONSIDERATIONS
34-16
34.14
DEFAULT TREATMENT OF SMIS AND SMM WITH VMX OPERATION AND SMX OPERATION
34-17
34.14.1
Default Treatment of SMI Delivery
34-17
34.14.2
Default Treatment of RSM
34-18
34.14.3
Protection of CR4.VMXE in SMM
34-19
34.14.4
VMXOFF and SMI Unblocking
34-19
34.15
DUAL-MONITOR TREATMENT OF SMIs AND SMM
34-19
34.15.1
Dual-Monitor Treatment Overview
34-19
34.15.2
SMM VM Exits
34-20
34.15.2.1
Architectural State Before a VM Exit
34-20
34.15.2.2
Updating the Current-VMCS and Executive-VMCS Pointers
34-20
34.15.2.3
Recording VM-Exit Information
34-20
34.15.2.4
Saving Guest State
34-21
34.15.2.5
Updating State
34-22
34.15.3
Operation of the SMM-Transfer Monitor
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Vol. 3A xxix