connected to one or more levels of larger
busses), used to increase the number of el-
ements that may be connected to a high-
performance bus structure.
bus idle
the condition that exists when
the bus is not in use.
bus impedance matrix
See
Z-bus
.
bus interface unit
in modern CPU im-
plementations, the module within the CPU
directly responsible for interactions between
the CPU and the memory bus.
bus line
one of the wires or conductors
that constitute a bus. A bus line may be used
for data, address, control, or timing.
bus locking
the action of retaining con-
trol of a bus after an operation which would
normally release the bus at completion. In
the manipulation of memory locks, a memory
read must be followed by a write to the same
location with a guarantee of no intervening
operation. The bus must be locked from the
initial read until after the update write to give
an indivisible read/write to memory.
bus master
a bus device whose request
is granted by the bus controller and thereby
gains control of the bus for one or more cy-
cles or transfers. The bus master may always
reside with one subsystem, or may be trans-
ferred between subsystems, depending on the
architecture of the bus control logic. See also
bus controller
,
bus cycle
.
bus owner
the entity that has exclusive
access to a bus at a given time.
bus phase
a term applying especially to
synchronous buses, controlled by a central
clock, with alternating “address” and “data”
transfers.
A single transfer operation re-
quires the two phases to transfer first the ad-
dress and then the associated data. Bus ar-
bitration may be overlapped with preceding
operations.
bus priority
rules for deciding the prece-
dence of devices in having bus requests hon-
ored.
Devices issue requests on one of several
bus request lines, each with a different bus
priority. A high priority request then “wins”
over a simultaneous request at a lower prior-
ity.
The request grant signals then “daisy
chains” through successive devices along the
bus or is sent directly to devices in appropri-
ate order. The requesting device closest to
the bus controller then accepts the grant and
blocks its propagation along the bus.
Buses may have handle interrupts and di-
rect memory accesses with separate priority
systems.
bus protocol
(1) a set of rules that two
parties use to communicate.
(2) the set of rules that define precisely
the bus signals that have to be asserted by the
master and slave devices in each phase of a
bus operation.
bus request
an input signal to a processor
that requests access to the bus; a hold signal.
Competing bus requests are resolved by the
bus controller. See also
bus controller
.
bus slave
a device that responds to a re-
quest issued by the bus master. See also
bus
master
.
bus snooping
the action of monitoring
all traffic on a bus, irrespective of the ad-
dress. Bus snooping is required where there
are several caches with the same or overlap-
ping address ranges. Each cache must then
“snoop” on the bus to check for writes to ad-
dresses it holds; conflicting addresses may be
updated or may be purged from the cache.
Bus snooping is also useful as a diagnostic
tool.
bus state triggering
a data acquisition
mode initiated when a specific digital code is
selected.
c
2000 by CRC Press LLC